Error Syndrome Register; Defaults Register 1 - Motorola MVME1X7P Programmer's Reference Manual

MCECC Functions

Error Syndrome Register

ADR/SIZ
BIT
NAME
4
OPER
RESET

Defaults Register 1

ADR/SIZ
BIT
NAME
OPER
RESET
4-30
1st $FFF43070/2nd $FFF43170 (16-bits)
31 30 29
0 S6 S5
R R R
0 PLS 0 PLS 0 PLS
S6-S0 Bits SYNDROME6-0 reflect the syndrome value at the last
logging of an error. The seven-bit code indicates the
position of the data error. When all the bits are 0, there is
no error. Note that if the logged error was non-
correctable, then these bits are meaningless (refer to the
Syndrome Decoding
1st $FFF43074/2nd $FFF43174 (8-bits)
31 30
RWB7 RWB6
R/W R/W
0 PL V PLS
It is not recommended that non-test software write to this register.
RSIZ2-RSIZ0
Bits RSIZ2-RSIZ0 determine the size of the DRAM array
that is assumed by the MCECC. They control the size as
follows:
28 27
S4 S3
R R
0 PLS 0 PLS
section).
29 28 27
FSTRD SELI1 SELI0 RSIZ2 RSIZ1 RSIZ0
R/W R/W R/W
V PLS V PLS V PLS V PLS V PLS V PLS
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26 25 24
S2 S1 S0
R R R
0 PLS 0 PLS 0 PLS
26 25 24
R/W R/W R/W