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BBRAM Interface
The PCCchip2 provides a read/write interface to the BBRAM by any bus
master on the MC68040 bus. The PCCchip2 performs dynamic sizing for
accesses to the 8-bit BBRAM to make it appear contiguous. This feature
allows code to be executable from the BBRAM. The BBRAM device
access time must be no greater than 5 BCLK periods in fast mode or 9
BCLK periods in slow mode. The BBRAM speed option is controlled by
a control bit in the General Control Register.
82596CA LAN Controller Interface
The LAN controller interface is described in the following sections.
MPU Port and MPU Channel Attention
The PCCchip2 allows the (MC68040-compatible) Local Bus master to
communicate directly with the Intel 82596CA LAN Coprocessor by
providing a map decoder and required control and timing logic. Two types
of direct access are feasible with the 82596CA: MPU Port and MPU
Attention.
MPU Port access enables the MPU to write to an internal, 32-bit 82596CA
command register. This allows the MPU to do four things:
1. Write an alternate System Configuration Pointer address.
2. Write an alternative dump area pointer and perform a dump.
3. Execute a software reset.
4. Execute a self-test.
Each Port access must consist of two 16-bit writes: Upper Command Word
(two bytes) and Lower Command Word (two bytes). The Upper Command
Word (two bytes) is mapped at $FFF46000 and the Lower Command
Word (two bytes) is mapped at $FFF46002.
The PCCchip2 only supports (decodes) MPU Port writes. It does not
decode MPU Port reads. (Nor does the 82596CA support MPU Port reads.)
http://www.motorola.com/computer/literature
Functional Description
3-3
3
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