Dmac Registers; Eprom Decoder, Sram And Dma Control Register; Table 2-3. Dmac Command Packet Format - Motorola MVME1X7P Programmer's Reference Manual

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Entry
0 (bits 0-15)
1 (bits 0-31)
2 (bits 0-31)
3 (bits 0-31)
4 (bits 0-31)

DMAC Registers

This section provides addresses and bit level descriptions of the DMAC
counters, control registers, and status registers. Other control functions are
also included in this section.

EPROM Decoder, SRAM and DMA Control Register

ADR/SIZ
BIT
23
NAME
OPER
RESET
This register controls the snoop control bits used by the DMAC when it is
accessing table entries.
SRAMS
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Table 2-3. DMAC Command Packet Format

--
Address of Next Command Packet
$FFF40030 (8 bits [6 used] of 32)
22 21 20
WAIT RMW ROM0
R/W R/W
0 PSL 1 PSL
These VMEchip2 bits are not used on the MVME1x7P.
LCSR Programming Model
Function
Control Word
Local Bus Address
VMEbus Address
Byte Count
19 18
TBLSC
R/W
0 PS
17 16
SRAMS
R/W
0 PS
2-53
2