GCSR Programming Model .................................................................................. 2-100
Programming the GCSR................................................................................. 2-102
VMEchip2 ID Register ........................................................................... 2-104
CHAPTER 3
PCCchip2
Introduction ............................................................................................................... 3-1
Functional Description .............................................................................................. 3-2
General Description............................................................................................ 3-2
BBRAM Interface .............................................................................................. 3-3
LANC Bus Error ......................................................................................... 3-4
LANC Interrupt ........................................................................................... 3-5
Parallel Port Interface ......................................................................................... 3-6
CD2401 SCC Interface....................................................................................... 3-7
Tick Timer .......................................................................................................... 3-9
Overall Memory Map .............................................................................................. 3-10
Programming Model................................................................................................ 3-11
Chip ID Register............................................................................................... 3-14
Chip Revision Register..................................................................................... 3-14
Vector Base Register ........................................................................................ 3-16
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