Motorola MVME1X7P Manuals

Manuals and User Guides for Motorola MVME1X7P. We have 1 Motorola MVME1X7P manual available for free PDF download: Programmer's Reference Manual

Motorola MVME1X7P Programmer's Reference Manual

Motorola MVME1X7P Programmer's Reference Manual (316 pages)

Single-Board Computer

Brand: Motorola | Category: Desktop | Size: 3 MB

Table of Contents

Do Not Substitute Parts or Modify Equipment
3
Ground the Instrument
3
Safety Summary
3
Emi Caution
4
Table of Contents
7
List of Figures
17
About this Manual

21
CHAPTER 1 Programming Issues

27
- Introduction
  27
- Programming Interfaces
  33
  - Mc680X0 Mpu
    33
  - Data Bus Structure
    33
  - Eeproms on the MVME1X7P
    34
    
    Mvme167
    34
    
    Mvme177
    35
  - Flash Memory on the MVME177
    35
  - Sram
    36
  - Figure 1-3. MVME177 Flash and EPROM Memory Mapping Schemes
    36
  - Onboard SDRAM
    37
  - Battery-Backed-Up RAM and Clock
    38
  - Vmebus Interface
    38
  - I/O Interfaces
    38
    
    Serial Port Interface
    39
    
    Parallel (Printer) Interface
    40
    
    Ethernet Interface
    41
    
    SCSI Interface
    42
  - Local Resources
    42
    
    Programmable Tick Timers
    42
    
    Watchdog Timer
    43
    
    Software-Programmable Hardware Interrupts
    43
    
    Local Bus Timeout
    43
- Functional Description
  43
  - Vmebus Interface and Vmechip2
    44
    
    Vmechip2 General-Purpose I/O
    44
    
    Petra/Vmechip2 Redundant Logic
    44
    
    Table 1-2. Functions Duplicated in Vmechip2 and Petra Asics
    45
- Memory Maps
  46
  - Local Bus Memory Map
    46
    
    Normal Address Range
    46
    
    Table 1-3. Local Bus Memory Map
    47
    
    Table 1-4. Local I/O Devices Memory Map
    48
    
    Detailed I/O Memory Maps
    51
    
    Table 1-5. Vmechip2 Memory Map (Sheet 1 of 3)
    52
    
    Table 1-6. Printer Memory Map
    57
    
    Table 1-7. Pccchip2 Memory Map
    58
    
    Table 1-8. MCECC Internal Register Memory Map
    60
    
    Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map
    62
    
    Table 1-10. 82596CA Ethernet LAN Memory Map
    66
    
    BBRAM/TOD Clock Memory Map
    67
    
    Table 1-11. 53C710 SCSI Memory Map
    67
    
    Table 1-12. M48T58 BBRAM,TOD Clock Memory Map
    68
    
    Table 1-13. BBRAM Configuration Area Memory Map
    68
    
    Table 1-14. TOD Clock Memory Map
    69
    
    Interrupt Acknowledge Map
    72
  - Vmebus Memory Map
    72
    
    Vmebus Accesses to the Local Bus
    72
    
    Vmebus Short I/O Memory Map
    72
- Interrupt Handling
  73
  - Example: Vmechip2 Tick Timer 1 Periodic Interrupt
    73
- Cache Coherency (MVME167P)
  75
- Cache Coherency (MVME177P)
  76
- Using Bus Timers
  77
- Indivisible Cycles
  78
- Table 1-15. Single-Cycle Instructions
  78
- Supervisor Stack Pointer (MC68060)
  79
- Sources of Local Bus Errors
  80
  - Local Bus Timeout
    80
  - Vmebus Access Timeout
    80
  - Vmebus BERR
    80
  - Vmechip2
    81
  - Bus Error Processing
    81
- Error Conditions
  81
  - MPU Parity Error
    82
  - MPU Offboard Error
    82
  - MPU TEA - Cause Unidentified
    82
  - MPU Local Bus Time-Out
    83
  - DMAC Vmebus Error
    83
  - DMAC Parity Error
    83
  - DMAC Offboard Error
    84
  - DMAC LTO Error
    84
  - DMAC TEA - Cause Unidentified
    85
  - SCC Retry Error
    85
  - SCC Parity Error
    86
  - SCC Offboard Error
    86
  - SCC LTO Error
    87
  - LAN Parity Error
    87
  - LAN Offboard Error
    87
  - LAN LTO Error
    88
  - SCSI Parity Error
    88
  - SCSI Offboard Error
    88
  - SCSI LTO Error
    89
CHAPTER 2 Vmechip2

91
CHAPTER 3 Pccchip2

199
- Introduction
  199
  - Summary of Major Features
    199
- Functional Description
  200
  - General Description
    200
  - Figure 3-1. Pccchip2 Block Diagram
    200
  - BBRAM Interface
    201
  - 82596CA LAN Controller Interface
    201
    
    MPU Port and MPU Channel Attention
    201
    
    MC68040-Bus Master Support for 82596CA
    202
    
    LANC Bus Error
    202
    
    LANC Interrupt
    203
  - 53C710 SCSI Controller Interface
    204
  - Parallel Port Interface
    204
  - General Purpose I/O Pin
    205
  - CD2401 SCC Interface
    205
  - Tick Timer
    207
- Overall Memory Map
  208
- Table 3-1. Pccchip2 Devices Memory Map
  208
- Programming Model
  209
  - Table 3-2. Pccchip2 Memory Map - Control and Status Registers
    210
  - Chip ID Register
    212
  - Chip Revision Register
    212
  - General Control Register
    213
  - Vector Base Register
    214
  - Programming the Tick Timers
    216
    
    Tick Timer 1 Compare Register
    216
    
    Tick Timer 1 Counter
    217
    
    Tick Timer 2 Compare Register
    217
    
    Tick Timer 2 Counter
    218
    
    Prescaler Count Register
    218
    
    Prescaler Clock Adjust Register
    218
    
    Tick Timer 2 Control Register
    220
    
    Tick Timer 1 Control Register
    221
    
    General Purpose Input Interrupt Control Register
    222
    
    General Purpose Input/Output Pin Control Register
    223
    
    Tick Timer 2 Interrupt Control Register
    223
    
    Tick Timer 1 Interrupt Control Register
    224
  - SCC Error Status and Interrupt Control Registers
    225
    
    SCC Error Status Register
    225
    
    SCC Modem Interrupt Control Register
    226
    
    SCC Transmit Interrupt Control Register
    227
    
    SCC Receive Interrupt Control Register
    228
    
    Modem PIACK Register
    229
    
    Transmit PIACK Register
    230
    
    Receive PIACK Register
    231
  - LANC Error Status and Interrupt Control Registers
    232
    
    LANC Error Status Register
    232
    
    82596CA LANC Interrupt Control Register
    233
    
    LANC Bus Error Interrupt Control Register
    234
  - Programming the SCSI Error Status and Interrupt Registers
    235
    
    SCSI Error Status Register
    235
    
    SCSI Interrupt Control Register
    236
  - Programming the Printer Port
    237
    
    Printer ACK Interrupt Control Register
    237
    
    Printer FAULT Interrupt Control Register
    238
    
    Printer SEL Interrupt Control Register
    239
    
    Printer PE Interrupt Control Register
    240
    
    Printer BUSY Interrupt Control Register
    241
    
    Printer Input Status Register
    242
    
    Printer Port Control Register
    243
    
    Chip Speed Register
    244
    
    Printer Data Register
    245
    
    Interrupt Priority Level Register
    246
    
    Interrupt Mask Level Register
    247
CHAPTER 4 MCECC Functions

249
- Introduction
  249
- Features
  250
- Table 4-1. MCECC Functions on the Petra ASIC
  250
- Functional Description
  251
  - General Description
    251
  - Performance
    251
  - Cache Coherency
    252
  - Table 4-2. Memory System Cycle Timing
    252
  - Ecc
    253
    
    Cycle Types
    253
    
    Error Reporting
    253
    
    Single Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    253
    
    Double Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    254
    
    Triple (or Greater) Bit Error (Cycle Type = Burst Read or Non-Burst Read)
    254
    
    Cycle Type = Burst Write
    254
    
    Single Bit Error (Cycle Type = Non-Burst Write)
    254
    
    Double Bit Error (Cycle Type = Non-Burst Write)
    254
    
    Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write)
    255
    
    Single Bit Error (Cycle Type = Scrub)
    255
    
    Double Bit Error (Cycle Type = Scrub)
    255
    
    Triple (or Greater) Bit Error (Cycle Type = Scrub)
    255
  - Error Logging
    256
  - Scrub
    256
  - Refresh
    256
  - Arbitration
    257
  - Chip Defaults
    257
- Programming Model
  258
  - Table 4-3. MCECC Sector Internal Register Memory Map
    259
  - Chip ID Register
    261
  - Chip Revision Register
    261
  - Memory Configuration Register
    262
  - Base Address Register
    263
  - DRAM Control Register
    263
  - BCLK Frequency Register
    264
  - Data Control Register
    265
  - Scrub Control Register
    267
  - Scrub Period Register Bits 15-8
    268
  - Scrub Period Register Bits 7-0
    268
  - Chip Prescaler Counter
    269
  - Scrub Time On/Time off Register
    269
  - Scrub Prescaler Counter (Bits 15-8)
    271
  - Scrub Prescaler Counter (Bits 21-16)
    271
  - Scrub Prescaler Counter (Bits 7-0)
    272
  - Scrub Timer Counter (Bits 15-8)
    272
  - Scrub Address Counter (Bits 26-24)
    273
  - Scrub Timer Counter (Bits 7-0)
    273
  - Scrub Address Counter (Bits 15-8)
    274
  - Scrub Address Counter (Bits 7-4)
    274
  - Error Logger Register
    275
  - Error Address (Bits 23-16)
    276
  - Error Address (Bits 31-24)
    276
  - Error Address (Bits 15-8)
    277
  - Error Address (Bits 7-4)
    277
  - Defaults Register 1
    278
  - Error Syndrome Register
    278
  - Defaults Register 2
    280
  - SDRAM Configuration Register
    281
  - Initialization
    282
- Syndrome Decoding
  284
- Table 4-4. Syndrome Bit Encoding
  284
- Table 4-5. Identifying SDRAM Bank in Error
  285
APPENDIX A Summary of Changes

287
- Introduction
  287
  - Table A-1. List of Changes
    287
APPENDIX B Printer and Serial Port Connections

289
APPENDIX C Related Documentation

299
- MCG Documents
  299
  - Table C-1. Motorola Computer Group Documents
    299
- Manufacturers' Documents
  300
  - Table C-2. Manufacturers' Documents
    300
- Related Specifications
  301
  - Table C-3. Related Specifications
    301

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