Lanc Error Status And Interrupt Control Registers; Lanc Error Status Register - Motorola MVME1X7P Programmer's Reference Manual

PCCchip2

LANC Error Status and Interrupt Control Registers

3

LANC Error Status Register

ADR/SIZ
BIT
NAME
OPER
RESET
3-34
This section provides addresses and bit level descriptions of the LANC
interrupt control registers and status register.
31 30 29
R R
0 0
SCLR Writing a 1 to this bit clears bits 25 through 27 (LTO,
EXT, and PRTY). Reading this bit always yields 0.
These bits indicate the status of the last Local Bus error
LTO,EXT,PRTY
condition encountered by the LANC while performing
DMA accesses to the Local Bus.
A Local Bus error condition is flagged by the assertion of
TEA*.
When the LANC receives TEA*:
Writing a 1 to bit 24 (SCLR) also clears all three bits.
$FFF42028 (8 bits)
28 27
PRTY
R R R
0 0 0 PL
If the source of the error is local time-out,
then LTO is set and EXT and PRTY are
cleared.
If the source of the TEA* is due to an error in
going to the VMEbus, then EXT is set and the
other two status bits are cleared.
If the source of the error is DRAM parity
check error, then PRTY is set and the other
two status bits are cleared.
If the source of the error is none of the above
conditions, then all three bits are cleared.
Computer Group Literature Center Web Site
26 25 24
EXT LTO SCLR
R R W/R-0
0 PL 0 PL 0