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VMEchip2
2
2-6
Using the four programmable map decoders, separate VMEbus maps can
be created, each with its own attributes. For example, one map can be
configured as A32, D32 with write posting enabled while a second map
can be A24, D16 with write posting disabled.
The first I/O map decoder decodes local bus addresses $FFFF0000 through
$FFFFFFFF as the short I/O A16/D16 or A16/D32 area. The other
provides an A24/D16 space at $F0000000 to $F0FFFFFF and an A32/D16
space at $F1000000 to $FF7FFFFF.
Supervisor/non-privileged and program/data space is determined by
attribute bits. Write posting may be enabled or disabled for each decoder
I/O space and this map decoder may be enabled or disabled.
When write posting is enabled, the VMEchip2 stores the local bus address
and data and then acknowledges the local bus master. The local bus is then
free to perform other operations while the VMEbus master requests the
VMEbus and performs the requested operation.
The write post buffer stores data in single-byte, double-byte, quad-byte, or
one-cache-line (four quad-bytes) form. Write posting should only be
enabled when bus errors are not expected. If a bus error is returned on a
write posted cycle and the interrupt is enabled, the local processor is
interrupted. The address of the error is not saved. Normal memory never
returns a bus error on a write cycle. However, some VMEbus ECC
memory cards perform a read-modify-write operation and therefore may
return a bus error if there is an error on the read portion of a read-modify-
write. Write posting should not be enabled when this type of memory card
is used. Also, memory should not be sized using write operations if write
posting is enabled. I/O areas that have holes should not be write posted if
software may access non-existent memory. Using the programmable map
decoders, write posting can be enabled for "safe" areas and disabled for
areas which are not "safe".
Block transfer is not supported because the MC680x0 block transfer
capability is not compatible with the VMEbus.
The VMEbus master supports dynamic bus sizing. When a local device
initiates a quad-byte access to a VMEbus slave that only has the D16 data
transfer capability, the chip executes two double-byte cycles on the
VMEbus, acknowledging the local device after all requested four-bytes
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