Programming The Tick And Watchdog Timers; Vmebus Arbiter Time-Out Control Register - Motorola MVME1X7P Programmer's Reference Manual

VMEchip2
2

Programming the Tick and Watchdog Timers

VMEbus Arbiter Time-Out Control Register

ADR/SIZ
BIT
NAME
OPER
RESET
2-64
DLPE If this bit is set, the DMAC has received a TEA and the
status indicated a parity error during a DRAM data
transfer. This bit is cleared when the DMAC is enabled.
DLBE If this bit is set, the DMAC has received a TEA and no
additional status was provided. This bit is cleared when
the DMAC is enabled.
MLTO If this bit is set, the MPU has received a TEA and the
status indicated a local bus time-out. This bit is cleared by
writing a 1 to the MCLR bit in this register.
The VMEchip2 has two 32-bit tick timers and one watchdog timer. This
section provides addresses and bit level descriptions of the prescaler, tick
timer, watchdog timer registers, and various other timer registers.
$FFF4004C (8 bits [1 used] of 32)
31 30 29
This register controls the VMEbus arbiter time-out timer.
ARBTO When this bit is high, the VMEbus grant time-out timer is
enabled. When this bit is low, the VMEbus grant timer is
disabled. When the timer is enabled and the arbiter does
not receive a BBSY signal within 256 s after a grant is
issued, the arbiter asserts BBSY and removes the grant.
The arbiter then rearbitrates any pending requests.
28 27 26
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25 24
ARBTO
R/W
0 PS