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Programming Issues
1
VMEbus Interface and VMEchip2
VMEchip2 General-Purpose I/O
Petra/VMEchip2 Redundant Logic
1-18
The local-bus-to-VMEbus interface and the VMEbus-to-local-bus
interface are provided by the VMEchip2 ASIC. The VMEchip2 can also
provide the VMEbus system controller functions. Refer to the VMEchip2
description in Chapter 2 for detailed programming information.
The MVME1X7P single-board computers, both MVME167P and
MVME177P, follow the previous MVME177 in their routing of GPIO
signals:
GPIO1 controls Flash memory write protection.
GPIO3 selects between shared EPROM/Flash mode or Flash-only
mode.
GPIO2 controls whether the upper or lower Flash addresses are used
in shared EPROM/Flash mode.
GPIO0's function as +12V power status signal is unchanged.
In support of possible future configurations in which the MVME1X7P
might be offered as a single-board computer without the VMEbus
interface, certain logic in the VMEchip2 has been duplicated in the Petra
chip.
Table 1-2
shows the location of the overlapping logic. As long as the
VMEchip2 ASIC is present, the redundant logic is inhibited in the Petra
chip.
Note that the
switch logic in the VMEchip2 is not used. Likewise
ABORT
unused are the GPI inputs to the VMEchip2, which are located at
$FFF40088 bits 7-0. Instead, the
the Petra ASIC at location $FFF42043. The GPI inputs are integrated into
the Petra ASIC at location $FFF4202C bits 23-16.
switch interrupt is integrated into
ABORT
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