Scc Modem Interrupt Control Register - Motorola MVME1X7P Programmer's Reference Manual

PCCchip2

SCC Modem Interrupt Control Register

ADR/SIZ
BIT
3
NAME
OPER
RESET
3-28
23 22 21
IRQ
R R
0 0
IL2-IL0 Interrupt Request Level. These three bits select the
interrupt level for SCC modem Interrupt. Level 0 does not
generate an interrupt.
AVEC When this bit is high, the PCCchip2 supplies the interrupt
vector to the MPU during an IACK for SCC modem
interrupt. When this bit is low, the PCCchip2 obtains the
vector from the SCC and passes it to the MPU. The use of
the AVEC mode is not recommended.
IEN Interrupt Enable. When this bit is high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
IRQ Interrupt Status. This status bit reflects the state of the
SCC-IRQ1 pin of the CD2401 (qualified by the IEN bit).
When this bit is high, an SCC modem interrupt is being
generated at the level programmed in IL2-IL0 (if
nonzero). This status bit does not need to be cleared,
because it is not edge-sensitive.
$FFF4201D (8 bits)
20 19
IEN AVEC
R R/W R/W
X 0 PL 0 PL
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18 17 16
IL2 IL1 IL0
R/W R/W R/W
0 PL 0 PL 0 PL