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Interrupt Handling
M68000-based systems use hardware-vectored interrupts. Board MPUs
from the M68000 family require that the C040 bit in the PCCchip2 General
Control register (address $FFF42002) be set. For more information, refer
to the
Most interrupt sources are level and base vector programmable. Interrupt
vectors from the PCCchip2 and VMEchip2 ASICs have two sections:
Base value
Lower bits
There is a hierarchy of interrupt sources, prioritized as follows:
Highest priority
Lowest priority
The MC68040 and MC68060 processors employ a seven-level prioritized,
hardware-vectored interrupt scheme that is standard in the M68000 family.
The Local Bus distinguishes interrupt acknowledge cycles from other
cycles by placing the binary value %11 on TT1-TT0. It also specifies the
level that is being acknowledged using TM2-TM0. The interrupt handler
selects which device within that level is being acknowledged.
Example: VMEchip2 Tick Timer 1 Periodic Interrupt
This section describes the use of interrupts on MVME167P and
MVME177P single-board computers. The following example illustrates
how to generate and handle a VMEchip2 Tick Timer 1 interrupt on
M68000-based single-board computers such as the MVME1X7P. Specific
values are given for the register writes. It is advisable to read this entire
section before you perform any of these procedures.
http://www.motorola.com/computer/literature
General Control Register
Can be set by the processor, usually the upper four
bits
Set according to the particular interrupt source
Interrupts from the PCCchip2
Interrupt sources from the VMEchip2
section in
Chapter 3,
PCCchip2.
Interrupt Handling
1-47
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