Data Control Register - Motorola MVME1X7P Programmer's Reference Manual

Note
ADR/SIZ
BIT 31
NAME
BCK7
OPER R/W
RESET
0 P

Data Control Register

ADR/SIZ
BIT
31
NAME
0
OPER R
RESET
X
RWCKB
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This register is configured only during power-up-reset and is
unchanged by software or local reset.
1st $FFF4301C/2nd $FFF4311C (8-bits)
30 29 28
BCK6 BCK5 BCK4
R/W R/W R/W
0 P 0 P 1 P
1st $FFF43020/2nd $FFF43120 (16-bits)
30 29 28
0 DERC ZFILL
R R/W R/W
X 1 PLS 0 PLS
READ/WRITE CHECKBITS, when set, enables the data
from the seven checkbits in the Petra MCECC sector (bits
30-24) to be written and read on the local MC680x0 data
bus. This bit should be cleared for normal system
operation.
Note that if test software forces a single-bit error to a
location (line) using this function, the scrubber may
correct the location before the test software gets a chance
to check for the single-bit error at that location. This can
be avoided by disabling scrubbing and making sure that
all previous scrubs have completed before performing the
test. Also note that writing bad checkbits can set the
ERRLOG bit in the Error Logger register.
Programming Model
27 26 25
BCK3 BCK2 BCK1
R/W R/W R/W
1 P 0 P 0 P
27 26 25
RWCKB 0 0
R/W R R
0 PLS X X
24
4
BCK0
R/W
1P
24
0
R
X
4-17