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Motorola MVME1X7P Programmer's Reference Manual

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MVME1X7P Single-Board Computer
Programmer's Reference
Guide
V1X7PA/PG1
Edition of October 2000

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   Summary of Contents for Motorola MVME1X7P

  • Page 1

    MVME1X7P Single-Board Computer Programmer’s Reference Guide V1X7PA/PG1 Edition of October 2000...

  • Page 2

    Printed in the United States of America. ® Motorola and the Motorola logo are registered trademarks of Motorola, Inc. MC68040™ and MC68060™ are trademarks of Motorola, Inc. All other products mentioned in this document are trademarks or registered trademarks of...

  • Page 3: Safety Summary, Ground The Instrument, Do Not Substitute Parts Or Modify Equipment

    The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

  • Page 4: Emi Caution

    All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.

  • Page 5

    While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

  • Page 6

    If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.

  • Page 7: Table Of Contents

    The Petra ASIC and Second-Generation MVME1X7 Boards...1-1 Features...1-3 Applicable Industry Standards...1-4 Block Diagram ...1-4 Programming Interfaces...1-7 MC680X0 MPU...1-7 Data Bus Structure ...1-7 EEPROMs on the MVME1X7P ...1-8 MVME167...1-8 MVME177...1-9 Flash Memory on the MVME177...1-9 SRAM ...1-10 Onboard SDRAM ...1-11 Battery-Backed-Up RAM and Clock...1-12 VMEbus Interface...1-12...

  • Page 8: Table Of Contents

    Functional Description ... 1-17 VMEbus Interface and VMEchip2... 1-18 VMEchip2 General-Purpose I/O... 1-18 Petra/VMEchip2 Redundant Logic ... 1-18 Memory Maps... 1-20 Local Bus Memory Map... 1-20 Normal Address Range ... 1-20 Detailed I/O Memory Maps ... 1-25 BBRAM/TOD Clock Memory Map ... 1-41 Interrupt Acknowledge Map ...

  • Page 9: Table Of Contents

    LAN Offboard Error ...1-61 LAN LTO Error ...1-62 SCSI Parity Error ...1-62 SCSI Offboard Error ...1-62 SCSI LTO Error ...1-63 CHAPTER 2 VMEchip2 Introduction...2-1 Functional Blocks ...2-4 Local-Bus-to-VMEbus Interface ...2-4 Local-Bus-to-VMEbus Requester ...2-7 VMEbus-to-Local-Bus Interface ...2-9 Local-Bus-to-VMEbus DMA Controller...2-10 No-Address-Increment DMA Transfers ...2-12 DMAC VMEbus Requester...2-13 Tick and Watchdog Timers ...2-14 Prescaler...2-14...

  • Page 10: Table Of Contents

    VMEbus Slave Address Modifier Select Register 1 ... 2-36 Programming the Local-Bus-to-VMEbus Map Decoders... 2-37 Local Bus Slave (VMEbus Master) Ending Address Register 1 ... 2-39 Local Bus Slave (VMEbus Master) Starting Address Register 1 ... 2-40 Local Bus Slave (VMEbus Master) Ending Address Register 2 ... 2-40 Local Bus Slave (VMEbus Master) Starting Address Register 2 ...

  • Page 11: Table Of Contents

    VME Access, Local Bus, and Watchdog Time-out Control Register ...2-66 Prescaler Control Register ...2-67 Tick Timer 1 Compare Register ...2-68 Tick Timer 1 Counter ...2-68 Tick Timer 2 Compare Register ...2-69 Tick Timer 2 Counter ...2-69 Board Control Register ...2-70 Watchdog Timer Control Register ...2-71 Tick Timer 2 Control Register ...2-72 Tick Timer 1 Control Register ...2-73...

  • Page 12: Table Of Contents

    I/O Control Register 2 ... 2-97 I/O Control Register 3 ... 2-97 Miscellaneous Control Register ... 2-98 GCSR Programming Model ... 2-100 Programming the GCSR... 2-102 VMEchip2 Revision Register ... 2-103 VMEchip2 ID Register ... 2-104 VMEchip2 LM/SIG Register ... 2-104 VMEchip2 Board Status/Control Register ...

  • Page 13: Table Of Contents

    Programming the Tick Timers ...3-18 Tick Timer 1 Compare Register ...3-18 Tick Timer 1 Counter ...3-19 Tick Timer 2 Compare Register ...3-19 Tick Timer 2 Counter ...3-20 Prescaler Count Register ...3-20 Prescaler Clock Adjust Register ...3-20 Tick Timer 2 Control Register...3-22 Tick Timer 1 Control Register...3-23 General Purpose Input Interrupt Control Register...3-24 General Purpose Input/Output Pin Control Register ...3-25...

  • Page 14: Table Of Contents

    CHAPTER 4 MCECC Functions Introduction ... 4-1 Features... 4 -2 Functional Description ... 4-3 General Description... 4-3 Performance... 4-3 Cache Coherency... 4-4 ECC ... 4-5 Cycle Types... 4-5 Error Reporting ... 4-5 Single Bit Error (Cycle Type = Burst Read or Non-Burst Read) ... 4-5 Double Bit Error (Cycle Type = Burst Read or Non-Burst Read) ...

  • Page 15: Table Of Contents

    Scrub Prescaler Counter (Bits 7-0) ...4-24 Scrub Timer Counter (Bits 15-8) ...4-24 Scrub Timer Counter (Bits 7-0) ...4-25 Scrub Address Counter (Bits 26-24)...4-25 Scrub Address Counter (Bits 23-16)...4-26 Scrub Address Counter (Bits 15-8)...4-26 Scrub Address Counter (Bits 7-4)...4-26 Error Logger Register ...4-27 Error Address (Bits 31-24) ...4-28 Error Address (Bits 23-16) ...4-28 Error Address (Bits 15-8) ...4-29...

  • Page 17: List Of Figures

    Figure 3-1. PCCchip2 Block Diagram...3-2 Figure B-1. MVME1X7P Printer Port with MVME712M ... B-2 Figure B-2. MVME1X7P Serial Port 1 Configured as DCE ... B-3 Figure B-3. MVME1X7P Serial Port 2 Configured as DCE ... B-4 Figure B-4. MVME1X7P Serial Port 3 Configured as DCE ... B-5 Figure B-5.

  • Page 18

    xviii...

  • Page 19

    Table 4-3. MCECC Sector Internal Register Memory Map ...4-11 Table 4-4. Syndrome Bit Encoding...4-36 Table 4-5. Identifying SDRAM Bank in Error ...4-37 Table A-1. List of Changes ...A-1 Table C-1. Motorola Computer Group Documents ... C-1 Table C-2. Manufacturers’ Documents ... C-2 Table C-3. Related Specifications ... C-3...

  • Page 21: About This Manual

    Motorola VME boards which combines a variety of functions previously implemented in other ASICs (among them the MC2 chip, the IP2 chip, and the MCECC chip) in a single ASIC. On the MVME1X7P, the “Petra” chip replaces the MCECC ASIC. As of the publication date, the...

  • Page 22: Introduction

    SCSI and LAN controllers. Chapter 4, MCECC (MCECC). On the MVME1X7P boards, it supplies the interface to a 144- bit wide DRAM memory system. Appendix A, Summary of accompanied the introduction of the Petra ASIC on the MVME167P and MVME177P.

  • Page 23: Conventions Used In This Manual

    You can also submit comments to the following e-mail address: reader-comments@mcg.mot.com In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

  • Page 24

    bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.

  • Page 25

    The terms control bit, status bit, true, and false are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls.

  • Page 26

    xxvi...

  • Page 27: The Petra Asic And Second-generation Mvme1x7 Boards, Introduction

    This chapter discusses those topics in addition to interrupt handling, the use of bus timers, and the programming interface to each device on the board. Programmable registers that reside in ASICs (Application-Specific Integrated Circuits) on the MVME1X7P boards are covered in the chapters devoted to those devices. Note The MVME1X7P’s new ’‘Petra’’...

  • Page 28

    Programming Issues The Petra ASIC is functionally compatible with each of the components that it replaces. In cases where functionality between ASICs is exclusive, configuration switches or jumpers are provided to let you select the desired functionality. In several areas of functionality, the configuration switches provide backward compatibility with earlier MVME167/177 implementations, but you can override their settings in software if you wish.

  • Page 29: Features

    Features The “Petra” ASIC supplants the MCECC memory controller ASIC on MVME1X7P boards, performing the memory control functions previously carried out by the MCECC chip: It supplies the programmable interface for the ECC-protected 16/32/64/128MB DRAM emulation. The following table summarizes the features of the MVME167P and MVME177P single-board computers.

  • Page 30: Applicable Industry Standards, Block Diagram

    Programming Issues Table 1-1. MVME1X7P Features Summary (Continued) Feature VMEbus VMEbus system controller functions interface VMEbus-to-local-bus interface (A32/A24, D32/D16/D8) Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32) Programmable interrupter and interrupt handler Global Control/Status register for interprocessor communications DMA capability for fast local-memory/VMEbus transfers (A16/A24/A32,...

  • Page 31

    Introduction 2816 0800 Figure 1-1. MVME167P Block Diagram http://www.motorola.com/computer/literature...

  • Page 32

    Programming Issues 2816 0800 Figure 1-2. MVME177P Block Diagram Computer Group Literature Center Web Site...

  • Page 33: Programming Interfaces, Mc680x0 Mpu, Data Bus Structure

    Local Bus to communicate. The Local Bus is arbitrated by priority type arbiter. The priority of the Local Bus masters from highest to lowest is: Highest priority Lowest priority http://www.motorola.com/computer/literature 1-3. 82596CA LAN CD2401 serial (through the PCCchip2) 53C710 SCSI...

  • Page 34: Eeproms On The Mvme1x7p, Mvme167

    EEPROMs on the MVME1X7P Both boards include 44-pin PLCC/CLCC sockets for EEPROMs, organized as follows: The MVME167P boards use 27C102JK or 27C202JK type EEPROMs.

  • Page 35: Mvme177, Flash Memory On The Mvme177

    1. Map Flash and EEPROM as shown in Map 3 in Figure 1-3. 2. Copy the 177Bug into the bottom 2MB of Flash memory. 3. Remap Flash memory as shown in Map 1 in Figure 1-3. http://www.motorola.com/computer/literature Programming Interfaces Chapter 2, VMEchip2.

  • Page 36: Sram

    Programming Issues MAP 1 FFBFFFFF FLASH MEMORY FF800000 NO EPROM IN MAP Figure 1-3. MVME177 Flash and EPROM Memory Mapping Schemes SRAM The MVME167P and MVME177P single-board computers include 128KB of 32-bit wide 100ns static RAM (SRAM) that supports 8-, 16-, and 32-bit wide accesses.

  • Page 37: Onboard Sdram

    MVME167P boards are built with 16MB-64MB synchronous DRAM (SDRAM). MVME177P boards are built with 16MB-128MB SDRAM. The MVME1X7P may have the SDRAM configured to model 4MB, 8MB, 16MB, 32MB, 64MB, or 128MB of ECC-protected DRAM. In addition to the onboard SDRAM, an additional mezzanine (of the type used on previous MVME1X7 boards) can be plugged in to provide up to 128MB of additional DRAM.

  • Page 38: Battery-backed-up Ram And Clock, Vmebus Interface, I/o Interfaces

    Programming Issues Battery-Backed-Up RAM and Clock Although the M48T58-70 RAM and clock chip is an 8-bit device, the interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the M48T58. No interrupts are generated by the clock. Refer to 3, PCCchip2 guidance and battery life information.

  • Page 39: Serial Port Interface

    I/O connector pinout to industry-standard connectors. Note The MVME1X7P board hardware ties the DTR signal from the CD2401 to the pin labeled RTS at connector P2. Likewise, RTS from the CD2401 is tied to DTR on P2. Therefore, when programming the CD2401, assert DTR when you want RTS, and RTS when you want DTR.

  • Page 40: Parallel (printer) Interface

    Programming Issues The CD2401 supports DMA operations to local memory. Because the CD2401 does not support a retry operation necessary to break VMEbus lockup conditions, the CD2401 DMA controllers should not be programmed to access the VMEbus. The hardware does not restrict the CD2401 to onboard DRAM.

  • Page 41: Ethernet Interface

    VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus. Every MVME1X7P that is built with an Ethernet interface is assigned an Ethernet Station Address. The address is $0001AFxxxxxx where xxxxxx is the unique 6-nibble number assigned to the board (i.e., every MVME1X7P has a different value for xxxxxx).

  • Page 42: Scsi Interface, Local Resources, Programmable Tick Timers

    Programming Issues SCSI Interface The MVME167P and MVME177P single-board computers provide for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.

  • Page 43: Watchdog Timer, Software-programmable Hardware Interrupts, Local Bus Timeout, Functional Description

    VMEbus global timer. Refer to programming information. Functional Description This section highlights a few specific features of the MVME1X7P single- board computers. For a complete functional description of the major blocks of the MVME1X7P, refer to the Installation and Use manual.

  • Page 44: Vmebus Interface And Vmechip2, Vmechip2 General-purpose I/o, Petra/vmechip2 Redundant Logic

    MVME177P, follow the previous MVME177 in their routing of GPIO signals: Petra/VMEchip2 Redundant Logic In support of possible future configurations in which the MVME1X7P might be offered as a single-board computer without the VMEbus interface, certain logic in the VMEchip2 has been duplicated in the Petra chip.

  • Page 45

    ABORT VMEchip2, but with a different bit organization (refer to the VMEchip2 description in Chapter 2). In the MVME1X7P, the ABORT 7. The SRAM and EPROM decoder in the VMEchip2 (version 2) must be disabled by software before any accesses are made to these address spaces.

  • Page 46: Memory Maps, Local Bus Memory Map, Normal Address Range

    The following tables show the memory maps of devices that respond to the normal address range. The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the MVME1X7P, Transfer Types 0, 1, and 2 define the normal address range.

  • Page 47

    The onboard I/O space must be marked cache-inhibit and serialized in its page table. Table 1-4 on page 1-22 devices on the MVME1X7P. Table 1-3. Local Bus Memory Map Address Devices Accessed Range $00000000 - User Programmable DRAMSIZE (Onboard SDRAM)

  • Page 48

    Programming Issues 2. This area is user-programmable. The suggested use is shown in the 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped. 5. This area is not decoded. If these locations are accessed and the 6.

  • Page 49

    Reserved $FFF80000 - $FFF9FFFF Reserved $FFFA0000 - $FFFBFFFF Reserved $FFFC0000 - $FFFCFFFF M48T58 (BBRAM, TOD Clock) $FFFD0000 - $FFFDFFFF Reserved $FFFE0000 - $FFFEFFFF Reserved http://www.motorola.com/computer/literature Devices Accessed Port Size D16-D8 D32/D8 D32-D8 Memory Maps Size Notes 256B 3.5KB 512B 512B...

  • Page 50

    TEA signal. writes: upper word first and lower word second. on the MVME1X7P. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. Computer Group Literature Center Web Site...

  • Page 51: Detailed I/o Memory Maps

    M48T58 BBRAM, TOD Clock BBRAM Configuration Area TOD Clock You can obtain manufacturers’ errata sheets for the various chips listed above by contacting your local Motorola sales representative. A non- disclosure agreement may be necessary. http://www.motorola.com/computer/literature Memory Maps Table 1-5...

  • Page 52

    Programming Issues Table 1-5. VMEchip2 Memory Map (Sheet 1 of 3) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: MAST MAST GCSR GROUP SELECT TICK TICK IRQ 1 1-26 SLAVE ENDING ADDRESS 1 SLAVE ENDING ADDRESS 2 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER MASTER ENDING ADDRESS 1...

  • Page 53

    BYTE COUNTER TABLE ADDRESS COUNTER DMA TABLE INTERRUPT COUNT STAT This sheet begins on facing page. http://www.motorola.com/computer/literature SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2...

  • Page 54

    Programming Issues Table 1-5. VMEchip2 Memory Map (Sheet 2 of 3) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: SCON FAIL FAIL FAIL AC FAIL IRQ LEVEL VME IACK IRQ LEVEL IRQ LEVEL SPARE IRQ LEVEL VECTOR BASE REGISTER 0 1-28 BGTO TIME OFF PURS...

  • Page 55

    COUNTER 2 SCALER P ERROR IRQ LEVEL SIG 1 IRQ LEVEL IRQ LEVEL VME IRQ 4 IRQ LEVEL GPIOO This sheet begins on facing page. http://www.motorola.com/computer/literature PRESCALER TIME OUT CLOCK ADJUST SELECT OVERFLOW COUNTER 1 SPARE IRQ7 IRQ6 IRQ5 IRQ1E...

  • Page 56

    Programming Issues Table 1-5. VMEchip2 Memory Map (Sheet 3 of 3) VMEchip2 GCSR Base Address = $FFF40100 Offsets Local -bus 1-30 Bit Numbers Chip Revision General Purpose Control and Status register 0 General Purpose Control and Status register 1 General Purpose Control and Status register 2 General Purpose Control and Status register 3 General Purpose Control and Status register 4 General Purpose Control and Status register 5...

  • Page 57

    PLTY E/L* Printer BUSY Interrupt Control Register NAME PLTY E/L* Printer Input Status Register NAME PLTY Printer Port Control Register NAME Printer Data Register NAME http://www.motorola.com/computer/literature $FFF42030 ICLR ICLR $FFF42032 ICLR $FFF42033 ICLR ICLR $FFF42036 $FFF42037 DOEN 16 bits $FFF4203A...

  • Page 58

    Programming Issues PCCchip2 Base Address = $FFF42000 OFFSET: PRESCALER COUNT REGISTER PLTY E/L* PRTR PRTR PRTR PLTY E/L* PRTR PRTR PRTR PLTY E/L* SCC PROVIDES ITS OWN VECTORS 1-32 Table 1-7. PCCchip2 Memory Map CHIP ID ICLR IRQ LEVEL RTRY SCLR SCLR SCSI...

  • Page 59

    PRTR PRTR PRTR PRTR PRTR PLTY E/L* ICLR PRTR PRTR PRTR PRTR This sheet begins on facing page. http://www.motorola.com/computer/literature MSTR FAST VECTOR BASE REGISTER BRAM OVERFLOW COUNTER 1 TIC TIMER 2 TIC1 TIC1 IRQ LEVEL SCC TRANSMIT IRQ LEVEL SCC MODEM PIACK...

  • Page 60

    Programming Issues Table 1-8. MCECC Internal Register Memory Map MCECC Base Address = $FFF43000 (1st); $FFF43100 (2nd) Register Register Offset Name CHIP ID CHIP REVISION MEMORY CONFIG DUMMY 0 DUMMY 1 BASE ADDRESS DRAM CONTROL BCLK FREQUENCY DATA CONTROL SCRUB CONTROL SCRUB PERIOD...

  • Page 61

    ERRLO LOGGER ERROR EA31 ADDRESS ERROR EA23 ADDRESS ERROR EA15 ADDRESS ERROR ADDRESS ERROR SYNDROME DEFAULTS1 WRHDI DEFAULTS2 FRC_O http://www.motorola.com/computer/literature Register Bit Names SAC22 SAC21 SAC20 SAC19 SAC14 SAC13 SAC12 SAC11 SAC6 SAC5 SAC4 ESCR EALT EA30E EA29 EA28 EA27...

  • Page 62

    Programming Issues Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map Base Address = $FFF45000 Register Description Global Firmware Revision Code Register Channel Access Register Channel Mode Register Channel Option Register 1 Channel Option Register 2 Channel Option Register 3 Channel Option Register 4 Channel Option Register 5 Channel Option Register 6...

  • Page 63

    Channel Status Register Modem Signal Value Registers Local Interrupt Vector Register Interrupt Enable Register Local Interrupting Channel Register Stack Register Receive Priority Interrupt Level Register Receive Interrupt Register Receive Interrupt Status Register http://www.motorola.com/computer/literature Register Offsets Name RFAR1 RFAR2 RFAR3 RFAR4 CPSR...

  • Page 64

    Programming Issues Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map (Continued) Base Address = $FFF45000 Register Description Receive Interrupt Status Register low Receive Interrupt Status Register high Receive FIFO Output Count Receive Data Register Receive End Of Interrupt Register Transmit Priority Interrupt Level Register Transmit Interrupt Register Transmit Interrupt Status Register...

  • Page 65

    B Transmit Buffer Status Transmit Current Buffer Address Lower Transmit Current Buffer Address Upper Timer Period Register Receive Time-out Period Register Receive Time-out Period Regis low Receive Time-out Period Register high General Timer 1 http://www.motorola.com/computer/literature Register Offsets Name BRBCNT ARBSTS BRBSTS RCBADRL...

  • Page 66

    Programming Issues Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map (Continued) Base Address = $FFF45000 Register Description General Timer 1 low General Timer 1 high General Timer 2 Transmit Timer Register Note Table 1-10. 82596CA Ethernet LAN Memory Map Address $FFF46000 Upper Command Word...

  • Page 67: Bbram/tod Clock Memory Map

    (TOD) clock, is defined by the chip hardware. The first area is reserved for user data. The second area is used by Motorola networking software. The third area may be used by an operating system. The fourth area is http://www.motorola.com/computer/literature...

  • Page 68

    Programming Issues used by the MVME1X7P board debugger (MVME1X7Bug). The fifth area, detailed in Table detailed in Table Table 1-12. M48T58 BBRAM,TOD Clock Memory Map Address Range $FFFC0000 - $FFFC0FFF $FFFC1000 - $FFFC10FF $FFFC1100 - $FFFC16F7 $FFFC16F8 - $FFFC1EF7 $FFFC1EF8 - $FFFC1FF7 $FFFC1FF8 - $FFFC1FFF Table 1-13.

  • Page 69

    ST = Stop Bit FT = Frequency Test x = Must be set to 0 The data structure of the configuration bytes starts at $FFFC1EF8 and is as follows. http://www.motorola.com/computer/literature Description Mezz. Board 2 PWB Mezz. Board 2 Serial Number Reserved...

  • Page 70

    Programming Issues struct brdi_cnfg { The fields are defined as follows: 1. Four bytes are reserved for the revision or version of this structure. 2. Twelve bytes are reserved for the serial number of the board in 3. Sixteen bytes are reserved for the board ID in ASCII format. For 4.

  • Page 71

    14. Growth space (153 bytes) is reserved. This pads the structure to an even 256 bytes. System-specific items, such as size of system side, and systems side version, may go here. http://www.motorola.com/computer/literature 01-W3620F35C 2500 prefix. For example, for a 16MB parity mezzanine...

  • Page 72: Interrupt Acknowledge Map, Vmebus Memory Map, Vmebus Accesses To The Local Bus

    GCSR in the VMEbus short I/O space. 1-46 the Debugging Package User’s Manual for MVME167Bug and MVME177Bug, and the Debugging Package for Motorola 68K CISC CPUs User’s Manual) for security and data integrity of the configuration area of the NVRAM. This data is stored in hexadecimal format.

  • Page 73: Interrupt Handling, Example: Vmechip2 Tick Timer 1 Periodic Interrupt

    MVME177P single-board computers. The following example illustrates how to generate and handle a VMEchip2 Tick Timer 1 interrupt on M68000-based single-board computers such as the MVME1X7P. Specific values are given for the register writes. It is advisable to read this entire section before you perform any of these procedures.

  • Page 74

    Programming Issues Step Register and Address Prescaler Control register $FFF4004C Tick Timer 1 Compare register $FFF40050 Tick Timer 1 Counter register $FFF40054 Tick Timer 1 Control register $FFF40060 (8 bits) Step Register and Address Vector Base register $FFF40088 (8 of 32 bits) Interrupt Level register 1 (bits 0-7) $FFF40078 (8 of 32 bits)

  • Page 75: Cache Coherency (mvme167p)

    When snooping is enabled, the MC68040 MPU can source data and invalidate cache entries as required by the current cycle. The MPU cannot watch VMEbus cycles that do not access the Local Bus. Software must http://www.motorola.com/computer/literature Cache Coherency (MVME167P) Action and Reference...

  • Page 76: Cache Coherency (mvme177p)

    Programming Issues ensure that data shared by multiple processors is kept in un-cached memory. The software must also mark all onboard I/O areas as cache inhibited and serialized. Cache Coherency (MVME177P) The MVME177P’s MC68060 processor has the ability to watch the external bus during accesses by other bus masters, maintaining coherency between the MC68060’s caches and external memory systems.To maintain cache coherency, the MC68060 provides automatic snoop-...

  • Page 77: Using Bus Timers

    Once the VMEbus has been granted, a third timer takes over. This is the global VMEbus timer. This timer starts when a transfer actually begins (DS0 or DS1 goes active) and ends when that transfer completes (DS0 or http://www.motorola.com/computer/literature Measures the time an access to an onboard resource takes...

  • Page 78: Indivisible Cycles

    Programming Issues DS1 goes inactive). This time should be longer than any expected legitimate transfer time on the bus. We normally set it to 256 sec. This timer can also be disabled for debug purposes. Before a single-board computer access to another single-board computer can complete, however, the VMEchip2 on the accessed board must decode a slave access and request the Local Bus of the second board.

  • Page 79: Supervisor Stack Pointer (mc68060)

    Software emulation of CAS2 and misaligned CAS instructions is performed by the MC68060 Software Package, which is included in all Motorola-supplied operating systems for the MVME177P. Contact your sales office for information about obtaining the MC68060 Software Package for use with other operating systems.

  • Page 80: Sources Of Local Bus Errors, Local Bus Timeout, Vmebus Access Timeout, Vmebus Berr*

    Programming Issues Sources of Local Bus Errors A TEA* signal (indicating a bus error) is returned to the Local Bus master when a Local Bus time-out occurs, a DRAM parity error occurs and parity checking is enabled, or a VME bus error occurs during a VMEbus access. The sources of Local Bus errors on the Single Board Computers are described in the next subsections.

  • Page 81: Vmechip2, Bus Error Processing, Error Conditions

    Application software must take this possibility into account. Error Conditions This section lists the various error conditions that are reported by the single-board computer hardware. A subheading identifies each error condition; a standard format provides the following information: Description of the error...

  • Page 82: Mpu Parity Error, Mpu Offboard Error, Mpu Tea - Cause Unidentified

    Programming Issues MPU Parity Error Description: MPU Notification: Status: Comments: MPU Offboard Error Description: MPU Notification: Status: Comments: MPU TEA - Cause Unidentified Description: MPU Notification: Status: Comments: 1-56 A DRAM parity error. TEA is asserted during an MPU DRAM access. Bit 9 of the MPU Status and DMA Interrupt Count register in the VMEchip2 at address $FFF40048.

  • Page 83: Mpu Local Bus Time-out, Dmac Vmebus Error, Dmac Parity Error

    DMAC Parity Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature An error occurred while the MPU was attempting to access a local resource. TEA is asserted during the MPU access. Bit 7 of the MPU Status and DMA Interrupt Count register (actually in the DMAC Status register).

  • Page 84: Dmac Offboard Error, Dmac Lto Error

    Programming Issues DMAC Offboard Error Description: MPU Notification: Status: Comments: DMAC LTO Error Description: MPU Notification: Status: Comments: 1-58 Error encountered while the Local Bus side of the DMAC was attempting to go to the VMEbus. DMAC interrupt (when enabled) The DLOB bit is set in the DMAC Status register (address $FFF40048 bit 4).

  • Page 85: Dmac Tea - Cause Unidentified, Scc Retry Error

    SCC Retry Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature An error occurred while the DMAC was Local Bus master and additional status was not provided. DMAC interrupt (when enabled) The DLBE bit is set in the DMAC Status register (address $FFF40048 bit 6).

  • Page 86: Scc Parity Error, Scc Offboard Error

    Programming Issues SCC Parity Error Description: MPU Notification: Status: Comments: SCC Offboard Error Description: MPU Notification: Status: Comments: 1-60 Parity Error detected while the SCC was reading DRAM. SCC Transmit Interrupt or SCC Receive Interrupt SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Buffer Address register PCCchip2...

  • Page 87: Scc Lto Error, Lan Parity Error, Lan Offboard Error

    Comments: LAN Offboard Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature Local Bus Time-out occurred while the SCC was Local Bus master. SCC Transmit Interrupt or SCC Receive Interrupt SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High...

  • Page 88: Lan Lto Error, Scsi Parity Error, Scsi Offboard Error

    Programming Issues LAN LTO Error Description: MPU Notification: Status: Comments: SCSI Parity Error Description: MPU Notification: Status: Comments: SCSI Offboard Error Description: MPU Notification: Status: Comments: 1-62 Local Bus Time-out occurred while the LANCE was Local Bus master. PCCchip2 Interrupt (LAN ERROR IRQ) PCCchip2 LAN Error Status register ($FFF42028) The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the PCCchip2.

  • Page 89: Scsi Lto Error

    SCSI LTO Error Description: MPU Notification: Status: Comments: http://www.motorola.com/computer/literature Local Bus Time-out occurred while the 53C710 was Local Bus master. 53C710 Interrupt 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register ($FFF4202C) 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2.

  • Page 90

    Programming Issues 1-64 Computer Group Literature Center Web Site...

  • Page 91

    Introduction This chapter describes the VMEchip2 ASIC, the local-bus/VMEbus interface chip. The VMEchip2 interfaces the local bus to the VMEbus. In addition to its VMEbus-defined functions, the VMEchip2 includes a local-bus-to- VMEbus DMA controller, VME board support features, and Global Control and Status Registers (GCSRs) for interprocessor communications.

  • Page 92

    VMEchip2 Table 2-1. Features of the VMEchip2 ASIC (Continued) Function VMEbus-to-Local- Bus Interface 32-bit Local-Bus-to- VMEbus DMA Controller VMEbus Interrupter Features Programmable VMEbus map decoder Programmable AM decoder Programmable local bus snoop enable Simple VMEbus-to-local-bus address translation 8-bit, 16-bit and 32-bit VMEbus data width 8-bit, 16-bit and 32-bit block transfer Standard and extended VMEbus addressing Software-enabled write posting mode...

  • Page 93

    Four 16-bit dual-ported general purpose registers Interrupt Handler All interrupts level-programmable All interrupts maskable All interrupts providing a unique vector Software and external interrupts Watchdog timer Control and status bits, 4-bit counter Two tick timers Control and status bits, 32-bit counter http://www.motorola.com/computer/literature Introduction Features...

  • Page 94: Functional Blocks, Local-bus-to-vmebus Interface

    VMEchip2 Functional Blocks The following sections provide an overview of the functions implemented by the VMEchip2 ASIC. See VMEchip2. Detailed programming models for the local control and status registers (LCSRs) and the global control and status registers (GCSRs) appear in subsequent sections. Local-Bus-to-VMEbus Interface The local-bus-to-VMEbus interface allows local bus masters access to global resources on the VMEbus.

  • Page 95

    Functional Blocks Figure 2-1. VMEchip2 Block Diagram http://www.motorola.com/computer/literature...

  • Page 96

    VMEchip2 Using the four programmable map decoders, separate VMEbus maps can be created, each with its own attributes. For example, one map can be configured as A32, D32 with write posting enabled while a second map can be A24, D16 with write posting disabled. The first I/O map decoder decodes local bus addresses $FFFF0000 through $FFFFFFFF as the short I/O A16/D16 or A16/D32 area.

  • Page 97: Local-bus-to-vmebus Requester

    Requiring no external jumpers, the chip provides the means for software to program the requester to request the bus on any one of the four bus request levels, automatically establishing the bus grant daisy-chains for the three inactive levels. http://www.motorola.com/computer/literature Functional Blocks...

  • Page 98

    VMEchip2 The requester requests the bus if any of the following conditions occur: 1. The local bus master initiates either a data transfer cycle or an 2. The chip is requested to acquire control of the VMEbus as signaled 3. The chip is requested to acquire control of the VMEbus as signaled The local-bus-to-VMEbus requester in the VMEchip2 implements a fair mode.

  • Page 99: Vmebus-to-local-bus Interface

    (in increments of 64KB), as well as setting each bank’s address modifier codes, write post enable, and snoop enable. http://www.motorola.com/computer/literature Functional Blocks A24, A32 D08(EO), D16, D32, D8/BLT,...

  • Page 100: Local-bus-to-vmebus Dma Controller

    VMEchip2 Each map decoder includes an alternate address register and an alternate address select register. These registers allow any or all of the upper 16 VMEbus address lines to be replaced by signals from the alternate address register. This allows the address of local resources to differ from their VMEbus address.

  • Page 101

    VMEbus. Since the local bus is generally faster than the VMEbus, other local bus masters may use the local bus while the DMAC is waiting for the VMEbus. http://www.motorola.com/computer/literature Functional Blocks A16, A24, A32 D16, D32, D16/BLT, D32/BLT,...

  • Page 102: No-address-increment Dma Transfers

    VMEbus address. The DMA controller also allows DMA transfers without incrementing the local bus address, although the MVME1x7P has no onboard devices that benefit from not incrementing the local bus address. The transfer mode on the VMEbus may be D16, D16/BLT, D32, D32/BLT or D64/BLT.

  • Page 103: Dmac Vmebus Requester

    Requiring no external jumpers, the chip provides the means for software to program the DMAC requester to request the bus on any one of the four bus request levels, automatically establishing the bus grant daisy-chains for the three inactive levels. http://www.motorola.com/computer/literature Functional Blocks 2-13...

  • Page 104: Tick And Watchdog Timers, Prescaler

    VMEchip2 The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer. The requester implements a fair mode. By setting the DFAIR bit, the requester refrains from requesting the bus until it detects its assigned request line in its negated state.

  • Page 105: Tick Timers, Watchdog Timer

    When this occurs, the WDTO status bit is set; and if the local or SYSRESET function is enabled, the selected reset is generated; if the board fail function is enabled, the board fail signal is generated. http://www.motorola.com/computer/literature Functional Blocks 2-15...

  • Page 106: Vmebus Interrupter

    VMEchip2 VMEbus Interrupter The interrupter provides all the signals necessary to allow software to request interrupt service from a VMEbus interrupt handler. The chip connects to all signals that a VMEbus interrupter is required to drive and monitor. Requiring no external jumpers, the chip provides the means for software to program the interrupter to request an interrupt on any one of the seven interrupt request lines.

  • Page 107: Vmebus System Controller, Arbiter, Iack Daisy-chain Driver, Bus Timer

    The timeout period can be set to 8, 64, or 256 secs. The bus timer terminates an unresponded VMEbus cycle only if both it and the system controller are enabled. http://www.motorola.com/computer/literature Functional Blocks 2-17...

  • Page 108: Reset Driver, Local Bus Interrupter And Interrupt Handler

    VMEchip2 In addition to the VMEbus timer, the chip contains a local bus timer. This timer asserts the local TEA when the local bus cycle maintained in its asserted state for longer that the programmed time-out period. This timer can be enabled or disabled under software control. The time-out period can be programmed for 8, 64, or 256 seconds.

  • Page 109

    The location monitor interrupters are edge-sensitive interrupters connected to the location monitor bits in the GCSR. The software 7-0 interrupters can be set by software to generate interrupts. The VMEbus IRQ7-1 interrupters are level-sensitive interrupters connected to the VMEbus IRQ7 -IRQ1 signal lines. http://www.motorola.com/computer/literature 2-19...

  • Page 110: Global Control And Status Registers, Lcsr Programming Model

    VMEchip2 The interrupt handler provides all logic necessary to identify and handle all local interrupts as well as VMEbus interrupts. When a local interrupt is acknowledged, a unique vector is provided by the chip. Edge-sensitive interrupters are not cleared during the interrupt acknowledge cycle and must by reset by software as required.

  • Page 111

    W/AC This bit can be set and it is automatically cleared. This bit can 5. The state of the bit following a reset, defined as follows: Table 2-2 shows a summary of the LCSRs. http://www.motorola.com/computer/literature This bit is a read-only status bit. This bit is readable and writable. also be read.

  • Page 112

    VMEchip2 Table 2-2. VMEchip2 Memory Map—LCSR Summary (Sheet 1 of 2) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: MAST MAST GCSR GROUP SELECT TICK TICK IRQ 1 2-22 SLAVE ENDING ADDRESS 1 SLAVE ENDING ADDRESS 2 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER MASTER ENDING ADDRESS 1...

  • Page 113

    BYTE COUNTER TABLE ADDRESS COUNTER DMA TABLE INTERRUPT COUNT STAT This sheet begins on facing page. http://www.motorola.com/computer/literature SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4...

  • Page 114

    VMEchip2 Table 2-2. VMEchip2 Memory Map—LCSR Summary (Sheet 2 of 2) VMEchip2 LCSR Base Address = $FFF40000 OFFSET: SCON FAIL FAIL FAIL AC FAIL IRQ LEVEL VME IACK IRQ LEVEL IRQ LEVEL SPARE IRQ LEVEL VECTOR BASE REGISTER 0 2-24 BGTO TIME OFF PURS...

  • Page 115

    COUNTER 2 SCALER P ERROR IRQ LEVEL SIG 1 IRQ LEVEL IRQ LEVEL VME IRQ 4 IRQ LEVEL GPIOO This sheet begins on facing page. http://www.motorola.com/computer/literature PRESCALER TIME OUT CLOCK ADJUST SELECT OVERFLOW COUNTER 1 SPARE IRQ7 IRQ6 IRQ5 IRQ1E...

  • Page 116: Programming The Vmebus Slave Map Decoders

    VMEchip2 Programming the VMEbus Slave Map Decoders This section includes programming information for the VMEbus-to-local- bus map decoders. The VMEbus-to-local-bus interface allows off-board VMEbus masters access to local on-board resources. The address of the local resources as viewed from the VMEbus is controlled by the VMEbus slave map decoders, which are part of the VMEbus-to-local-bus interface.

  • Page 117

    A32 of the local bus and A32 of the VMEbus. In addition to the address translation method previously described, the VMEchip2 as used on the MVME1X7P includes an adder which can be used for address translation. When the adder is enabled, the local bus address is generated by adding the offset value to the VMEbus address lines VA<31..16>.

  • Page 118: Vmebus Slave Ending Address Register 1, Vmebus Slave Starting Address Register 1

    VMEchip2 $FFF40010. The adders allow any size board to be mapped on any 64KB boundary. The adders are disabled and the address replacement method is used following reset. Write posting is enabled for the segment by setting the write post enable bit in the attribute register.

  • Page 119: Vmebus Slave Ending Address Register 2, Vmebus Slave Starting Address Register 2

    This register is the address translation address register for the first VMEbus-to-local-bus map decoder. It should be programmed to the local bus starting address. When the adder is engaged, this register is the offset value. http://www.motorola.com/computer/literature $FFF40004 (16 bits of 32) . . . Ending Address Register 2...

  • Page 120: Vmebus Slave Address Translation Select Register 1

    VMEchip2 VMEbus Slave Address Translation Select Register 1 ADR/SIZ NAME OPER RESET This register is the address translation select register for the first VMEbus- to-local-bus map decoder. The address translation select register value is based on the segment size (the difference between the VMEbus starting and ending addresses).

  • Page 121: Vmebus Slave Address Translation Address Offset Register 2, Vmebus Slave Address Translation Select Register 2

    Segment Size 64KB 128KB 256KB 512KB 16MB http://www.motorola.com/computer/literature $FFF4000C (16 bits of 32) . . . Address Translation Address Offset Register 2 0 PS $FFF4000C (16 bits of 32) . . . Address Translation Select Register 2...

  • Page 122: Vmebus Slave Write Post And Snoop Control Register 2

    VMEchip2 VMEbus Slave Write Post and Snoop Control Register 2 ADR/SIZ NAME OPER RESET This register is the slave write post and snoop control register for the second VMEbus-to-local-bus map decoder. SNP2 SNP2 ADDER2 2-32 $FFF40010 (8 bits [4 used] of 32) ADDER 0 PS When this bit is high, write posting is enabled for the...

  • Page 123: Vmebus Slave Address Modifier Select Register 2

    DAT, PGM, BLK and D64; A24 and A32; and USR and SUP. At least one bit must be set from each group to enable the map decoder. http://www.motorola.com/computer/literature $FFF40010 (8 bits of 32) 0 PSL 0 PSL...

  • Page 124

    VMEchip2 2-34 When this bit is high, the second map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, the second map decoder does not respond to VMEbus A32 access cycles. When this bit is high, the second map decoder responds to VMEbus user (non-privileged) access cycles.

  • Page 125: Vmebus Slave Write Post And Snoop Control Register 1

    This register is the slave write post and snoop control register for the first VMEbus-to-local-bus map decoder. SNP1 SNP1 ADDER1 http://www.motorola.com/computer/literature $FFF40010 (8 bits [4 used] of 32) ADDER 0 PS When this bit is high, write posting is enabled for the address range defined by the first VMEbus slave map decoder.

  • Page 126: Vmebus Slave Address Modifier Select Register 1

    VMEchip2 VMEbus Slave Address Modifier Select Register 1 ADR/SIZ NAME OPER RESET 0 PSL This register is the address modifier select register for the first VMEbus- to-local-bus map decoder. There are three groups of address modifier select bits: DAT, PGM, BLK and D64; A24 and A32; and USR and SUP. At least one bit must be set from each group to enable the first map decoder.

  • Page 127: Programming The Local-bus-to-vmebus Map Decoders

    VMEbus address to be provided by the address translation address register rather than the upper 16 bits of the local bus. http://www.motorola.com/computer/literature When this bit is high, the first map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, the first map decoder does not respond to VMEbus A32 access cycles.

  • Page 128

    VMEchip2 Each of the four programmable local bus map decoders has a starting address, an ending address, an address modifier register with attribute bits, and an enable bit. The fourth decoder also has address translation registers. The addresses and bit definitions for these registers are in the tables below.

  • Page 129: Local Bus Slave (vmebus Master) Ending Address Register 1

    Local Bus Slave (VMEbus Master) Ending Address Register 1 ADR/SIZ NAME OPER RESET This register is the ending address register for the first local-bus-to- VMEbus map decoder. http://www.motorola.com/computer/literature LCSR Programming Model $FFF40014 (16 bits of 32) . . . Ending Address Register 1 0 PS 2-39...

  • Page 130: Local Bus Slave (vmebus Master) Starting Address Register 1

    VMEchip2 Local Bus Slave (VMEbus Master) Starting Address Register 1 ADR/SIZ NAME OPER RESET This register is the starting address register for the first local-bus-to- VMEbus map decoder. Local Bus Slave (VMEbus Master) Ending Address Register 2 ADR/SIZ NAME OPER RESET This register is the ending address register for the second local-bus-to- VMEbus map decoder.

  • Page 131: Local Bus Slave (vmebus Master) Ending Address Register 3

    ADR/SIZ NAME OPER RESET This register is the ending address register for the fourth local-bus-to- VMEbus map decoder. http://www.motorola.com/computer/literature LCSR Programming Model $FFF4001C (16 bits of 32) . . . Ending Address Register 3 0 PS $FFF4001C (16 bits of 32) .

  • Page 132: Local Bus Slave (vmebus Master) Starting Address Register 4

    VMEchip2 Local Bus Slave (VMEbus Master) Starting Address Register 4 ADR/SIZ NAME OPER RESET This register is the starting address register for the fourth local-bus-to- VMEbus map decoder. Local Bus Slave (VMEbus Master) Address Translation Address Register 4 ADR/SIZ NAME OPER RESET This register is the address translation address register for the fourth local-...

  • Page 133: Local Bus Slave (vmebus Master) Attribute Register 4

    0 PS 0 PS This register is the attribute register for the fourth local-bus-to-VMEbus bus map decoder. http://www.motorola.com/computer/literature $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 4.

  • Page 134: Local Bus Slave (vmebus Master) Attribute Register 3

    VMEchip2 Local Bus Slave (VMEbus Master) Attribute Register 3 ADR/SIZ NAME OPER RESET 0 PS This register is the attribute register for the third local-bus-to-VMEbus bus map decoder. 2-44 $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 3.

  • Page 135: Local Bus Slave (vmebus Master) Attribute Register 2

    0 PS 0 PS This register is the attribute register for the second local-bus-to-VMEbus bus map decoder. http://www.motorola.com/computer/literature $FFF40028 (8 bits of 32) O PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 2.

  • Page 136: Local Bus Slave (vmebus Master) Attribute Register 1

    VMEchip2 Local Bus Slave (VMEbus Master) Attribute Register 1 ADR/SIZ NAME OPER RESET 0 PS This register is the attribute register for the first local-bus-to-VMEbus bus map decoder. 2-46 $FFF40028 (8 bits of 32) 0 PS These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 1.

  • Page 137: Vmebus Slave Gcsr Group Address Register

    $FFF4002C (8 bits of 32) . . . GCSR Group Address Register 4 $00 PS These bits are compared with VMEbus address lines A8 through A15. The recommended group address for the MVME1x7P is $D2. LCSR Programming Model 2-47...

  • Page 138: Vmebus Slave Gcsr Board Address Register

    VMEchip2 VMEbus Slave GCSR Board Address Register ADR/SIZ NAME OPER RESET This register defines the board address of the GCSR as viewed from the VMEbus. The GCSR address is defined by the group address and the board address. Once enabled, the GCSR register should not be reprogrammed unless the VMEchip2 is VMEbus master.

  • Page 139: Local-bus-to-vmebus Enable Control Register

    OPER RESET This register is the map decoder enable register for the four programmable local-bus-to-VMEbus map decoders. http://www.motorola.com/computer/literature $FFF4002C (4 bits of 32) 0 PSL When this bit is high, the first local-bus-to-VMEbus map decoder is enabled. When this bit is low, the first local- bus-to-VMEbus map decoder is disabled.

  • Page 140: Local-bus-to-vmebus I/o Control Register

    VMEchip2 Local-Bus-to-VMEbus I/O Control Register ADR/SIZ NAME I2EN OPER RESET 0 PSL This register controls the VMEbus short I/O map and the F page ($F0000000 through $FF7FFFFF) I/O map. I1SU I1WP I1D16 I1EN I2PD I2SU 2-50 $FFF4002C (8 bits of 32) I2WP I2SU I2PD...

  • Page 141: Rom Control Register, Programming The Vmechip2 Dma Controller

    NAME SIZE OPER RESET 0 PS This function is not used on the MVME1x7P. Programming the VMEchip2 DMA Controller This section includes programming information on the DMA controller, VMEbus interrupter, MPU status register, and local-bus-to-VMEbus requester register. The VMEchip2 features a local-bus -to-VMEbus DMA controller (DMAC).

  • Page 142

    VMEchip2 A maximum of 4GB of data may be transferred with one DMAC command. Larger transfers can be accomplished using the command chaining mode. In command chaining mode, a singly-linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands.

  • Page 143: Dmac Registers, Eprom Decoder, Sram And Dma Control Register

    Address of Next Command Packet $FFF40030 (8 bits [6 used] of 32) WAIT RMW ROM0 TBLSC 0 PSL 1 PSL 0 PS These VMEchip2 bits are not used on the MVME1x7P. LCSR Programming Model Control Word SRAMS 0 PS 2-53...

  • Page 144: Local-bus-to-vmebus Requester Control Register

    Source dirty, sink byte/word/longword Source dirty, invalidate line Snoop disabled (Reserved) This bit is not used on the MVME1x7P. Its function is performed by the ROM0 bit in the Petra/MC2 PROM Access Time Control register. Refer to Chapter 3. $FFF40030 (8 bits [7 used] OF 32)

  • Page 145: Dmac Control Register 1 (bits 0-7)

    0 PS This control register is loaded by the processor; it is not modified when the DMAC loads new values from the command packet. DREQL http://www.motorola.com/computer/literature The request level is 0. The request level is 1. The request level is 2.

  • Page 146

    VMEchip2 DRELM DFAIR DTBL DHALT 2-56 always requests at the old level until it becomes bus master and the new level takes effect. If the VMEchip2 is bus master when the level is changed, the new level does not take effect until the bus has been released and re- requested at the old level.

  • Page 147: Dmac Control Register 2 (bits 8-15)

    TVME LINC VINC http://www.motorola.com/computer/literature $FFF40034 (8 bits [7 USED] of 32) VINC 0 PS 0 PS When this bit is high, the DMAC executes D16 cycles on the VMEbus.

  • Page 148: Dmac Control Register 2 (bits 0-7)

    VMEchip2 INTE DMAC Control Register 2 (bits 0-7) ADR/SIZ NAME OPER RESET This portion of the control register is loaded by the processor or the DMAC when it loads the command word from the command packet. Because this byte is loaded from the command packet in command chaining mode, the descriptions here also apply to the control word in the command packet.

  • Page 149: Dmac Local Bus Address Counter

    In direct mode, this counter is programmed with the starting address of the data in local bus memory. http://www.motorola.com/computer/literature VMEbus address modifier bits 2-5, and address modifier bits 0 and 1 are provided by the DMAC to indicate a block transfer.

  • Page 150: Dmac Vmebus Address Counter, Dmac Byte Counter, Table Address Counter

    VMEchip2 DMAC VMEbus Address Counter ADR/SIZ NAME OPER RESET In direct mode, this counter is programmed with the starting address of the data in VMEbus memory. DMAC Byte Counter ADR/SIZ NAME OPER RESET In direct mode, this counter is programmed with the number of bytes of data to be transferred.

  • Page 151: Vmebus Interrupter Control Register

    ADR/SIZ NAME OPER RESET This register controls the VMEbus interrupter. IRQL IRQS IRQC IRQ1S http://www.motorola.com/computer/literature $FFF40048 (8 bits [7 used] of 32) IRQ1S IRQC IRQS 0 PS 0 PS 0 PS These bits define the level of the VMEbus interrupt generated by the VMEchip2.

  • Page 152: Vmebus Interrupter Vector Register, Mpu Status And Dma Interrupt Count Register

    VMEchip2 VMEbus Interrupter Vector Register ADR/SIZ NAME OPER RESET This register controls the VMEbus interrupter vector. MPU Status and DMA Interrupt Count Register ADR/SIZ NAME OPER RESET This is the MPU status register and DMAC interrupt counter. MLOB MLPE MLBE MCLR 2-62 $FFF40048 (8 bits of 32)

  • Page 153: Dmac Status Register

    This is the DMAC status register. DONE DLTO DLOB http://www.motorola.com/computer/literature The DMAC interrupt counter is incremented when an interrupt is sent to the local bus interrupter. The value in this counter indicates the number of commands processed when the DMAC is operated in command chaining mode.

  • Page 154: Programming The Tick And Watchdog Timers, Vmebus Arbiter Time-out Control Register

    VMEchip2 DLPE DLBE MLTO Programming the Tick and Watchdog Timers The VMEchip2 has two 32-bit tick timers and one watchdog timer. This section provides addresses and bit level descriptions of the prescaler, tick timer, watchdog timer registers, and various other timer registers. VMEbus Arbiter Time-Out Control Register ADR/SIZ NAME...

  • Page 155: Dmac Ton/toff Timers And Vmebus Global Time-out Control Register

    This register controls the DMAC time off timer, the DMAC time on timer, and the VMEbus global time-out timer. VGTO TIME ON TIME OFF http://www.motorola.com/computer/literature $FFF4004C (8 bits of 32) TIME ON 0 PS These bits define the VMEbus global time-out value.

  • Page 156: Vme Access, Local Bus, And Watchdog Time-out Control Register

    VMEchip2 VME Access, Local Bus, and Watchdog Time-out Control Register ADR/SIZ NAME OPER RESET WDTO LBTO VATO 2-66 $FFF4004C (8 bits of 32) VATO LBTO 0 PS 0 PS These bits define the watchdog time-out period: Bit Encoding Time-out 1 ms 2 ms 4 ms 8 ms...

  • Page 157: Prescaler Control Register

    B clock divided by two. The prescaler register control logic does not allow the value 255 ($FF) to be programmed. http://www.motorola.com/computer/literature LCSR Programming Model $FFF4004C (8 bits of 32) . . .

  • Page 158: Tick Timer 1 Compare Register, Tick Timer 1 Counter

    VMEchip2 Tick Timer 1 Compare Register ADR/SIZ NAME OPER RESET The tick timer 1 counter is compared to this register. When they are equal, an interrupt is sent to the local bus interrupter and the overflow counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.

  • Page 159: Tick Timer 2 Compare Register, Tick Timer 2 Counter

    OPER RESET This is the tick timer 2 counter. When enabled, it increments every microsecond. Software may read or write the counter at any time. http://www.motorola.com/computer/literature LCSR Programming Model $FFF40058 (32 bits) . . . Tick timer 2 Compare Register $FFF4005C (32 bits) .

  • Page 160: Board Control Register

    VMEchip2 Board Control Register ADR/SIZ NAME OPER RESET RSWE BDFLO CPURS PURS BRFLI SFFL SCON 2-70 $FFF40060 (8 bits [7 used] of 32) SCON SFFL BRFLI PURS 1 PSL switch enable bit is used with the “no RESET VMEbus interface” option. This bit is duplicated at the same bit position in the MC2 chip at location $FFF42044.

  • Page 161: Watchdog Timer Control Register

    WDEN WDRSE WDS/L WDBFE WDTO WDCC http://www.motorola.com/computer/literature $FFF40060 (8 bits of 32) WDCC WDTO WDBFE WDS/L WDRSE WDEN 0 PSL When this bit is high, the watchdog timer is enabled. When this bit is low, the watchdog timer is not enabled.

  • Page 162: Tick Timer 2 Control Register

    VMEchip2 WDCS SRST Tick Timer 2 Control Register ADR/SIZ NAME OPER RESET COVF 2-72 When this bit is set high, the watchdog time-out status bit (WDTO bit in this register) is cleared. When this bit is set high, a SYSRESET signal is generated on the VMEbus.

  • Page 163: Tick Timer 1 Control Register, Prescaler Counter

    8 bits increment at the local bus clock rate and the upper 24 bits increment every microsecond. The counter may be read at any time. http://www.motorola.com/computer/literature $FFF40060 (8 bits of 32) 0 PS When this bit is high, the counter increments.

  • Page 164: Programming The Local Bus Interrupter

    VMEchip2 Programming the Local Bus Interrupter The local bus interrupter is used by devices that need to interrupt the local bus. There are 31 devices that can interrupt the local bus through the VMEchip2. In the general case, each interrupter has a level select register, an enable bit, a status bit, a clear bit, and a set bit for the software interrupts.

  • Page 165

    Software 2 Software 3 Software 4 Software 5 Software 6 Software 7 GCSR LM0 GCSR LM1 GCSR SIG0 GCSR SIG1 GCSR SIG2 GCSR SIG3 http://www.motorola.com/computer/literature LCSR Programming Model Priority for Vector Simultaneous Interrupts External Lowest External External External External External...

  • Page 166

    VMEchip2 Table 2-4. Local Bus Interrupter Summary (Continued) Interrupt DMAC VMEbus Interrupter Acknowledge Tick Timer 1 Tick Timer 2 VMEbus IRQ1 Edge-Sensitive MVME1x7P (Not used on VMEbus Master Write Post Error VMEbus SYSFAIL MVME1x7P (Not used on VMEbus ACFAIL Notes 1.

  • Page 167: Local Bus Interrupter Status Register (bits 24-31)

    0 PSL 0 PSL 0 PSL Tick timer 1 interrupt. Tick timer 2 interrupt VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME1x7P. VMEbus master write post error interrupt. VMEbus SYSFAIL interrupt. Not used on MVME1x7P. VMEbus ACFAIL interrupt. LCSR Programming Model...

  • Page 168: Local Bus Interrupter Status Register (bits 16-23)

    VMEchip2 Local Bus Interrupter Status Register (bits 16-23) ADR/SIZ NAME OPER RESET 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.

  • Page 169: Local Bus Interrupter Status Register (bits 8-15)

    When an interrupt status bit is low, a local interrupt is not being generated. The interrupt status bits are: http://www.motorola.com/computer/literature $FFF40068 (8 bits of 32) 0 PSL 0 PSL 0 PSL Software 0 interrupt.

  • Page 170: Local Bus Interrupter Status Register (bits 0-7)

    VMEchip2 Local Bus Interrupter Status Register (bits 0-7) ADR/SIZ NAME SPARE OPER RESET 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.

  • Page 171: Local Bus Interrupter Enable Register (bits 24-31)

    0 PSL Enable tick timer 1 interrupt. Enable tick timer 2 interrupt. Enable VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME1x7P. Enable VMEbus master write post error interrupt. Enable VMEbus SYSFAIL interrupt. Not used on MVME1x7P. Enable VMEbus ACFAIL interrupt.

  • Page 172: Local Bus Interrupter Enable Register (bits 16-23)

    VMEchip2 Local Bus Interrupter Enable Register (bits 16-23) ADR/SIZ NAME EVIA OPER RESET 0 PSL This register is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.

  • Page 173: Local Bus Interrupter Enable Register (bits 8-15)

    ESW0 ESW1 ESW2 ESW3 ESW4 ESW5 ESW6 ESW7 http://www.motorola.com/computer/literature $FFF4006C (8 bits of 32) ESW5 ESW4 ESW3 0 PSL 0 PSL 0 PSL Enable software 0 interrupt. Enable software 1 interrupt.

  • Page 174: Local Bus Interrupter Enable Register (bits 0-7)

    VMEchip2 Local Bus Interrupter Enable Register (bits 0-7) ADR/SIZ NAME SPARE OPER RESET 0 PSL This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.

  • Page 175: Software Interrupt Set Register (bits 8-15), Interrupt Clear Register (bits 24-31)

    0 PSL This register is used to clear the edge-sensitive interrupts. An interrupt is cleared by writing a 1 to its clear bit. The clear bits are defined below. CTIC1 CTIC2 http://www.motorola.com/computer/literature $FFF40070 (8 bits of 32) SSW5 SSW4 SSW3...

  • Page 176: Interrupt Clear Register (bits 16-23)

    CSIG1 CSIG2 CSIG3 CDMA CVIA 2-86 Clear VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME1x7P. Clear VMEbus master write post error interrupt. Clear VMEbus SYSFAIL interrupt. Not used on MVME1x7P. Clear VMEbus ACFAIL interrupt. $FFF40074 (8 bits of 32) CDMA...

  • Page 177: Interrupt Clear Register (bits 8-15), Interrupt Level Register 1 (bits 24-31)

    Clear software 4 interrupt. Clear software 5 interrupt. Clear software 6 interrupt. Clear software 7 interrupt. $FFF40078 (8 bits [6 used] of 32) ACF LEVEL 0 PSL Not used on MVME1x7P. LCSR Programming Model CSW2 CSW1 CSW0 AB LEVEL 0 PSL...

  • Page 178: Interrupt Level Register 1 (bits 16-23), Interrupt Level Register 1 (bits 8-15)

    $FFF40078 (8 bits [6 used] of 32) PE LEVEL 0 PSL These bits define the level of the VMEbus IRQ1 edge-sensitive interrupt. Not used on MVME1x7P. Computer Group Literature Center Web Site WPE LEVEL 0 PSL IRQ1E LEVEL 0 PSL...

  • Page 179: Interrupt Level Register 1 (bits 0-7), Interrupt Level Register 2 (bits 24-31)

    This register is used to define the level of the DMA controller interrupt and the VMEbus acknowledge interrupt. DMA LEVEL These bits define the level of the DMA controller VIA LEVEL http://www.motorola.com/computer/literature $FFF40078 (8 bits [6 used] of 32) TICK2 LEVEL 0 PSL These bits define the level of the tick timer 1 interrupt.

  • Page 180: Interrupt Level Register 2 (bits 16-23), Interrupt Level Register 2 (bits 8-15)

    VMEchip2 Interrupt Level Register 2 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the GCSR SIG2 interrupt and the GCSR SIG3 interrupt. SIG2 LEVEL These bits define the level of the GCSR SIG2 interrupt. SIG3 LEVEL These bits define the level of the GCSR SIG3 interrupt.

  • Page 181: Interrupt Level Register 2 (bits 0-7), Interrupt Level Register 3 (bits 24-31)

    This register is used to define the level of the software 6 interrupt and the software 7 interrupt. SW6 LEVEL These bits define the level of the software 6 interrupt. SW7 LEVEL These bits define the level of the software 7 interrupt. http://www.motorola.com/computer/literature $FFF4007C (8 bits [6 used] of 32) LM1 LEVEL 0 PSL...

  • Page 182: Interrupt Level Register 3 (bits 16-23), Interrupt Level Register 3 (bits 8-15)

    VMEchip2 Interrupt Level Register 3 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the software 4 interrupt and the software 5 interrupt. SW4 LEVEL These bits define the level of the software 4 interrupt. SW5 LEVEL These bits define the level of the software 5 interrupt.

  • Page 183: Interrupt Level Register 3 (bits 0-7), Interrupt Level Register 4 (bits 24-31)

    SW1 LEVEL 0 PSL $FFF40084 (8 bits [6 used] of 32) SPARE LEVEL 0 PSL These bits define the level of the VMEbus IRQ7 interrupt. Not used on the MVME1x7P. LCSR Programming Model SW0 LEVEL 0 PSL VIRQ7 LEVEL 0 PSL...

  • Page 184: Interrupt Level Register 4 (bits 16-23), Interrupt Level Register 4 (bits 8-15)

    VMEchip2 Interrupt Level Register 4 (bits 16-23) ADR/SIZ NAME OPER RESET This register is used to define the level of the VMEbus level 5 (IRQ5) interrupt and the VMEbus level 6 (IRQ6) interrupt. The IRQ5 and IRQ6 interrupts may be mapped to any local bus interrupt level. VIRQ5 LEVEL VIRQ6 LEVEL Interrupt Level Register 4 (bits 8-15)

  • Page 185: Interrupt Level Register 4 (bits 0-7), Vector Base Register

    $FFF40088 to $67xxxxxx). This produces a Vector Base0 of $60 corresponding to the “X” in and a Vector Base1 of $70 corresponding to the “Y” in 2-4. http://www.motorola.com/computer/literature $FFF40084 (8 bits [6 used] of 32) VIRQ2 0 PSL These bits define the level of the VMEbus IRQ1 interrupt.

  • Page 186: I/o Control Register 1

    VMEchip2 I/O Control Register 1 ADR/SIZ NAME MIEN OPER RESET 0 PSL This register is a general purpose I/O control register. Bits 16-19 control the direction of the four General Purpose I/O pins (GPIO0-3). GPOEN0 GPOEN1 GPOEN2 GPOEN3 ABRTL ACFL SYSFL MIEN 2-96...

  • Page 187: I/o Control Register 2, I/o Control Register 3

    I/O Control Register 3 ADR/SIZ NAME GPI7 GPI6 OPER RESET This function is not used on the MVME1x7P. http://www.motorola.com/computer/literature $FFF40088 (8 bits of 32) GPIOI3 GPIOI2 GPIOI1 GPIOI0 0 PS 0 PS Connects to pin 16 of the Remote Status and Control register.

  • Page 188: Miscellaneous Control Register

    VMEchip2 Miscellaneous Control Register ADR/SIZ NAME MPIRQEN OPER RESET 0 PSL DISBGN ENINT DISBSYT 2-98 $FFF4008C (8 bits of 32) REVEROM DISSRAM DISMST NOELBBSY DISBSYT 0 PSL 0 PSL 0 PS 0 PS When this bit is high, the VMEbus BGIN filters are disabled.

  • Page 189

    VMEchip2 is disabled. When this bit is low, the SRAM decoder in the VMEchip2 is enabled. Because the SRAM decoder in the VMEchip2 is not used on the MVME1x7P, this bit must be set. This function is not used on the MVME1x7P. This bit must not be set.

  • Page 190: Gcsr Programming Model

    VMEchip2 GCSR Programming Model This section describes the programming model for the Global Control and Status Registers (GCSR) in the VMEchip2. The local bus map decoder for the GCSR registers is included in the VMEchip2. The local bus base address for the GCSR is $FFF40100. The registers in the GCSR are 16 bits wide and they are byte accessible from both the VMEbus and the local bus.

  • Page 191

    Communications between the local processor and a VMEbus master should use interrupts or mailbox locations; reset should not be used in normal communications. Reset should be used only when the local processor is halted or the local bus is hung and reset is the last resort. http://www.motorola.com/computer/literature 2-101...

  • Page 192: Programming The Gcsr

    VMEchip2 Programming the GCSR A complete description of the GCSR appears in the following tables. Each register definition includes a table with five lines. 1. The base address of the register and the number of bits defined in 2. The bits defined by this table. 3.

  • Page 193: Vmechip2 Revision Register

    RESET This register is the VMEchip2 revision register. The revision level for the VMEchip2 starts at 0 and is incremented if mask changes are required. The VMEchip2 used on the MVME1x7P is revision $01 or greater. http://www.motorola.com/computer/literature Bit Numbers General Purpose Control and Status Register 0...

  • Page 194: Vmechip2 Id Register, Vmechip2 Lm/sig Register

    VMEchip2 VMEchip2 ID Register ADR/SIZ NAME OPER RESET This register is the VMEchip2 ID register. The ID for the VMEchip2 is 10. VMEchip2 LM/SIG Register ADR/SIZ NAME OPER RESET 1 PS This register is the VMEchip2 location monitor register and the interrupt register.

  • Page 195

    SIG3 http://www.motorola.com/computer/literature The SIG3 bit is set when a VMEbus master writes a 1 to it. When the SIG3 bit is set, an interrupt is sent to the local bus interrupter. The SIG3 bit is cleared when the local processor writes a 1 to the SIG3 bit in this register or the CSIG3 bit in the local interrupt clear register.

  • Page 196: Vmechip2 Board Status/control Register

    VMEchip2 VMEchip2 Board Status/Control Register ADR/SIZ NAME OPER RESET 0 PSL This register is the VMEchip2 board status/control register. SYSFL SCON 2-106 Local Bus: $FFF40104/VMEbus: $XXY2 (8 bits [5 used]) SCON 0 PSL 1 PS This bit is set when the VMEchip2 is driving the SYSFAIL signal.

  • Page 197: General Purpose Register 0, General Purpose Register 1, General Purpose Register 2

    This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. http://www.motorola.com/computer/literature GCSR Programming Model . . . General Purpose Register 0 0 PS .

  • Page 198: General Purpose Register 3, General Purpose Register 4, General Purpose Register 5

    VMEchip2 General Purpose Register 3 ADR/SIZ NAME OPER RESET This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. General Purpose Register 4 ADR/SIZ NAME...

  • Page 199: Summary Of Major Features, Introduction

    Introduction This chapter defines the peripheral channel controller ASIC, referred to hereafter as the PCCchip2. The PCCchip2 is designed to interface an MC68040-compatible local bus (Local Bus) to various peripheral devices. Summary of Major Features This section lists the major features of the PCCchip2. BBRAM interface with dynamic sizing support.

  • Page 200: Functional Description, General Description

    PCCchip2 Functional Description The following sections provide an overview of the functions provided by the PCCchip2. A detailed programming model for the PCCchip2 control and status registers is provided in a later section. General Description The PCCchip2 interfaces the MC68040 microprocessor bus to the local peripherals on the Single-Board Computers including: battery-backed RAM, Serial Communications Controller (CL-CD2401), LAN controller (82596CA), and SCSI controller (NCR53C710).

  • Page 201: Bbram Interface, Ca Lan Controller Interface, Mpu Port And Mpu Channel Attention

    Word (two bytes) is mapped at $FFF46000 and the Lower Command Word (two bytes) is mapped at $FFF46002. The PCCchip2 only supports (decodes) MPU Port writes. It does not decode MPU Port reads. (Nor does the 82596CA support MPU Port reads.) http://www.motorola.com/computer/literature Functional Description...

  • Page 202: Mc68040-bus Master Support For 82596ca, Lanc Bus Error

    PCCchip2 MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Command blocks. To execute an MPU Channel Attention, the Local Bus bus master performs a simple read or write to address $FFF46004. MC68040-Bus Master Support for 82596CA The 82596CA has DMA capability with an Intel i486-bus interface.

  • Page 203: Lanc Interrupt

    LANC interrupts in the LANC Interrupt Control Register is higher than the level set in the Interrupt Mask Level Register). When the MPU acknowledges the LANC interrupt, the PCCchip2 responds with the vector that corresponds to LANC interrupts. http://www.motorola.com/computer/literature Functional Description...

  • Page 204: C710 Scsi Controller Interface, Parallel Port Interface

    PCCchip2 53C710 SCSI Controller Interface The PCCchip2 provides a map decoder and an interrupt handler for the NCR-53C710 SCSI I/O Processor. The base address for the 53C710 is $FFF47000. When the PCCchip2 detects low a level on the IRQ* line from the 53C710, if such interrupts are enabled, it generates an interrupt to the MPU.

  • Page 205: General Purpose I/o Pin, Cd2401 Scc Interface

    SCC: auto vector and direct. In auto vector mode, the PCCchip2 supplies the interrupt vector to the MPU. (No interrupt acknowledge cycle is seen by the CD2401.) In direct mode, the SCC supplies the vector to the MPU. (The PCCchip2 passes the interrupt acknowledge cycle on through http://www.motorola.com/computer/literature Functional Description...

  • Page 206

    PCCchip2 to the CD2401. Note that the PCCchip2 drives the CD2401 A7-A0 pins with $01 for modem interrupt acknowledges, $02 for transmit interrupt acknowledges and $03 for receive interrupt acknowledges.) The use of the auto vector mode is not recommended because the CD2401 can supply the vector and the CD2401 requires an interrupt acknowledge cycle.

  • Page 207: Tick Timer

    An interrupt to the Local Bus is only generated if the tick timer interrupt is enabled by the Local Bus interrupter. The overflow counter can be cleared by writing a one to the overflow clear bit. http://www.motorola.com/computer/literature Functional Description...

  • Page 208: Overall Memory Map

    PCCchip2 Overall Memory Map The following memory map includes all devices selected by the PCCchip2 map decoders, including those internal to the chip and those external. These devices respond only when the Transfer Type signals carry the values of %00 or %01 which correspond to Normal and MOVE16 accesses on the Local Bus.

  • Page 209: Programming Model

    The bit is not affected by reset. The effect of reset on this bit is variable. The bit is always 0. The bit is always 1. A summary of the PCCchip2 CSR is shown in Table 6-2. http://www.motorola.com/computer/literature Programming Model 3-11...

  • Page 210

    PCCchip2 Table 3-2. PCCchip2 Memory Map - Control and Status Registers PCCchip2 Base Address = $FFF42000 OFFSET: PRESCALER COUNT REGISTER PLTY E/L* PRTR PRTR PRTR PLTY E/L* PRTR PRTR PRTR PLTY E/L* SCC PROVIDES ITS OWN VECTORS 3-12 CHIP ID ICLR IRQ LEVEL RTRY...

  • Page 211

    E/L* PRTR PRTR PRTR PRTR PRTR PLTY E/L* ICLR PRTR PRTR PRTR This sheet begins on facing page. http://www.motorola.com/computer/literature MSTR FAST VECTOR BASE REGISTER BRAM OVERFLOW COUNTER 1 TIC TIMER 2 TIC1 TIC1 IRQ LEVEL SCC TRANSMIT IRQ LEVEL SCC MODEM PIACK...

  • Page 212: Chip Id Register, Chip Revision Register

    PCCchip2 Chip ID Register The Chip ID Register is located at $FFF42000. It is an 8-bit read-only register that is hard-wired to a hexadecimal value of $20. Writes to this register are ignored; however, the PCCchip2 always terminates the cycles properly with TA*.

  • Page 213: General Control Register

    The PCCchip2 runs at half the MPU speed on the MVME177P. For example, an MVME177P with a 50 MHz MPU will run the PCCchip2 at 25 MHz. MIEN http://www.motorola.com/computer/literature $FFF42002 (8 bits) This control bit tailors the control circuit for BBRAM to the speed of BBRAM.

  • Page 214: Vector Base Register

    When the bit is cleared, EIPL<2..0> are not driven as outputs, but are inputs only. Download ROM at 0 (not applicable to MVME1X7P). This bit should remain cleared, so that DROM appears only in its normal address range. (When DR0 is set, DROM also appears at $00000000 through $0001FFFF.)

  • Page 215

    Register, and SCC Receive Interrupt Control Register.) If this mode is disabled by setting the AVEC bits to 0, then the PCCchip2 obtains the vector from the SCC and passes it to the MPU. Using the auto vector mode is NOT recommended. http://www.motorola.com/computer/literature $FFF42003 (8 bits) 0 PL 0 PL...

  • Page 216: Programming The Tick Timers, Tick Timer 1 Compare Register

    PCCchip2 A suggested setting of the Local Interrupt Vector Register in the SCC chip is $5C. This produces the following vectors: Programming the Tick Timers This section provides addresses and bit level descriptions of the prescaler, tick timers, and various other timer registers. Tick Timer 1 Compare Register The Tick Timer 1 Compare Register is a 32-bit register located at $FFF42004.

  • Page 217: Tick Timer 1 Counter, Tick Timer 2 Compare Register

    The rollover time for the counter is 71.6 minutes. ADR/SIZ NAME OPER RESET http://www.motorola.com/computer/literature $FFF42008 (32 bits) . . . Tick Timer 1 Counter $FFF4200C (32 bits) . . .

  • Page 218: Tick Timer 2 Counter, Prescaler Count Register, Prescaler Clock Adjust Register

    PCCchip2 Tick Timer 2 Counter The Tick Timer 2 Counter is a 32-bit read/write register located at address $FFF42010. When enabled, it increments every microsecond. Software may read or write the counter at any time. ADR/SIZ NAME OPER RESET Prescaler Count Register The Prescaler Count Register is an 8-bit counter used to generate the 1 MHz clock for the two tick timers.

  • Page 219

    If a write with the value of $FF occurs to this register, the PCCchip2 terminates the cycle properly with TA*, but the register remains unchanged. ADR/SIZ NAME OPER RESET http://www.motorola.com/computer/literature Programming Model $FFF42015 (8 bits) . . . Prescaler Clock Adjust $DF P 3-21...

  • Page 220

    PCCchip2 Tick Timer 2 Control Register This is an 8-bit read/write register that controls Tick Timer 2. It is located at address $FFF42016. ADR/SIZ NAME OVF3 OPER RESET 0 PL COVF OVF3-OVF0 These four bits are the outputs of the overflow counter. 3-22 $FFF42016 (8 bits) OVF2...

  • Page 221

    OVF2 OPER RESET 0 PL 0 PL COVF OVF3-OVF0 These four bits are the outputs of the overflow counter. http://www.motorola.com/computer/literature $FFF42017 (8 bits) OVF1 OVF0 0 PL 0 PL Counter Enable. When this bit is high, the counter increments. When this bit is low, the counter does not increment.

  • Page 222: General Purpose Input Interrupt Control Register

    PCCchip2 General Purpose Input Interrupt Control Register ADR/SIZ NAME PLTY OPER RESET 0 PL IL2-IL0 ICLR E/L* PLTY 3-24 $FFF42018 (8 bits) E/L* ICLR 0 PL 0 PL 0 PL 0 PL These three bits select the interrupt level for the general purpose input/output (GPIO) pin.

  • Page 223: General Purpose Input/output Pin Control Register, Tick Timer 2 Interrupt Control Register

    OPER RESET IL2-IL0 ICLR http://www.motorola.com/computer/literature $FFF42019 (8 bits) When GPO is set, and GPOE is set, the GPIO pin is at a logic high level. When GPO is cleared, and GPOE is set, the GPIO pin is at a logic low level.

  • Page 224: Tick Timer 1 Interrupt Control Register

    PCCchip2 Tick Timer 1 Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 ICLR 3-26 Interrupt Status. When this bit is high a Tick Timer 2 interrupt is being generated at the level programmed in IL2-IL0 (if nonzero). This bit is edge-sensitive and can be cleared by writing a logic 1 into the ICLR control bit.

  • Page 225: Scc Error Status And Interrupt Control Registers, Scc Error Status Register

    ADR/SIZ NAME OPER RESET SCLR LTO,EXT, PRTY,RTRY error condition encountered by the SCC while performing http://www.motorola.com/computer/literature $FFF4201C (8 bits) RTRY PRTY 0 PL 0 PL Writing a 1 to this bit clears bits 25 through 28 (LTO, EXT, PRTY, and RTRY). Reading this bit always yields These bits indicate the status of the last Local Bus DMA accesses to the Local Bus.

  • Page 226: Scc Modem Interrupt Control Register

    PCCchip2 SCC Modem Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 AVEC 3-28 $FFF4201D (8 bits) AVEC 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for SCC modem Interrupt. Level 0 does not generate an interrupt. When this bit is high, the PCCchip2 supplies the interrupt vector to the MPU during an IACK for SCC modem interrupt.

  • Page 227: Scc Transmit Interrupt Control Register

    SCC Transmit Interrupt Control Register ADR/SIZ NAME OPER RESET IL2-IL0 AVEC http://www.motorola.com/computer/literature $FFF4201E (8 bits) AVEC 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for SCC Transmit Interrupt. Level 0 does not generate an interrupt.

  • Page 228: Scc Receive Interrupt Control Register

    PCCchip2 SCC Receive Interrupt Control Register ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 AVEC SC1-SC0 Note 3-30 $FFF4201F (8 bits) AVEC 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for SCC Receive Interrupt. Level 0 does not generate an interrupt.

  • Page 229: Modem Piack Register

    Note If this register is read when an interrupt is not present, the interrupt acknowledge cycle times out with a TEA if the Local Bus timer is enabled. MIV7-MIV0 http://www.motorola.com/computer/literature $FFF42023 (8 bits) MIV5 MIV4 MIV3 Modem interrupt vector bits 7-0 reflect the modem interrupt vector driven by the CD2401 to the PCCchip2 during a pseudo interrupt acknowledge cycle.

  • Page 230: Transmit Piack Register

    PCCchip2 Transmit PIACK Register ADR/SIZ NAME TIV7 OPER RESET The Transmit PIACK Register is used to execute transmit pseudo interrupt acknowledge cycles to the CD2401. When the Local Bus master initiates a read cycle to this register, the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with A7-A0 = $02.

  • Page 231: Receive Piack Register

    Note If this register is read when an interrupt is not present, the interrupt acknowledge cycle times out with a TEA if the Local Bus timer is enabled. RIV7-RIV0 http://www.motorola.com/computer/literature $FFF42027 (8 bits) RIV5 RIV4 RIV3 Receive Interrupt vector bits 7-0 reflect the transmit interrupt vector driven by the CD2401 to the PCCchip2 during a pseudo interrupt acknowledge cycle.

  • Page 232: Lanc Error Status And Interrupt Control Registers, Lanc Error Status Register

    PCCchip2 LANC Error Status and Interrupt Control Registers This section provides addresses and bit level descriptions of the LANC interrupt control registers and status register. LANC Error Status Register ADR/SIZ NAME OPER RESET SCLR LTO,EXT,PRTY 3-34 $FFF42028 (8 bits) PRTY 0 PL Writing a 1 to this bit clears bits 25 through 27 (LTO, EXT, and PRTY).

  • Page 233: Ca Lanc Interrupt Control Register

    OPER RESET 0 PL 0 PL IL2-IL0 ICLR E/L* PLTY http://www.motorola.com/computer/literature $FFF4202A (8 bits) ICLR 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for the 82596CA LANC. Level 0 does not generate an interrupt.

  • Page 234: Lanc Bus Error Interrupt Control Register

    PCCchip2 LANC Bus Error Interrupt Control Register ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 ICLR SC1-SC0 Note 3-36 $FFF4202B (8 bits) ICLR 0 PL 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level. Level 0 does not generate an interrupt. Writing a logic 1 into this bit clears the INT status bit.

  • Page 235: Programming The Scsi Error Status And Interrupt Registers, Scsi Error Status Register

    ADR/SIZ NAME OPER RESET SCLR LTO,EXT,PRTY http://www.motorola.com/computer/literature $FFF4202C (8 bits) PRTY 0 PL Writing a 1 to this bit clears bits 25 through 27 (LTO, EXT, and PRTY). Reading this bit always yields 0. These bits indicate the status of the last Local Bus error condition encountered by the SCSI processor while performing DMA accesses to the Local Bus.

  • Page 236: Scsi Interrupt Control Register

    PCCchip2 SCSI Interrupt Control Register ADR/SIZ NAME OPER RESET 0 PL IL2-IL0 3-38 $FFF4202F (8 bits) 0 PL 0 PL 0 PL 0 PL Interrupt Request Level. These three bits select the interrupt level for the SCSI Processor. Level 0 does not generate an interrupt.

  • Page 237: Programming The Printer Port, Printer Ack Interrupt Control Register

    OPER RESET 0 PL 0 PL IL2-IL0 ICLR E/L* PLTY http://www.motorola.com/computer/literature $FFF42030 (8 bits) ICLR 0 PL 0 PL 0 PL 0 PL These three bits select the interrupt level for the printer ACK. Level 0 does not generate an interrupt.

  • Page 238: Printer Fault Interrupt Control Register

    PCCchip2 Printer FAULT Interrupt Control Register ADR/SIZ NAME PLTY OPER RESET 0 PL IL2-IL0 ICLR E/L* PLTY 3-40 $FFF42031 (8 bits) E/L* ICLR 0 PL 0 PL 0 PL 0 PL These three bits select the interrupt level for the printer FAULT.

  • Page 239: Printer Sel Interrupt Control Register

    OPER RESET 0 PL 0 PL IL2-IL0 ICLR E/L* PLTY http://www.motorola.com/computer/literature $FFF42032 (8 bits) ICLR 0 PL 0 PL 0 PL These three bits select the interrupt level for the printer SEL. Level 0 does not generate an interrupt. In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.

  • Page 240: Printer Pe Interrupt Control Register

    PCCchip2 Printer PE Interrupt Control Register ADR/SIZ NAME PLTY OPER RESET 0 PL IL2-IL0 ICLR E/L* PLTY 3-42 $FFF42033 (8 bits) E/L* ICLR 0 PL 0 PL 0 PL 0 PL These three bits select the interrupt level for the printer PE.

  • Page 241: Printer Busy Interrupt Control Register

    OPER RESET 0 PL 0 PL IL2-IL0 ICLR E/L* PLTY http://www.motorola.com/computer/literature $FFF42034 (8 bits) ICLR 0 PL 0 PL 0 PL These three bits select the interrupt level for the printer BUSY. Level 0 does not generate an interrupt. In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.

  • Page 242: Printer Input Status Register

    PCCchip2 Printer Input Status Register ADR/SIZ NAME PINT OPER RESET PINT 3-44 $FFF42036 (8 bits) This bit reflects the state of the Printer Busy input pin. It is 1 when BSY is high and 0 when BSY is low. This bit reflects the state of the Printer Paper Error input pin.

  • Page 243: Printer Port Control Register

    FAST Note The PCCchip2 runs at half the MPU speed on the MVME177P. For example, an MVME177P with a 50 MHz MPU will run the PCCchip2 at 25 MHz. http://www.motorola.com/computer/literature $FFF42037 (8 bits) DOEN 0 PL 0 PL Manual Strobe Control - This bit selects the auto or manual mode for the printer strobe.

  • Page 244: Chip Speed Register

    PCCchip2 DOEN Chip Speed Register ADR/SIZ NAME OPER RESET CS31-CS16 3-46 Printer Input Prime - This bit controls the input prime signal. When this bit is high, the input prime signal is activated. When this bit is low, the input prime signal is not activated.

  • Page 245: Printer Data Register

    Printer Data Register ADR/SIZ NAME OPER RESET PD15-PD0 http://www.motorola.com/computer/literature $FFF4203A (16-bits) 15-0 PD15 - PD0 Writing to these bits causes the PCCchip2 to latch data into the external printer data buffer. Generally the printer data buffer only connects to PD7-PD0, because most printer data paths are 8 bits wide.

  • Page 246: Interrupt Priority Level Register

    PCCchip2 Interrupt Priority Level Register ADR/SIZ NAME OPER RESET IPL2-IPL0 3-48 $FFF4203E (8 bits) Interrupt Priority Level - These bits reflect the priority- encoded interrupt request level. This level is a combination of the PCCchip2 interrupt requests and the interrupt requests driven onto the EIPL2-EIPL0 pins. Note that when the C040 bit is cleared, external devices can drive EIPL2-EIPL0 with their interrupt requests.

  • Page 247: Interrupt Mask Level Register

    OPER RESET MSK2-MSK0 Interrupt Mask Level - The interrupt mask level bits MSK2 http://www.motorola.com/computer/literature $FFF4203F (8 bits) determine the level which must be exceeded by IPL2- IPL0 in order for the PCCchip2 to assert its INT pin. The MSK bits are encoded as follows:...

  • Page 248

    PCCchip2 3-50 Computer Group Literature Center Web Site...

  • Page 249

    4MCECC Functions Introduction The ECC DRAM Controller ASIC (MCECC) is a device used on earlier MVME167/177 models whose functions are now incorporated into the Petra chip on the MVME1x7. The two memory controllers modeled in Petra duplicate the functionality of the “parity memory controller” found in MC ASICs as well as that of the “single-bit error correcting/double-bit error detecting”...

  • Page 250

    MCECC Functions Features MCECC functions now implemented on the Petra chip include: Table 4-1. MCECC Functions on the Petra ASIC Function Memory Control 2-1-1-1 memory accesses (sustained) for burst writes 4-1-1-1 memory accesses (sustained) for burst reads (5-1-1-1 with BERR on or when FSTRD is cleared) Support for byte, two-byte, four-byte, and cache line read or write transfers Programmable base address for DRAM...

  • Page 251: General Description, Functional Description, Performance

    The Petra MCECC sector design is targeted for SDRAM devices of the PC100 type. Memory access time are not influenced by the settings of mode bits or SDRAM speed selections. The basic performance specifications for the MCECC sector are listed in Table 4-2. http://www.motorola.com/computer/literature Functional Description...

  • Page 252: Cache Coherency

    MCECC Functions Note Table 4-2. Memory System Cycle Timing Access Description Read Single Read Burst Write Burst Write Longword Write 1 or 2 Bytes 9 clock cycles Cache Coherency The MCECC sector supports the MC680x0 caching scheme on the local bus by always providing 32 bits of valid data during DRAM read cycles regardless of the number of bytes requested by the local bus master for the cycle.

  • Page 253: Cycle Types, Error Reporting, Single Bit Error (cycle Type = Burst Read Or Non-burst Read)

    3. Terminate the cycle normally. (Assert TA to the local bus.) 4. Log the error if not already logged. 5. Notify the local MPU via interrupt, if so enabled. http://www.motorola.com/computer/literature Functional Description...

  • Page 254: Double Bit Error (cycle Type = Burst Read Or Non-burst Read)

    MCECC Functions Double Bit Error (Cycle Type = Burst Read or Non-Burst Read) You cannot correct the data that is driven to the local MC680x0 bus. 1. Leave the error in DRAM. (Note that the error is not corrected in 2.

  • Page 255: Triple (or Greater) Bit Error (cycle Type = Non-burst Write)

    Triple (or Greater) Bit Error (Cycle Type = Scrub) Some of these errors are detected correctly and are treated the same as a double-bit error. The rest may show up as "no error" or "single-bit error", both of which are incorrect. http://www.motorola.com/computer/literature Functional Description...

  • Page 256: Error Logging, Scrub, Refresh

    MCECC Functions Error Logging ECC error logging is facilitated by the Petra MCECC sector because of its internal latches. When an error (single- or double-bit) occurs in the DRAMs to which the MCECC sector is connected, it freezes the address of the error and the syndrome bits associated with the data that is in error.

  • Page 257: Arbitration, Chip Defaults

    Software can override this initial setting by writing to the Defaults registers. However, it is not recommended that non-test software alter the contents of the Defaults registers. The actual values loaded into the Defaults registers are determined by board-level jumpers and configuration resistors. http://www.motorola.com/computer/literature Functional Description...

  • Page 258

    MCECC Functions Programming Model This section defines the programming model for the control and status registers (CSRs) in the MCECC sector. The base address of the CSRs is hard-coded to the address $FFF43000 for the MCECC sector on the first mezzanine board and to $FFF43100 for the MCECC sector on the second mezzanine board.

  • Page 259

    PERIOD SCRUB SBPD7 SBPD6 PERIOD CHIP CPS7 CPS6 PRESCALE SCRUB TIME SRDIS ON/OFF SCRUB PRESCALE SCRUB SPS15 SPS14 PRESCALE http://www.motorola.com/computer/literature Register Bit Names CID5 CID4 CID3 REV5 REV47 REV3 FSTRD BAD29 BAD28 BAD27 RWB5 RWB4 RWB3 BCK5 BCK47 BCK3 DERC...

  • Page 260

    MCECC Functions Table 4-3. MCECC Sector Internal Register Memory Map (Continued) MCECC Sector Base Address = $FFF43000 (1st board); $FFF43100 (2nd board) Register Offset Name SCRUB SPS7 PRESCALE SCRUB ST15 TIMER SCRUB TIMER SCRUB ADDR CNTR SCRUB SAC23 ADDR CNTR SCRUB SAC15 ADDR CNTR...

  • Page 261: Chip Revision Register, Chip Id Register

    Petra/MCECC ASIC. The current value of the register is $01. Although writes to this register are ignored, the MCECC sector pair always terminates the cycles properly with TA . ADR/SIZ 1st $FFF43004/2nd $FFF43104 (8-bits) NAME REV7 REV6 OPER RESET http://www.motorola.com/computer/literature CID5 CID4 CID3 CID2 REV5 REV4 REV3 REV2 Programming Model...

  • Page 262: Memory Configuration Register

    DRAM configurations from earlier programming models. For the actual SDRAM device and size options now applicable to the MVME1x7P boards, refer to FSTRD reflects the state of the FSTRD bit in Defaults Register 1. When 1, this bit indicates that DRAM reads are operating at full speed.

  • Page 263: Base Address Register, Dram Control Register

    The bit assignments for the DRAM Control register are: ADR/SIZ 1st $FFF43018/2nd $FFF43118 (8-bits) NAME BAD23 BAD22 RWB5 RWB4 OPER RESET 0 PLS 0 PLS RAMEN http://www.motorola.com/computer/literature BAD29 BAD28 BAD27 0 PLS 0 PLS 0 PLS RWB3 NCEIEN NCEBEN RAMEN 0 PLS...

  • Page 264: Bclk Frequency Register

    MCECC Functions NCEBEN Setting the NCEBEN control bit enables the MCECC pair NCEIEN When NCEIEN is set, the logging of a non-correctable RWB3 RWB4 RWB5 BAD22, BAD23 BCLK Frequency Register The Bus Clock (BCLK) Frequency register should be programmed with the hexadecimal value of the operating clock frequency in MHz (i.e., $19 for 25MHz and $21 for 33MHz).

  • Page 265: Data Control Register

    NAME BCK7 BCK6 OPER RESET Data Control Register ADR/SIZ 1st $FFF43020/2nd $FFF43120 (16-bits) NAME OPER RESET RWCKB http://www.motorola.com/computer/literature BCK5 BCK4 BCK3 BCK2 DERC ZFILL RWCKB 1 PLS 0 PLS 0 PLS READ/WRITE CHECKBITS, when set, enables the data from the seven checkbits in the Petra MCECC sector (bits 30-24) to be written and read on the local MC680x0 data bus.

  • Page 266

    MCECC Functions 1. Stop all scrub operations by clearing all of the STON bits and setting 2. Set the DERC and RWCKB bits in the Data Control register. 3. Perform the desired read and/or write checkbit operations. 4. Clear the DERC and RWCKB bits in the Data Control register. 5.

  • Page 267: Scrub Control Register

    0 PLS RWB0 SBEIEN SCRBEN This control bit enables the scrubber to operate. When http://www.motorola.com/computer/literature cleared during normal system operation. DERC also allows the write portion of a read-modify-write to complete regardless of whether or not there was a multiple bit error during the read portion of the read-modify-write.

  • Page 268: Scrub Period Register Bits 15-8, Scrub Period Register Bits 7-0

    MCECC Functions SCRB Scrub Period Register Bits 15-8 The Scrub Period Control register controls how often a scrub of the entire memory is performed if the SCRBEN bit is set in the Scrub Control register. The time between scrubs is approximately two seconds times the value programmed into the Scrub Period register.

  • Page 269: Chip Prescaler Counter, Scrub Time On/time Off Register

    Scrub Time On/Time Off Register ADR/SIZ 1st $FFF43034/2nd $FFF43134 (8-bits) NAME RWB7 STON2 OPER RESET 0 PLS 0 PLS STOFF2-STOFF0 http://www.motorola.com/computer/literature CPS57 CPS4 CPS3 CPS2 STON1 STON0 STOFF2 0 PLS 0 PLS 0 PLS STOFF2-STOFF0 control the amount of time that the scrubber refrains from requesting use of the DRAM each time it gives it up during a scrub.

  • Page 270

    MCECC Functions STOFF2 STOFF1 STON2-STON0 STON2 STON1 4-22 STOFF0 Scrubber Time Off Request DRAM immediately Request DRAM after 16 BCLK cycles Request DRAM after 32 BCLK cycles Request DRAM after 64 BCLK cycles Request DRAM after 128 BCLK cycles Request DRAM after 256 BCLK cycles Request DRAM after 512 BCLK cycles Request DRAM never STON2-STON0 control the amount of time that the...

  • Page 271: Scrub Prescaler Counter (bits 21-16), Scrub Prescaler Counter (bits 15-8)

    OPER RESET 0 PLS 0 PLS http://www.motorola.com/computer/literature Note that if STON2-0 is zero, the scrubber always releases the DRAM after one memory cycle, even if neither the local bus nor refresher need it. Read/Write Bit 7 is a general-purpose read/write bit.

  • Page 272: Scrub Prescaler Counter (bits 7-0), Scrub Timer Counter (bits 15-8)

    MCECC Functions Scrub Prescaler Counter (Bits 7-0) This register reflects the current value in the scrub prescaler bits 7-0. ADR/SIZ NAME SPS7 OPER RESET 0 PLS Scrub Timer Counter (Bits 15-8) This read/write register is the Scrub Timer counter. If scrubbing is enabled and the Scrub Period register is non-zero, the Scrub Timer counter increments approximately once every two seconds until it matches the value programmed into the Scrub Period register, at which time it clears...

  • Page 273: Scrub Timer Counter (bits 7-0), Scrub Address Counter (bits 26-24)

    This register reflects the current value in the Scrub Address counter bits 26-24. ADR/SIZ 1st $FFF4304C/2nd $FFF4314C (8-bits) NAME OPER RESET http://www.motorola.com/computer/literature 0 PLS 0 PLS 0 PLS 0 PLS SAC26 0 PLS Programming Model...

  • Page 274: Scrub Address Counter (bits 23-16), Scrub Address Counter (bits 15-8), Scrub Address Counter (bits 7-4)

    MCECC Functions Scrub Address Counter (Bits 23-16) This register reflects the current value in the Scrub Address counter bits 23-16. ADR/SIZ NAME SAC23 OPER RESET 0 PLS Scrub Address Counter (Bits 15-8) This register reflects the current value in the Scrub Address counter bits 15-8.

  • Page 275: Error Logger Register

    ERRLOG OPER RESET 0 PLS 0 PLS EALT ESCRB http://www.motorola.com/computer/literature ESCRB EALT 0 PLS 0 PLS 0 PLS SINGLE BIT ERROR is set when the last error logged was due to a single-bit error. It is cleared when a 1 is written to the ERRLOG bit.

  • Page 276: Error Address (bits 31-24), Error Address (bits 23-16)

    MCECC Functions ERRLOG When set, ERRLOG indicates that a single- or a double- Error Address (Bits 31-24) This register reflects the value that was on bits 31-24 of the local MC680x0 address bus at the last logging of an error. ADR/SIZ NAME EA31...

  • Page 277: Error Address (bits 15-8), Error Address (bits 7-4)

    This register reflects the value that was on bits 7-4 of the local MC680x0 bus at the last logging of an error. ADR/SIZ 1st $FFF4306C/2nd $FFF4316C (8-bits) NAME OPER RESET 0 PLS 0 PLS http://www.motorola.com/computer/literature EA13 EA12 EA11 EA10 0 PLS 0 PLS 0 PLS 0 PLS...

  • Page 278: Error Syndrome Register, Defaults Register 1

    MCECC Functions Error Syndrome Register ADR/SIZ NAME OPER RESET 0 PLS S6-S0 Defaults Register 1 ADR/SIZ NAME RWB7 OPER RESET 0 PL It is not recommended that non-test software write to this register. RSIZ2-RSIZ0 4-30 1st $FFF43070/2nd $FFF43170 (16-bits) 0 PLS 0 PLS 0 PLS 0 PLS...

  • Page 279

    RSIZ2 RSIZ1 SELI1, SELI0 SELI1 FSTRD http://www.motorola.com/computer/literature RSIZ0 DRAM Array Size 16MB 32MB 64MB 128MB Reserved Reserved The states of RSIZ2-0 after reset (power-up, soft, or local) match those of the RSIZ2-0 bits from the reset serial bit stream. The SELI1, SELI0 control bits determine the base address...

  • Page 280: Defaults Register 2

    MCECC Functions RWB6 RWB7 Defaults Register 2 ADR/SIZ NAME 0 OPER R/W RESET 0 PLS It is not recommended that non-test software write to this register. RESST2-RESST0 4-32 being set. The state of FSTRD after a reset (power-up, soft, or local) is determined by board-level configuration resistors.

  • Page 281: Sdram Configuration Register

    1st $FFF4307c/2nd $FFF4317c (8-bits) NAME OPER RESET 0 PLS 0 PLS SDCFG2-SDCFG0 SDCFG2 SDCFG1 http://www.motorola.com/computer/literature SDCFG2 SDCFG1 SDCGF0 0 PLS V PLS V PLS V PLS Define the physical SDRAM memory population on the printed circuit board: SDCFG0 DRAM Array Size...

  • Page 282: Initialization

    MCECC Functions Initialization Most DRAM vendors require that the DRAMs be subjected to some number of access cycles before the DRAMs are fully operational. The MCECC does not perform this initialization automatically, but depends on software to perform enough dummy accesses to DRAM to meet the requirement.

  • Page 283

    11. Clear the ZFILL bit in the MCECC pair. (Clear Bit 28 of offset $20.) 12. The entire DRAM that is controlled by this MCECC is now zero- filled. The software can now program the appropriate scrubbing mode and other desired initialization, and enable DRAM for operation. http://www.motorola.com/computer/literature Programming Model 4-35...

  • Page 284: Syndrome Decoding

    MCECC Functions Syndrome Decoding The following table defines the syndrome bit encoding for the Petra/MCECC ASIC. A syndrome code value of $00 indicates no error found. All other syndrome code values denote an error. The bit in error is decoded as shown in the table. Bit in Error Bit 0 Bit 1...

  • Page 285

    SDRAM configuration, the following table relates bits in the Error Address register to the physical bank where the error originated. Table 4-5. Identifying SDRAM Bank in Error SDCFG2 SDCFG1 http://www.motorola.com/computer/literature DRAM Array Size and Bank with SDCFG0 the Error Device is 64Mbit x 16 data with one bank composed of 3 devices.

  • Page 286

    MCECC Functions 4-38 Computer Group Literature Center Web Site...

  • Page 287

    Petra ASIC on the MVME167P and MVME177P single-board computers. Differences in function and implementation between previous MVME167 and MVME177 models and the new MVME1x7P boards are listed in the following table.. Function MCECC memory control MCECC ASIC, revision 00.

  • Page 288

    Summary of Changes Computer Group Literature Center Web Site...

  • Page 289: Connection Diagrams

    Introduction This appendix has connection diagrams for the printer port and the four serial ports on the MVME1X7P. These ports are connected to external devices through an MVME712M transition module. The configuration of the serial ports as Data Terminal Equipment (DTE) or Data Circuit-terminating Equipment (DCE) is accomplished by jumpers on the transition module.

  • Page 290

    Printer and Serial Port Connections Figure B-1. MVME1X7P Printer Port with MVME712M Computer Group Literature Center Web Site...

  • Page 291

    Connection Diagrams Figure B-2. MVME1X7P Serial Port 1 Configured as DCE http://www.motorola.com/computer/literature...

  • Page 292

    Printer and Serial Port Connections Figure B-3. MVME1X7P Serial Port 2 Configured as DCE Computer Group Literature Center Web Site...

  • Page 293

    Connection Diagrams Figure B-4. MVME1X7P Serial Port 3 Configured as DCE http://www.motorola.com/computer/literature...

  • Page 294

    Printer and Serial Port Connections Figure B-5. MVME1X7P Serial Port 4 Configured as DCE Computer Group Literature Center Web Site...

  • Page 295

    Connection Diagrams Figure B-6. MVME1X7P Serial Port 1 Configured as DTE http://www.motorola.com/computer/literature...

  • Page 296

    Printer and Serial Port Connections Figure B-7. MVME1X7P Serial Port 2 Configured as DTE Computer Group Literature Center Web Site...

  • Page 297

    Connection Diagrams Figure B-8. MVME1X7P Serial Port 3 Configured as DTE http://www.motorola.com/computer/literature...

  • Page 298

    Printer and Serial Port Connections Figure B-9. MVME1X7P Serial Port 4 Configured as DTE B-10 Computer Group Literature Center Web Site...

  • Page 299: Mcg Documents

    CRelated Documentation MCG Documents The Motorola Computer Group publications listed below are referenced in this manual. You can obtain paper or electronic copies of MCG publications by: Contacting your local Motorola sales office Visiting MCG’s World Wide Web literature site, http://www.motorola.com/computer/literature...

  • Page 300: Manufacturers' Documents

    M68000 Family Reference Manual MC68060 Microprocessor User’s Manual Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 E-mail: ldcformotorola@hibbertco.com Web: http://www.mot.com/SPS...

  • Page 301: Related Specifications

    NOTE: An earlier version of the VME specification is available as: Versatile Backplane Bus: VMEbus Institute of Electrical and Electronics Engineers, Inc. Publication and Sales Department 345 East 47th Street New York, New York 10017-21633 Telephone: 1-800-678-4333 http://www.motorola.com/computer/literature Related Specifications Publication Number Z85230pb.pdf Publication Number...

  • Page 302

    Related Documentation Table C-3. Related Specifications (Continued) Microprocessor system bus for 1 to 4 byte data Bureau Central de la Commission Electrotechnique Internationale 3, rue de Varembé Geneva, Switzerland ANSI Small Computer System Interface-2 (SCSI-2), Draft Document X3.131- 198X, Revision 10c Global Engineering Documents 15 Inverness Way East Englewood, CO 80112-5704...

  • Page 303

    Numerics 53C710 SCSI controller 1-15, 82596CA LAN coprocessor 1-14, LAN coprocessor memory map LANC Interrupt Control Register A16/D16 space, VMEbus 2-37 A16/D16 space, VMEchip2 ASIC A16/D32 space, VMEbus 2-37 A16/D32 space, VMEchip2 ASIC A24/D16 space, VMEbus 2-37, A24/D16 space, VMEchip2 ASIC A32/D16 space, VMEbus 2-37, A32/D16 space, VMEchip2 ASIC ABORT switch interrupt, address...

  • Page 304

    BBSY* signal, VMEbus BERR* signal, VMEbus BGIN filters, VMEbus binary number, symbol for block (D64) access cycles, VMEbus 2-33, 2-36 block access cycles, VMEbus 2-33, block diagrams MVME1X7P board PCCchip2 ASIC VMEchip2 ASIC block transfer cycles, VMEchip2 DMAC mode modes, DMAC 2-59...

  • Page 305

    2-26 devices, normal address range 1-20 DFAIR bit 2-14 differences from previous boards direct mode DMAC 2-51 PCCchip2 ASIC http://www.motorola.com/computer/literature and serial interface transfers, no-address-increment DMA Controller (DMAC), VMEchip2 ASIC 2-10, 2-51 DMAC command packets interrupter, VMEbus LTO error 1-58...

  • Page 306

    VMEbus 2-34, fair mode, VMEchip2 2-8, fast read bit status 4-14 IN-4 features MCECC sector MVME1X7P PCCchip2 ASIC VMEchip2 ASIC Flash memory devices 1-8, 3-39 functional description VMEchip2 ASIC 3-42 GCSR...

  • Page 307

    1 3-26 tick timer 2 3-25 interrupt acknowledge map 1-46 base vectors, VMEbus 2-95 control register, VMEchip2 2-101 http://www.motorola.com/computer/literature counter, DMAC handler routine, how to set up mask level 3-49 interrupt enable GPIO 3-24 2-103 LANC bus error LANC interrupt...

  • Page 308

    Interrupt Priority Level register (PCCchip2 ASIC) 3-48 interrupt sources PCCchip2 VBR 3-17 VMEchip2 ASIC 2-18 interrupt status GPIO 3-24 LANC bus error 3-36 LANC interrupt 3-35 printer acknowledge printer busy 3-43 printer fault 3-40 printer input 3-44 printer paper error printer select 3-41 SCC modem...

  • Page 309

    SCSI ID 1-45 local-bus-to-VMEbus Enable Control register 2-49 I/O Control register 2-50 interface 1-18 interface, VMEchip2 http://www.motorola.com/computer/literature map decoders, programming requester requester register, programming location monitor 2-95 interrupters, VMEbus 2-98 status register (VMEchip2 ASIC) location monitors LM0-LM3 (VMEchip2 ASIC)

  • Page 310

    MVME167Bug/177Bug debugging packages 1-52 MVME1X7P example of VMEchip2 Tick Timer 1 features functional description 1-42 microprocessors 1-41 MVME712M, MVME1X7P printer port no-address-increment DMA transfers 1-46 non-burst read cycle type non-burst write cycle type Computer Group Literature Center Web Site Index 1-42 1-34...

  • Page 311

    3-18 SCC Error Status register and Interrupt Control registers 3-27 SCSI controller interface tick timer support 1-16, http://www.motorola.com/computer/literature Vector Base register periodic interrupt example periodic interrupts (PCCchip2 ASIC) Petra ASIC functionality of redundancies with VMEchip2 PIACK register, modem...

  • Page 312

    Printer Input Status register (PCCchip2 ASIC) 3-44 Printer PE Interrupt Control register (PCCchip2 ASIC) printer port connection MVME1X7P, MVME712M B-2, B-3, B-4, B-5, B-6, B-7, B-8, B-9, B-10 printer port connection diagrams Printer Port Control register (PCCchip2 ASIC) 3-45 Printer SEL Interrupt Control register...

  • Page 313

    VMEbus segment 2-30, 2-31 slave map decoders, VMEbus 2-26 snoop control SCC receive 3-30 http://www.motorola.com/computer/literature snoop control bits snoop control register snoop control, LANC bus error snoop function enabling 2-28, 2-32, snoop signal lines (DMAC) snooping, definition of 1-49,...

  • Page 314

    TEA source 3-34 Tick Timer 1 Compare register Tick Timer 1 Control register (PCCchip2 ASIC) 3-23 Tick Timer 1 counter (PCCchip2 ASIC) Tick Timer 1 Interrupt Control register (PCCchip2 ASIC) Tick Timer 2 Compare register (PCCchip2 ASIC) 3-19 Tick Timer 2 Control register (PCCchip2 ASIC) 3-22 Tick Timer 2 counter (PCCchip2 ASIC)

  • Page 315

    GCSR programming model 2-100 programming model 2-20 watchdog timer function 1-17 VMEchip2/Petra chip redundancies http://www.motorola.com/computer/literature watchdog timer 2-26 VMEchip2 1-17, 2-14, write post buffer buffer, VMEchip2 ASIC 2-36 bus error interrupter, VMEbus 2-33 enable bits...

  • Page 316

    IN-14 Computer Group Literature Center Web Site Index...

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