Vector Base Register - Motorola MVME1X7P Programmer's Reference Manual

PCCchip2
3

Vector Base Register

3-16
C040 CPU040. This bit should remain set to indicate that the
MPU is from the M68000 family. When the bit is set,
EIPL<2..0> are driven as outputs which carry the
priority encoded interrupt request from the PCCchip2
interrupt sources. When the bit is cleared, EIPL<2..0>
are not driven as outputs, but are inputs only.
DR0 Download ROM at 0 (not applicable to MVME1X7P).
This bit should remain cleared, so that DROM appears
only in its normal address range. (When DR0 is set,
DROM also appears at $00000000 through $0001FFFF.)
DR0 is cleared by power-up or local reset, but if no other
device responds (within a certain amount of time) to the
first memory access after the reset, then the PCCchip2 sets
DR0. This causes the DROM to respond to the memory
access (and all memory accesses thereafter until software
clears DR0).
Note
V=1 if no other device responds to the first memory access
after Power-up or Local Reset. Otherwise V=0.
The Interrupt Vector Base Register is located at $FFF42003. It is an 8-bit
read/write register that is used to supply the vector to the MPU during an
interrupt acknowledge cycle for: the two internal tick timers, LAN
interrupt, LAN BERR interrupt, SCSI interrupt, GPIO interrupt, and
parallel port interrupts. Only the most significant four bits are used. The
least significant four bits encode the interrupt source during the
acknowledge cycle. The exception to this is that after reset occurs, the
interrupt vector passed is $0F, which remains in effect until a write is
generated to the Vector Base Register.
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