Table of Contents
Advertisement
RSIZ2
SELI1, SELI0
FSTRD
http://www.motorola.com/computer/literature
RSIZ1
RSIZ0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
The states of RSIZ2-0 after reset (power-up, soft, or local)
match those of the RSIZ2-0 bits from the reset serial bit
stream.
The SELI1, SELI0 control bits determine the base address
at which the control and status registers respond, as shown
below:
SELI1
SELI0
Register Base Address
0
1
1
0
SELI1 and SELI0 are initialized by hardware after a
power-up, soft, or local reset. Their initialized state is
determined by board-level configuration resistors.
The FSTRD control bit determines the speed at which
SDRAM reads occur. When it is 1, SDRAM reads happen
at full speed. When it is 0, SDRAM reads are slowed by
one clock, unless they are already slowed by NCEBEN
DRAM Array Size
4MB
8MB
16MB
32MB
64MB
128MB
Reserved
Reserved
$FFF43000
$FFF43100
Programming Model
4-31
4
Advertisement
Table of Contents
