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MCECC Functions
Initialization
4
4-34
Most DRAM vendors require that the DRAMs be subjected to some
number of access cycles before the DRAMs are fully operational. The
MCECC does not perform this initialization automatically, but depends on
software to perform enough dummy accesses to DRAM to meet the
requirement. The number of cycles required is fewer than 10. If there are
multiple blocks of DRAM, software has to perform at least 10 accesses to
each block.
The MCECC pair provides a fast zero-fill capability. The sequence shown
below performs such a zero fill. It zeroes all of the DRAM controlled by
this MCECC pair at the rate of 100MB/second when the BCLK pin is
operating at 25MHz. This sequence may have to be altered to perform the
scrub more slowly if the scrub causes the DRAM to consume too much
power at full speed.
1. Make sure that the scrubber is disabled by clearing the SCRBEN bit
in the Scrub Control register. (Clear bit 27 of offset $24.)
2. Make sure that the scrubber is done with any old scrub cycles by
waiting for the SCRB bit in the Scrub Control register to be cleared.
(Wait for bit 28 of offset $24 = 0.)
3. Discontinue all accesses from the MC680x0 bus to the DRAM.
4. Ensure that all accesses have stopped by clearing the RAMEN bit in
the DRAM Control register. (Clear bit 0 of offset $18)
5. Set the ZFILL bit in the MCECC pair. (Set Bit 28 of offset $20)
6. Set the Scrub Time On/Time Off register for the maximum rate and
to do write cycles, by setting the SRDIS bit, setting all of the STON
bits, and clearing all of the STOFF bits. (Write $B8 to offset $34)
7. Enable scrubbing by setting the SCRBEN bit in the Scrub Control
register. (Set bit 27 of offset $24.)
8. Ensure that the zero-fill has started by waiting for the SCRB bit in
the Scrub Control register to be set. (Wait for bit 28 of offset $24 =
1.)
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