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D15
DRO
COMPARE REGISTER
COUNTER REGISTER
COMPARE REGISTER
COUNTER REGISTER
OVERFLOW
COUNTER 2
TIC2
TIC2
INT
IEN
SCC
SCC
TX
IRQ
IEN
LAN
LAN
LAN
LAN
INT
INT
INT
IEN
PLTY
E/L*
PRTR
PRTR
PRTR
PRTR
SEL
SEL
SEL
SEL
PLTY
E/L*
INT
IEN
PRTR
PRTR
ANY
ACK
INT
This sheet begins on facing page.
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D8
CPU
MSTR
FAST
040
INT
BRAM
EN
CLR
COC
TIC
OVF
EN
EN
2
2
2
TIC2
TIC TIMER 2
ICLR
IRQ LEVEL
SCC
SCC TRANSMIT
TX
TX
IRQ LEVEL
AVEC
LAN
LAN INT
ICLR
IRQ LEVEL
PRTR
PRTR SEL
SEL
IRQ LEVEL
ICLR
PRTR
PRTR
PRTR
PRTR
FLT
SEL
PE
BSY
PRINTER DATA
INTERRUPT
IPL LEVEL
D7
VECTOR BASE REGISTER
OVERFLOW
COUNTER 1
TIC1
TIC1
TIC1
INT
IEN
ICLR
SCC
SCC
SCC
SCC
SCC
RX
RX
RX
SC1
SC0
IRQ
IEN
AVEC
SCC MODEM PIACK
SCC RECEIVE PIACK
LAN
LAN
LAN
LAN
LAN
ERR
ERR
ERR
SC1
SC0
INT
IEN
ICLR
SCSI
SCSI
IRQ
IEN
PRTR
PRTR
PRTR
PRTR
PRTR
PE
PE
PE
PE
PE
PLTY
E/L*
INT
IEN
ICLR
PRTR
PRTR
DAT
INP
ENBL
Programming Model
D0
CLR
COC
TIC
OVF
EN
EN
1
1
1
TIC TIMER 1
IRQ LEVEL
SCC RECEIVE
IRQ LEVEL
LAN ERR
IRQ LEVEL
SCSI INT
IRQ LEVEL
PRTR PE
IRQ LEVEL
PRTR
PRTR
PRTR
FAST
MAN
STB
ASTB
STB
INTERRUPT
MASK LEVEL
1362 9403
3-13
3
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