Table 1-2. Functions Duplicated In Vmechip2 And Petra Asics - Motorola MVME1X7P Programmer's Reference Manual

Table 1-2. Functions Duplicated in VMEchip2 and Petra ASICs

VMEchip2
Address
$FFF40060
$FFF40060
$FFF4004C
$FFF40048
$FFF40048
$FFF40048
$FFF40048
$FFF40064
$FF800000-$FFBFFFFF
$FFE00000-$FFEFFFFF
Notes
1.
2. Watchdog timer control.
3. Access and watchdog timer parameters.
4. MPU TEA (bus error) status
5. Bit numbering for the VMEchip2 and Petra ASICs has a one-to-one
6.
7. The SRAM and EPROM decoder in the VMEchip2 (version 2) must
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Bit #
28-24
22-19,
17,16
13-8
7
9
10
11
31-0
31-0 $FF800000-$FFBFFFFF
31-0
switch control.
RESET
correspondence.
switch interrupt control. Implemented also in the
ABORT
VMEchip2, but with a different bit organization (refer to the
VMEchip2 description in Chapter 2). In the MVME1X7P, the
switch is wired to the Petra chip, not the VMEchip2.
ABORT
be disabled by software before any accesses are made to these
address spaces.
Functional Description
Petra Chip
Address
$FFF42044
$FFF42044
$FFF42044
$FFF42048
$FFF42048
$FFF42048
$FFF42048
$FFF4204C
$FFF42040
Programmable
Notes
Bit #
28-24 1,5
22-19, 2,5
17,16
13-8 3,5
8 4
9 4,5
10 4,5
11 4,5
3-0 8
6- 0 6
31-0 7
31-0 7
1-19
1