Pci Memory Map; Vme Memory Map; Pci Local Bus Memory Map; Vmebus Memory Map - Motorola MVME5100 Manual

7 Programming the MVME5100
4. The only method to generate a PCI Interrupt Acknowledge cycle (8259 IACK) is to
perform a read access to the Hawks PIACK Register at 0xFEFF0030.
5. VME should be placed at the top of PCI memory space.
The following table shows the programmed values for the associated Hawk PCI Host Bridge
Registers for the suggested Processor Memory Map.

Table 7-3. Hawk PPC Register Values for Suggested Memory Map

Address
FEFF 0040
FEFF 0044
FEFF 0048
FEFF 004C
FEFF 0050
FEFF 0054
FEFF 0058
FEFF 005C

PCI Memory Map

Following a reset, the Hawk ASIC disables all PCI slave map decoders. The MVME5100 is fully
capable of supporting both PREP and CHRP PCI Memory Maps with RAM size limited to 2GB.

VME Memory Map

The MVME5100 is fully capable of supporting both the PREP and the CHRP VME Memory
Maps examples with RAM size limited to 2GB.

PCI Local Bus Memory Map

The PCI memory map is controlled by the MPU/PCI bus bridge controller portion of the Hawk
ASIC and by the Universe PCI/VME bus bridge ASIC. The Hawk and Universe devices adjust
system mapping to suit a given application via programmable map decoder registers.
No default PCI memory map exists. Resetting the system turns the PCI map decoders off, and
they must be reprogrammed in software for the intended application.
For detailed PCI memory maps, including suggested CHRP- and PREP-compatible memory
maps, refer to the MVME5100-Series Single Board Computer Programmer's Reference Guide.

VMEbus Memory Map

The VMEbus is programmable. Like other parts of the MVME5100 memory map, the mapping
of local resources as viewed by VMEbus masters varies among applications.
76
MVME5100 Installation and Use (V5100A/IH5)
Register Name
MSADD0
MSOFF0 & MSATT0
MSADD1
MSOFF1 & MSATT1
MSADD2
MSOFF2 & MSATT2
MSADD3
MSOFF3 & MSATT3
Register Name
X000 F3FF [X:1..8]
0000 00C2
FE00 FE7F
0200 00C0
0000 0000
0000 0000
0000 0000
0000 0000