Figure 2-4 Register Organization In Thumb State - ARM ARM7TDMI Technical Reference Manual

Programmer's Model
2.6.2 The Thumb-state register set
System and User
r0
r1
r2
r3
r4
r5
r6
r7
SP
LR
PC
CPSR
= banked register
2-10
The Thumb-state register set is a subset of the ARM-state set. The programmer has
access to:
• 8 general registers, r0–r7
• the PC
• the SP
• the LR
• the CPSR.
There are banked SPs, LRs, and SPSRs for each privileged mode. This register set is
shown in Figure 2-4.
Thumb-state general registers and program counter
FIQ Supervisor
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6
r7 r7
SP_fiq SP_svc
LR_fiq LR_svc
PC PC
Thumb-state program status registers
CPSR CPSR
SPSR_fiq SPSR_svc
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Abort IRQ
r0 r0
r1 r1
r2 r2
r3 r3
r4 r4
r5 r5
r6 r6
r7 r7
SP_abt SP_irq
LR_abt LR_irq
PC PC
CPSR CPSR
SPSR_abt SPSR_irq

Figure 2-4 Register organization in Thumb state

Undefined
r0
r1
r2
r3
r4
r5
r6
r7
SP_und
LR_und
PC
CPSR
SPSR_und
ARM DDI 0210C