ARM ARM7TDMI Technical Reference Manual page 92

Memory Interface
3-22
ARM7TDMI core test chip example system
Connecting the ARM7TDMI processor data bus, D[31:0] to an external shared bus
requires additional logic that varies between applications in the case of a test chip.
In this application, care must be taken to prevent bus clash on D[31:0] when the data
bus drive changes direction. The timing of nENIN, and the pad control signals must be
arranged so that when the core starts to drive out, the pad drive onto D[31:0] is disabled
before the core starts to drive. Similarly, when the bus switches back to input, the core
must stop driving before the pad is enabled.
Figure 3-17 on page 3-23 shows the circuit implemented in the ARM7TDMI processor
test chip.
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