ARM ARM7TDMI Technical Reference Manual page 129

ARM DDI 0210C
A breakpointed instruction does not cause the ARM7TDMI core to enter debug state
when:
• A branch or a write to the PC precedes the breakpointed instruction. In this case,
when the branch is executed, the core flushes the instruction pipeline and so
cancels the breakpoint.
• An exception occurs before the breakpointed instruction reaches the Execute
stage of the pipeline. This causes the processor to flush the instruction pipeline
and so cancel the breakpoint. In normal circumstances, on exiting from an
exception, the ARM7TDMI core branches back to the next instruction to be
executed before the exception occurred. In this case, the pipeline is refilled and
the breakpoint is reflagged.
Entry into debug state on watchpoint
Watchpoints occur on data accesses. Depending on whether you have set bit [4] in the
debug control register, the core instruction processing stops, or an abort exception is
executed (Abort on page 2-19). A watchpoint is always taken, but the core might not
enter debug state immediately. In all cases, the current instruction completes. If the
current instruction is load or store multiple instruction (
elapse before the watchpoint is taken.
On a watchpoint, the following sequence occurs:
1. The current instruction completes.
2. All changes to the core state are made.
3. Load data is written into the destination registers.
4. Base write-back is performed.
If a watchpoint occurs when an exception is pending (even when
is reset), the core enters debug state in the same mode as the exception.
Entry into debug state on debug request
The ARM7TDMI processor can be forced into debug state on debug request in either of
the following ways:
• through EmbeddedICE-RT logic programming (see Programming breakpoints on
page B-47 and Programming watchpoints on page B-50)
• by asserting the DBGRQ pin.
The DBGRQ pin is an asynchronous input and is therefore synchronized by logic inside
the ARM7TDMI processor before it takes effect. Following synchronization, the core
normally enters debug state at the end of the current instruction. However, if the current
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Debug Interface
or ), many cycles can
LDM STM
Monitor mode enable
5-9