Table 7-21 Ale Address Control Timing Parameters; Table 7-22 Ape Address Control Timing Parameters; Figure 7-23 Ape Address Control - ARM ARM7TDMI Technical Reference Manual

ARM DDI 0210C
Note
In Figure 7-22 on page 7-18, T
latch the current address in phase 2. If ALE is driven LOW after T
is latched. This is known as address breakthrough.
The timing parameters used in Figure 7-22 on page 7-18 are listed in Table 7-21.
MCLK
APE
T
A[31:0]
aph
nRW
LOCK
nOPC
nTRANS
MAS[1:0]
The timing parameters used in Figure 7-23 are listed in Table 7-22.
Symbol
T
ape
T
apeh
T
aph
T
aps
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is the time by which ALE must be driven LOW to
ald

Table 7-21 ALE address control timing parameters

Symbol Parameter
T Address group latch output time
ald
T Address group latch open output delay
ale
T Address group latch output hold time
aleh
T
aps

Table 7-22 APE address control timing parameters

Parameter
MCLKf to address group valid
Address group output hold time from MCLKf
APE hold time from MCLKf
APE set up time to MCLKr
AC and DC Parameters
, then a new address
ald
Parameter
type
Maximum
Maximum
Minimum
T
apeh
T
ape

Figure 7-23 APE address control

Parameter
type
Maximum
Minimum
Minimum
Minimum
7-19