ARM ARM7TDMI Technical Reference Manual page 237

B.8.3 Exit from debug state
ARM DDI 0210C
When the core returns to debug state after a system-speed access, bit [33] of scan chain
1 is driven HIGH. This gives the debugger information about why the core entered
debug state the first time this scan chain is read.
Restrictions on setting BREAKPT
The instruction types that can be executed with bit [33] of scan chain 1 (BREAKPT)
set are:
• load instructions
• store instructions
• load multiple instructions
• store multiple instructions.
The following sequence is performed on leaving debug state:
1. The internal state of the ARM7TDMI core is restored.
2. A branch is generated to the next instruction to be executed.
A branch instruction must be loaded into the pipeline. See Behavior of the
program counter in debug state on page B-30 for a description of how to calculate
the branch.
3. The ARM7TDMI core synchronizes back to MCLK.
Bit [33] of scan chain 1 is used to force the ARM7TDMI core to resynchronize back to
MCLK, as follows:
1. The penultimate instruction of the debug sequence is scanned in with bit [33] set
HIGH.
2. The final instruction of the debug sequence is the branch and this is scanned in
with bit [33] LOW.
3. The core is clocked to load the branch into the pipeline.
4. The RESTART instruction is selected in the TAP controller.
5. When the state machine enters the RUN-TEST-IDLE state, the scan chain reverts
back to system mode and clock resynchronization to MCLK occurs in the core.
The ARM7TDMI core resumes normal operation, fetching instructions from memory.
The delay, until the state machine is in the RUN-TEST-IDLE state, enables conditions
to be set up in other devices in a multiprocessor system without taking immediate effect.
Then, when the RUN-TEST-IDLE state is entered, all processors resume operation
simultaneously.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Debug in Depth
B-27