Software Interrupt And Exception Entry; Table 6-15 Software Interrupt Instruction Cycle Operations - ARM ARM7TDMI Technical Reference Manual

6.12

Software interrupt and exception entry

Cycle Address
1 pc+2L
2 Xn
3 Xn+4
Xn+8
ARM DDI 0210C
Exceptions (including software interrupts) force the PC to a particular value and cause
the instruction pipeline to be refilled. During the first cycle the forced address is
constructed, and a mode change can take place. The return address is moved to R14 and
the CPSR to SPSR_svc.
During the second cycle the return address is modified to facilitate return, though this
modification is less useful than in the case of the branch with link instruction.
The third cycle is required only to complete the refilling of the instruction pipeline.
The cycle timings are listed in Table 6-15 where:
• pc for:
— software interrupts is the address of the SWI instruction
— Prefetch Aborts is the address of the aborting instruction
— Data Aborts is the address of the instruction following the one which
attempted the aborted data transfer
— other exceptions is the address of the instruction following the last one to
be executed before entering the exception
• C represents the current mode-dependent value
• T represents the current state-dependent value
• Xn is the appropriate trap address.
MA
S nRW Data
[1:0]
i 0 (pc+2L)
2 0 (Xn)
2 0 (Xn+4)
Copyright © 2001, 2004 ARM Limited. All rights reserved.

Table 6-15 Software Interrupt instruction cycle operations

nMREQ SEQ nOPC
0 0 0
0 1 0
0 1 0
Instruction Cycle Timings
nTRANS Mode
C old
1 exception
1 exception
TBI
T
T
0
0
6-19