ARM ARM7TDMI Technical Reference Manual page 210

Signal and Transistor Descriptions
Name
TBE
Test bus enable
TBIT
TCK
TCK1
TCK, phase one
TCK2
TCK, phase two
TDI
TDO
Test data output
TMS
VDD
Power supply
VSS
Ground
A-12
Type Description
IC When LOW, D[31:0], A[31:0], LOCK, MAS[1:0], nRW, nTRANS, and
nOPC are set to high impedance.
Similar in effect as if both ABE and DBE had been driven LOW. However,
TBE does not have an associated scan cell and so enables external signals to
be driven high impedance during scan testing.
Under normal operating conditions TBE must be HIGH.
O When the processor is executing the THUMB instruction set, this is HIGH.
It is LOW when executing the ARM instruction set.
This signal changes in phase two in the first execute cycle of a BX
instruction.
IC Clock signal for all test circuitry. When in debug state, this is used to
generate DCLK, TCK1, and TCK2.
O HIGH when TCK is HIGH (slight phase lag because of the internal clock
non-overlap).
O HIGH when TCK is LOW (slight phase lag because of the internal clock
non-overlap).
It is the non-overlapping complement of TCK1.
IC Serial data for the scan chains.
O Serial data from the scan chains.
IC Mode select for scan chains.
P Provide power to the device.
P These connections are the ground reference for all signals.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Table A-3 Signal descriptions (continued)
ARM DDI 0210C