Contents
Chapter 3
Chapter 6
iv
Memory Interface
3.1
3.2
Bus interface signals .................................................................................. 3-3
3.3
Bus cycle types .......................................................................................... 3-4
3.4
Addressing signals ................................................................................... 3-11
3.5
Address timing .......................................................................................... 3-14
3.6
Data timed signals .................................................................................... 3-17
3.7
3.8
3.9
4.1
About coprocessors .................................................................................... 4-2
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.1
5.2
Debug systems ........................................................................................... 5-4
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Monitor mode ............................................................................................ 5-21
Instruction Cycle Timings
6.1
6.2
6.3
6.4
Branch and Exchange ................................................................................ 6-6
6.5
Data operations .......................................................................................... 6-7
6.6
6.7
Load register ............................................................................................. 6-12
6.8
Store register ............................................................................................ 6-14
6.9
6.10
6.11
Data swap ................................................................................................. 6-18
6.12
6.13
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ARM DDI 0210C