ARM ARM7TDMI Technical Reference Manual page 44

Introduction
Operation
Unconditional
Long branch with link
Optional state change
•
•
Load With immediate offset
•
•
•
With register offset
•
•
•
•
•
PC-relative
SP-relative
Address
•
•
Multiple
Store With immediate offset
•
•
•
1-24
to address held in Lo reg
to address held in Hi reg
word
halfword
byte
word
halfword
signed halfword
byte
signed byte
using PC
using SP
word
halfword
byte
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Table 1-7 Thumb instruction set summary (continued)
Assembly syntax
B label
BL label
-
BX Rs
BX Hs
-
LDR Rd, [Rb, #7bit_offset]
LDRH Rd, [Rb, #6bit_offset]
LDRB Rd, [Rb, #5bit_offset]
-
LDR Rd, [Rb, Ro]
LDRH Rd, [Rb, Ro]
LDRSH Rd, [Rb, Ro]
LDRB Rd, [Rb, Ro]
LDRSB Rd, [Rb, Ro]
LDR Rd, [PC, #10bit_Offset]
LDR Rd, [SP, #10bit_Offset]
-
ADD Rd, PC, #10bit_Offset
ADD Rd, SP, #10bit_Offset
LDMIA Rb!, <reglist>
-
STR Rd, [Rb, #7bit_offset]
STRH Rd, [Rb, #6bit_offset]
STRB Rd, [Rb, #5bit_offset]
ARM DDI 0210C