ARM ARM7TDMI Technical Reference Manual page 228

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Debug in Depth
B-18
You use the TAP controller instructions to select one of the following basic modes of
operation of the scan chains:
INTEST mode
The core is tested internally. The data serially scanned in is
applied to the core and the resulting outputs are captured in the
output cells and scanned out.
EXTEST mode
Data is scanned onto the outputs of the core and applied to the
external system. System input data is captured in the input cells
and then shifted out.
SYSTEM mode
The scan cells are idle. System data is applied to inputs and core
outputs are applied to the system.
Scan chain 0
Scan chain 0 is intended primarily for inter-device testing, EXTEST, and testing the
core, INTEST. Scan chain 0 is selected using the SCAN_N instruction as described at
SCAN_N (b0010) on page B-10.
INTEST enables serial testing of the core. The TAP controller must be placed in
INTEST mode after scan chain 0 has been selected:
During CAPTURE-DR, the current outputs from the core logic are captured in the
output cells.
During SHIFT-DR, this captured data is shifted out while a new serial test pattern
is scanned in, therefore applying known stimuli to the inputs.
During RUN-TEST-IDLE, the core is clocked. Usually, the TAP controller only
spends one cycle in RUN-TEST-IDLE. The whole operation can then be repeated.
For a description of the core clocks during test and debug, see The ARM7TDMI core
clocks on page B-22.
EXTEST enables inter-device testing, useful for verifying the connections between
devices on a circuit board. The TAP controller must be placed in EXTEST mode after
scan chain 0 has been selected:
During CAPTURE-DR, the current inputs to the core logic from the system are
captured in the input cells.
During SHIFT-DR, this captured data is shifted out while a new serial test pattern
is scanned in, thus applying known values on the outputs of the core.
During UPDATE-DR, the value shifted into the scan cells appears on the outputs.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
ARM DDI 0210C

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