Store Register; Table 6-11 Store Register Instruction Cycle Operations - ARM ARM7TDMI Technical Reference Manual

Instruction Cycle Timings
6.8

Store register

Cycle
1
2
6-14
The first cycle of a store register instruction is similar to the first cycle of load register
instruction. During the second cycle the base modification is performed, and at the same
time the data is written to memory. There is no third cycle.
The cycle timings are listed in Table 6-11 where:
• c represents the current processor mode:
— c=0 for User mode
— c=1 for all other modes
• d=0 if the T bit has been specified in the instruction (such as LDRT) and d=c at
all other times.
• s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on
page 6-13).
Address MAS[1:0]
pc+2L i
alu s
pc+3L
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Table 6-11 Store register instruction cycle operations

nRW Data nMREQ
0 (pc+2L) 0
1 Rd 0
SEQ nOPC nTRANS
0 0 c
0 1 d
ARM DDI 0210C