ARM ARM7TDMI Technical Reference Manual page 164

Instruction Cycle Timings
CP
register Cycles Address
status
n registers 1 pc+8
(n>1) 2 pc+8
not ready • pc+8
b pc+8
b+1 alu
• alu+•
n+b alu+•
n+b+1 alu+•
pc+12
6-22
Table 6-17 Coprocessor data transfer instruction cycle operations (continued)
MA
S nRW
[1:0]
2 0
2 0
2 0
2 0
2 0
0
2 0
2 0
Note
Coprocessor data transfer operations are not available in Thumb state.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Data nMREQ SEQ
(pc+8) 1 0
- 1 0
- 1 0
- 0 0
(alu) 0 1
(alu+•) 0 1
(alu+•) 0 1
(alu+•) 0 0
nOPC nCPI CPA
0 0 0
1 0 0
1 0 0
1 0 0
1 1 0
1 1 0
1 1 0
1 1 1
ARM DDI 0210C
CPB
1
1
1
0
0
0
0
1