ARM ARM7TDMI Technical Reference Manual page 7

List of Tables
ARM7TDMI Technical Reference Manual
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 4-1
Table 4-2
ARM DDI 0210C
Change history .............................................................................................................. ii
Key to tables ........................................................................................................... 1-11
ARM instruction summary ....................................................................................... 1-13
Addressing modes .................................................................................................. 1-16
Operand 2 ............................................................................................................... 1-18
Fields ....................................................................................................................... 1-19
Condition fields ........................................................................................................ 1-19
Thumb instruction set summary .............................................................................. 1-22
Register mode identifiers .......................................................................................... 2-7
PSR mode bit values ............................................................................................... 2-15
Exception entry and exit .......................................................................................... 2-16
Exception vectors .................................................................................................... 2-21
Exception priority order ........................................................................................... 2-22
Bus cycle types ......................................................................................................... 3-5
Burst types ................................................................................................................ 3-7
Significant address bits ........................................................................................... 3-12
nOPC ...................................................................................................................... 3-12
nTRANS encoding .................................................................................................. 3-13
Tristate control of processor outputs ....................................................................... 3-21
Read accesses ........................................................................................................ 3-27
Use of nM[4:0] to indicate current processor mode ................................................ 3-31
Coprocessor availability ............................................................................................ 4-3
Handshaking signals ................................................................................................. 4-6
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