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Instruction Cycle Timings
6.17
Coprocessor register transfer, store to coprocessor
Cycle
ready
1
2
not ready
1
2
•
b
b+1
6-26
This is the same as described in Coprocessor register transfer, load from coprocessor
on page 6-25, except that the last cycle is omitted.
The cycle timings are listed in Table 6-20 where:
•
b represents the busy cycles.
Table 6-20 Coprocessor register transfer, store to coprocessor
MA
Address
S
nRW
[1:0]
pc+8
2
0
pc+12
2
1
pc+12
pc+8
2
0
pc+8
2
0
pc+8
2
0
pc+8
2
0
pc+12
2
1
pc+12
Note
Coprocessor register transfer operations are not available in Thumb state.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
Data
nMREQ
SEQ
(pc+8)
1
1
Rd
0
0
(pc+8)
1
0
-
1
0
-
1
0
-
1
1
Rd
0
0
nOPC
nCPI
CPA
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
1
1
ARM DDI 0210C
CPB
0
1
1
1
1
0
1
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