ARM ARM7TDMI Technical Reference Manual page 13

Figure 7-23
Figure B-1
Figure B-2
Figure B-3
Figure B-4
Figure B-5
Figure B-6
Figure B-7
Figure B-8
Figure B-9
Figure B-10
Figure B-11
Figure B-12
ARM DDI 0210C
APE address control ............................................................................................... 7-19
ARM7TDMI core scan chain arrangements .............................................................. B-4
Test access port controller state transitions .............................................................. B-5
ID code register format ............................................................................................ B-14
Output scan cell ...................................................................................................... B-17
Clock switching on entry to debug state .................................................................. B-22
Debug exit sequence .............................................................................................. B-28
EmbeddedICE-RT block diagram ........................................................................... B-43
Watchpoint control value and mask format ............................................................. B-45
Debug control register format .................................................................................. B-51
Debug status register format ................................................................................... B-54
Debug control and status register structure ............................................................ B-55
Debug abort status register ..................................................................................... B-56
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