ARM ARM7TDMI Technical Reference Manual page 8

List of Tables
Table 4-3
Table 4-4
Table 5-1
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table 6-6
Table 6-7
Table 6-8
Table 6-9
Table 6-10
Table 6-11
Table 6-12
Table 6-13
Table 6-14
Table 6-15
Table 6-16
Table 6-17
Table 6-18
Table 6-19
Table 6-20
Table 6-21
Table 6-22
Table 6-23
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
Table 7-20
Table 7-21
viii
Summary of coprocessor signaling ........................................................................... 4-7
Mode identifier signal meanings, nTRANS ............................................................. 4-17
DCC register access instructions ............................................................................ 5-18
Branch instruction cycle operations .......................................................................... 6-4
Thumb long branch with link ..................................................................................... 6-5
Branch and exchange instruction cycle operations .................................................. 6-6
Data operation instruction cycles .............................................................................. 6-8
Multiply instruction cycle operations ......................................................................... 6-9
Multiply accumulate instruction cycle operations ...................................................... 6-9
Multiply long instruction cycle operations ............................................................... 6-10
Multiply accumulate long instruction cycle operations ............................................ 6-10
Load register instruction cycle operations .............................................................. 6-12
MAS[1:0] signal encoding ....................................................................................... 6-13
Store register instruction cycle operations .............................................................. 6-14
Load multiple registers instruction cycle operations ............................................... 6-15
Store multiple registers instruction cycle operations ............................................... 6-17
Data swap instruction cycle operations .................................................................. 6-18
Software Interrupt instruction cycle operations ....................................................... 6-19
Coprocessor data operation instruction cycle operations ....................................... 6-20
Coprocessor data transfer instruction cycle operations .......................................... 6-21
coprocessor data transfer instruction cycle operations ........................................... 6-23
Coprocessor register transfer, load from coprocessor ............................................ 6-25
Coprocessor register transfer, store to coprocessor ............................................... 6-26
Undefined instruction cycle operations ................................................................... 6-27
Unexecuted instruction cycle operations ................................................................ 6-28
ARM instruction speed summary ............................................................................ 6-29
General timing parameters ....................................................................................... 7-4
ABE address control timing parameters ................................................................... 7-5
Bidirectional data write cycle timing parameters ....................................................... 7-6
Bidirectional data read cycle timing parameters ....................................................... 7-6
Data bus control timing parameters .......................................................................... 7-7
Output 3-state time timing parameters ..................................................................... 7-8
Unidirectional data write cycle timing parameters .................................................... 7-8
Unidirectional data read cycle timing parameters ..................................................... 7-9
Configuration pin timing parameters ....................................................................... 7-10
Coprocessor timing parameters .............................................................................. 7-10
Exception timing parameters .................................................................................. 7-11
Synchronous interrupt timing parameters ............................................................... 7-12
Debug timing parameters ....................................................................................... 7-13
DCC output timing parameters ............................................................................... 7-13
Breakpoint timing parameters ................................................................................. 7-14
TCK and ECLK timing parameters ......................................................................... 7-15
MCLK timing parameters ........................................................................................ 7-15
Scan general timing parameters ............................................................................. 7-16
Reset period timing parameters .............................................................................. 7-17
Output enable and disable timing parameters ........................................................ 7-18
ALE address control timing parameters .................................................................. 7-19
Copyright © 2001, 2004 ARM Limited. All rights reserved. ARM DDI 0210C