Table of Contents
Advertisement
Programmer's Model
2-20
Prefetch Abort
When a Prefetch Abort occurs, the ARM7TDMI processor marks the prefetched
instruction as invalid, but does not take the exception until the instruction reaches the
Execute stage of the pipeline. If the instruction is not executed, for example because it
fails its condition codes or because a branch occurs while it is in the pipeline, the abort
does not take place.
After dealing with the reason for the abort, the handler executes the following
instruction irrespective of the processor operating state:
SUBS PC,R14_abt,#4
This action restores both the PC and the CPSR, and retries the aborted instruction.
Data Abort
When a Data Abort occurs, the action taken depends on the instruction type:
•
Single data transfer instructions (LDR and STR). If write back base register is
specified by the instruction then the abort handler must be aware of this. In the
case of a load instruction the ARM7TDMI processor prevents overwriting of the
destination register with the loaded data.
•
Swap instruction (SWP):
—
on a read access suppresses the write access and the write to the destination
register
—
on a write access suppresses the write to the destination register.
•
Block data transfer instructions (LDM and STM) complete. When write-back is
specified, the base register is updated.
If the base register is in the transfer list and has already been overwritten with
loaded data by the time that the abort is indicated then the base register reverts to
the original value. The ARM7TDMI processor prevents all register overwriting
with loaded data after an abort is indicated. This means that the final value of the
base register is always the written-back value, if write-back is specified, at its
original value. It also means that the ARM7TDMI core always preserves r15 in
an aborted LDM instruction, because r15 is always either the last register in the
transfer list or not present in the transfer list.
After fixing the reason for the abort, the handler must execute the following return
instruction irrespective of the processor operating state at the point of entry:
SUBS PC,R14_abt,#8
This action restores both the PC and the CPSR, and retries the aborted instruction.
Copyright © 2001, 2004 ARM Limited. All rights reserved.
ARM DDI 0210C
- Quick Links:
- Architecture
Hide quick links:
Advertisement
Table of Contents
