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Functional Description
L2 Cache
3
Hawk ASIC
3-6
The PrPMC750 utilizes a back-side L2 cache structure via the MPC750
processor chip. MPC750 L2 cache is implemented with an onchip 2-way
set-associative tag memory and external direct-mapped synchronous
SRAMs for data storage. The external SRAMs are accessed through a
dedicated 72-bit wide (64 bits of data and 8 bits of parity) L2 cache port.
The MPC750 processor supports 256KB, 512KB or 1MB of L2 cache
SRAMs. The L2 cache can operate in copyback or writethru modes and
supports system cache coherency through snooping. Data parity
generation and checking can be disabled by programming the MPC750
accordingly. Refer to the MPC750 Data Sheet for additional information.
The Hawk ASIC provides the bridge function between the PPC60X bus,
the system memory, and the PCI Local Bus. The PCI interface provides 32
bit addressing and 64 bit data. PCI 64 bit addressing (dual address cycle)
is not supported.
There are four programmable map decoders for each direction to provide
flexible address mappings between the PowerPC and the PCI Local Bus.
Refer to the PRPMC750 Programmer's Reference Guide
(PRPMC750A/PG) for additional information and programming details.
The Hawk ASIC contains arbiters for the PPC bus and the PCI bus. The
PPC arbiter will be used to arbitrate between the processor and the Hawk
PPC bus master for ownership of the PPC bus. The MPC750 processor is
connected to the Hawk arbiter CPU0_REQ/CPU0_GNT signal pair
(XARB3/XARB0).
The Hawk PCI bus arbiter is disabled. PCI bus arbitration must be
provided by the carrier board.
The Hawk ASIC also provides an MPIC Interrupt Controller to handle
various interrupt sources. The interrupt sources include the four MPIC
Timer Interrupts, the Watchdog timer 1 interrupt, the four PCI interrupts
from the PMC connector, the two software interprocessor interrupts, and
the UART interrupt. The PrPMC750 can generate an interrupt to the host
processor on any of PMC interrupt lines INTA#-INTD# by activating the
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