Intel E5410 - Cpu Xeon Quad Core 2.33Ghz Fsb1333Mhz 12M Lga771 Tray Datasheet
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Intel E5410 - Cpu Xeon Quad Core 2.33Ghz Fsb1333Mhz 12M Lga771 Tray Datasheet

Intel E5410 - Cpu Xeon Quad Core 2.33Ghz Fsb1333Mhz 12M Lga771 Tray Datasheet

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Quad-Core Intel® Xeon® Processor
5400 Series
Datasheet
August 2008
318589-005

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Summary of Contents for Intel E5410 - Cpu Xeon Quad Core 2.33Ghz Fsb1333Mhz 12M Lga771 Tray

  • Page 1 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet August 2008 318589-005...
  • Page 2 The Quad-Core Intel® Xeon® Processor 5400 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

  • Page 3: Table Of Contents

    Processor Materials.................... 48 Processor Markings.................... 48 Processor Land Coordinates ................49 Land Listing......................51 Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments ......51 4.1.1 Land Listing by Land Name ..............51 4.1.2 Land Listing by Land Number ..............61 Signal Definitions ....................
  • Page 4 Debug Tools Specifications ..................117 Debug Port System Requirements ..............117 Target System Implementation................117 9.2.1 System Implementation................. 117 Logic Analyzer Interface (LAI) ................117 9.3.1 Mechanical Considerations ..............118 9.3.2 Electrical Considerations ................ 118 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet...
  • Page 5 2-15 Differential Rising and Falling Edge Rates ............. 42 Processor Package Assembly Sketch ..............43 Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 1 of 3) ..44 Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 2 of 3) ..45 Quad-Core Intel®...
  • Page 6 Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step) Thermal Specifications ....................81 Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile Table .82 Quad-Core Intel® Xeon® Processor X5400 Series Thermal Specifications ....83 Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table ....84 Quad-Core Intel®...

  • Page 7: Revision History

    Revision History Revision Description Date Initial release November 2007 Added product information for the Quad-Core Intel® Xeon® March 2008 Processor L5408. Added product information for the Quad-Core Intel® Xeon® April 2008 Processor L5400 Series. Corrected L1 cache size Introduced X5492...
  • Page 8 Quad-Core Intel® Xeon® Processor 5400 Series Datasheet...

  • Page 9: Introduction

    Intel’s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Quad- Core Intel® Xeon® Processor 5400 Series maintains the tradition of compatibility with IA-32 software. Some key features include on-die, primary 32-kB instruction cache and 32-kB write-back data cache in each core and 12 MB (2 x 6MB) Level 2 cache with ®...

  • Page 10: Terminology

    Further details on Intel Virtualization Technology can be found at http://developer.intel.com/technology/platform-technology/virtualization/index.htm. The Quad-Core Intel® Xeon® Processor 5400 Series is intended for high performance server and workstation systems. The Quad-Core Intel® Xeon® Processor 5400 Series supports a Dual Independent Bus (DIB) architecture with one processor on each bus, up to two processor sockets in a system.
  • Page 11 • Quad-Core Intel® Xeon® Processor L5408 - Intel 64-bit microprocessor intended for dual processor server blades and embedded servers. The Quad-Core Intel® Xeon® Processor L5408 is a lower voltage and lower power version of the Quad-Core Intel® Xeon® Processor 5400 Series supporting higher case temperatures.
  • Page 12 FSB speeds and bandwidth. • Flexible Motherboard Guidelines (FMB) – Estimate of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will have over certain time periods. Actual specifications for future processors may differ. • Functional Operation – Refers to the normal operating conditions in which all processor specifications, including DC, AC, FSB, signal quality, mechanical and thermal are satisfied.

  • Page 13: State Of Data

    Guidelines (TMDG) LGA771 Socket Mechanical Design Guide 313871 Quad-Core Intel® Xeon® Processor 5400 Series Boundary Scan Descriptive 318587 Language (BSDL) Model Notes: Contact your Intel representative for the latest revision of these documents Document is available publicly at http://developer.intel.com. §...

  • Page 15: Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications

    V . The on-die termination resistors are always enabled on the Quad-Core Intel® Xeon® Processor 5400 Series to control reflections on the transmission line. Intel chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals.

  • Page 16: Power And Ground Lands

    Due to its large number of transistors and high internal clock speeds, the Quad-Core Intel® Xeon® Processor 5400 Series is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.

  • Page 17: Front Side Bus Clock (Bclk[1:0]) And Processor Clocking

    Listed frequencies are not necessarily committed production frequencies. For valid processor core frequencies, see Quad-Core Intel® Xeon® Processor 5400 Series Specification Update. The lowest bus ratio supported by the Quad-Core Intel® Xeon® Processor 5400 Series is 1/6. 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) Upon power up, the FSB frequency is set to the maximum supported by the individual processor.

  • Page 18: Pll Power Supply

    Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines defines VID[7:0], VID7 and VID0 are not used on the Quad-Core Intel® Xeon® Processor 5400 Series; VID7 is always hard wired low at the voltage regulator.
  • Page 19 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage.

  • Page 20: Voltage Identification Definition

    When the “111111” VID pattern is observed, the voltage regulator output should be disabled. Shading denotes the expected VID range of the Quad-Core Intel® Xeon® Processor 5400 Series The VID range includes VID transitions that may be initiated by thermal events, assertion of the FORCEPR# signal (see ®...

  • Page 21: Reserved, Unused, And Test Signals

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-4. Loadline Selection Truth Table for LL_ID[1:0] LL_ID1 LL_ID0 Description Reserved ® ® Dual-Core Intel Xeon Processor 5100 series, Dual-Core Intel® Xeon® Processor 5200 Series, and Quad-Core Intel® Xeon® Processor 5400 Series Reserved ®...

  • Page 22: Front Side Bus Signal Groups

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The TESTHI signals must use individual pull-up resistors as detailed below. A matched resistor must be used for each signal: • TESTHI10 – cannot be grouped with other TESTHI signals • TESTHI11 – cannot be grouped with other TESTHI signals •...

  • Page 23: Agtl+ Signal Description Table

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-6. FSB Signal Groups (Sheet 2 of 2) Signal Group Type Signals CMOS Asynchronous Output Asynchronous BSEL[2:0], VID[6:1] FSB Clock Clock BCLK[1:0] TAP Input Synchronous to TCK TCK, TDI, TMS, TRST#...

  • Page 24: Cmos Asynchronous And Open Drain Asynchronous Signals

    Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The Quad-Core Intel® Xeon® Processor 5400 Series contains Digital Thermal Sensor (DTS) sprinkled both inside and outside the cores in a die.

  • Page 25: Input Device Hysteresis

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-10. PECI DC Electrical Limits Symbol Definition and Conditions Units Notes Input Voltage Range -0.150 Hysteresis 0.1 * V hysteresis Negative-edge threshold 0.275 * V 0.500 * V voltage Positive-edge threshold 0.550 * V...

  • Page 26: Mixing Processors

    FSB frequency, core frequency, power segments, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported.

  • Page 27: Processor Dc Specifications

    Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Quad-Core Intel® Xeon® Processor 5400 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ.
  • Page 28 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-12. Voltage and Current Specifications (Sheet 1 of 2) 1, 11 Symbol Parameter Unit Notes VID range 0.850 1.3500 for processor core Table 2-13 Table 2-14; 2, 3, 4, 6, 9...
  • Page 29 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-12. Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Unit Notes 1, 11 for V supply before V stable for V supply after V stable Thermal Design Current 6,14,18 CC_TDC (TDC) Quad-Core Intel®...

  • Page 30: Quad-Core Intel® Xeon® Processor X5482 Load Current Versus Time

    1.1 V. 17. I is specified while PWRGOOD and RESET# are asserted. CC_RESET 18. The Quad-Core Intel® Xeon® Processor X5482 is intended for dual processor workstations only. Figure 2-2. Quad-Core Intel® Xeon® Processor X5482 Load Current versus Time 16 0...

  • Page 31: Quad-Core Intel® Xeon® Processor X5400 Series Load Current Versus Time

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-3. Quad-Core Intel® Xeon® Processor X5400 Series Load Current versus Time 13 0 12 5 12 0 10 5 10 0 0 . 0 1 0 . 1 10 0 10 0 0...

  • Page 32: Quad-Core Intel® Xeon® Processor L5400 Series Load Current Versus Time

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-5. Quad-Core Intel® Xeon® Processor L5400 Series Load Current versus Time 0 .0 1 0 .1 10 0 10 0 0 Time Duration (s) Notes: Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than CC_TDC Not 100% tested.
  • Page 33 Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Table 2-13. Quad-Core Intel® Xeon® Processor X5482 V Static and Transient Tolerance (Sheet 2 of 2) Notes CC_Max CC_Typ CC_Min VID - 0.150 VID - 0.160 VID - 0.170 1,2,3 VID - 0.156 VID - 0.166...
  • Page 34 Please refer to the appropriate platform design guide for details on VR implementation. values greater than 102A are not applicable for the Quad-Core Intel® Xeon® Processor E5400 Series. values greater than 60A are not applicable for the Quad-Core Intel® Xeon® Processor L5400 Series.

  • Page 35: Transient Tolerance Load Lines

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-7. Quad-Core Intel® Xeon® Processor X5482 V Static and Transient Tolerance Load Lines Icc [A] 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 VID - 0.000...

  • Page 36: Transient Tolerance Load Lines

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-8. Quad-Core Intel® Xeon® Processor X5400 Series V Static and Transient Tolerance Load Lines Icc [A] 95 100 105 110 115 120 125 VID - 0.000 VID - 0.020 VID - 0.040 VID - 0.060...

  • Page 37: Quad-Core Intel® Xeon® Processor L5400 Series Vcc Static And Transient

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-10. Quad-Core Intel® Xeon® Processor L5400 Series VCC Static and Transient Tolerance Load Lines Icc [A] VID - 0.000 VID - 0.020 Maximum VID - 0.040 VID - 0.060 VID - 0.080 Typical VID - 0.100...

  • Page 38: Vcc Overshoot Specification

    0 V and V 2.13.2 Overshoot Specification The Quad-Core Intel® Xeon® Processor 5400 Series can tolerate short transient overshoot events where V exceeds the VID voltage when transitioning from a high- to-low current load condition. This overshoot cannot exceed VID + V...

  • Page 39: Die Voltage Validation

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-11. V Overshoot Example Waveform Example Overshoot Waveform VID + 0.050 VID - 0.000 Time [us] : Overshoot time above VID : Overshoot above VID Notes: VOS is the measured overshoot voltage.

  • Page 40: Agtl+ Bus Voltage Definitions

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications The AGTL+ reference voltages (GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END) must be generated on the baseboard using high precision voltage divider circuits. Refer to the appropriate platform design guidelines for implementation details. Table 2-19. AGTL+ Bus Voltage Definitions...

  • Page 41: Electrical Test Circuit

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. The crossing point must meet the absolute and relative crossing point specifications simultaneously.

  • Page 42: Differential Clock Crosspoint Specification

    Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications Figure 2-14. Differential Clock Crosspoint Specification 550 mV 550 + 0.5 (VHavg - 700) 250 + 0.5 (VHavg - 700) 250 mV 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 2-15.

  • Page 43: Mechanical Specifications

    Mechanical Specifications Mechanical Specifications The Quad-Core Intel® Xeon® Processor 5400 Series is packaged in a Flip Chip Land Grid Array (FC-LGA) package that interfaces to the baseboard via a LGA771 socket. The package consists of a processor core mounted on a pinless substrate with 771 lands. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink.

  • Page 44: Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 1 Of 3)

    Mechanical Specifications Figure 3-2. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 1 of 3) Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution are available in the processor Thermal/Mechanical Design Guidelines.
  • Page 45 Mechanical Specifications Figure 3-3. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 2 of 3)
  • Page 46 Mechanical Specifications Figure 3-4. Quad-Core Intel® Xeon® Processor 5400 Series Package Drawing (Sheet 3 of 3) Note: The optional dimple packing marking highlighted by Detail F from the above drawing may only be found on initial processors.

  • Page 47: Processor Component Keepout Zones

    For more information on the transient bend limits, please refer to the MAS document titled Manufacturing ® with Intel components using 771-land LGA package that interfaces with the motherboard via a LGA771 socket. Refer to the Quad-Core Intel® Xeon® Processor 5400 Series Thermal/Mechanical Design Guidelines (TMDG)for information on heatsink clip load metrology.

  • Page 48: Package Handling Guidelines

    LGA771 socket, which meets the criteria outlined in the LGA771 Socket Design Guidelines. Processor Mass Specifications The typical mass of the Quad-Core Intel® Xeon® Processor 5400 Series is 21.5 grams [0.76 oz.]. This includes all components which make up the entire processor product. Processor Materials The Quad-Core Intel®...

  • Page 49: Processor Land Coordinates

    Mechanical Specifications Figure 3-5. Processor Top-side Markings (Example) Mark Text (Production Mark): Legend: GROUP1LINE1 3200DP/12M/1600 GROUP1LINE1 GROUP1LINE2 Intel ® Xeon ® GROUP1LINE2 GROUP1LINE3 Proc# SXXX COO GROUP1LINE4 GROUP1LINE3 i (M) © ‘07 GROUP1LINE5 GROUP1LINE4 GROUP1LINE5 ATPO ATPO ATPO Note: 2D matrix is required for engineering samples only (encoded with ATPO-S/N).

  • Page 50: Processor Land Coordinates, Bottom View

    Mechanical Specifications Figure 3-7. Processor Land Coordinates, Bottom View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Address / Socket 771 Common Clock / Quadrants...

  • Page 51: Land Listing

    Land Listing Land Listing Quad-Core Intel® Xeon® Processor 5400 Series Pin Assignments This section provides sorted land list in Table 4-1 Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 a listing of all processor lands ordered by land number.
  • Page 52 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 3 of 20) (Sheet 4 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type BSEL0 CMOS ASync Output D33# Source Sync Input/Output...
  • Page 53 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 5 of 20) (Sheet 6 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type DP2# Common Clk Input/Output RESERVED DP3# Common Clk...
  • Page 54 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 7 of 20) (Sheet 8 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type RESERVED AD25 Power/Other RESERVED AD26 Power/Other RESERVED...
  • Page 55 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 9 of 20) (Sheet 10 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type AG30 Power/Other AK26 Power/Other Power/Other Power/Other Power/Other...
  • Page 56 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 11 of 20) (Sheet 12 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 57 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 13 of 20) (Sheet 14 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other AB24 Power/Other Power/Other AB25 Power/Other Power/Other...
  • Page 58 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 15 of 20) (Sheet 16 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type AF29 Power/Other AK23 Power/Other Power/Other AK24 Power/Other...
  • Page 59 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 17 of 20) (Sheet 18 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 60 Land Listing Table 4-1. Land Listing by Land Name Table 4-1. Land Listing by Land Name (Sheet 19 of 20) (Sheet 20 of 20) Signal Buffer Signal Buffer Pin Name Direction Pin Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...

  • Page 61: Land Listing By Land Number

    Land Listing 4.1.2 Land Listing by Land Number Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 2 of 20) (Sheet 1 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type...
  • Page 62 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 3 of 20) (Sheet 4 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type AD26 Power/Other Power/Other...
  • Page 63 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 5 of 20) (Sheet 6 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type AG18 Power/Other AH27...
  • Page 64 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 7 of 20) (Sheet 8 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other AL18 Power/Other...
  • Page 65 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 9 of 20) (Sheet 10 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type AM26 Power/Other D10#...
  • Page 66 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 11 of 20) (Sheet 12 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type BNR# Common Clk Input/Output...
  • Page 67 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 13 of 20) (Sheet 14 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other DSTBP2# Source Sync...
  • Page 68 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 15 of 20) (Sheet 16 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other Power/Other Power/Other...
  • Page 69 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 17 of 20) (Sheet 18 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other Power/Other Power/Other...
  • Page 70 Land Listing Table 4-2. Land Listing by Land Number Table 4-2. Land Listing by Land Number (Sheet 19 of 20) (Sheet 20 of 20) Signal Buffer Signal Buffer Pin No. Pin Name Direction Pin No. Pin Name Direction Type Type Power/Other Power/Other Power/Other...

  • Page 71: Signal Definitions

    ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. This signal must be connected to the appropriate pins on all Quad-Core Intel® Xeon® Processor 5400 Series FSB agents. ADSTB[1:0]# Address strobes are used to latch A[37:3]# and REQ[4:0]# on their rising and falling edge.
  • Page 72 Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 8) Name Type Description Notes BCLK[1:0] The differential bus clock pair BCLK[1:0] (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V CROSS...
  • Page 73 If a debug port connector is implemented in the system, DBR# is a no- connect on the Quad-Core Intel® Xeon® Processor 5400 Series package. DBR# is not a processor signal.
  • Page 74 CPUID Instruction application note. FORCEPR# The FORCEPR# (force power reduction) input can be used by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to activate the Thermal Control Circuit (TCC). GTLREF_ADD_MID GTLREF_ADD determines the signal reference level for AGTL+ address and common clock input lands.
  • Page 75 Signal Definitions Table 5-1. Signal Definitions (Sheet 5 of 8) Name Type Description Notes GTLREF_DATA_MID GTLREF_DATA determines the signal reference level for AGTL+ data input lands. GTLREF_DATA is used by the AGTL+ receivers to GTLREF_DATA_END determine if a signal is a logical 0 or a logical 1. Please refer to Table 2-19 and the appropriate platform design guidelines for additional details.
  • Page 76 • Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3. MS_ID[1:0] These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying.
  • Page 77 To protect the processor its core voltage (V ) must be removed following the assertion of THERMTRIP#. Intel also recommends the removal of V when THERMTRIP# is asserted. Driving of the THERMTRIP# signals is enabled within 10 μs of the assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD.
  • Page 78 Xeon® Processor 5400 Series package. Notes: For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the maximum number of symmetric agents is one. Maximum number of priority agents is zero. For this processor land on the Quad-Core Intel® Xeon® Processor 5400 Series, the maximum number of symmetric agents is two.

  • Page 79: Thermal Specifications

    Thermal Specifications Package Thermal Specifications The Quad-Core Intel® Xeon® Processor 5400 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
  • Page 80 Quad-Core Intel® Xeon® Processor L5408 Series in Embedded Applications Thermal/Mechanical Design Guidelines (TMDG). The Quad-Core Intel® Xeon® Processor X5400 Series supports a dual Thermal Profile, either of which can be implemented. Both ensure adherence to the Intel reliability requirements. Thermal Profile A (see Figure 6-2;...

  • Page 81: Quad-Core Intel® Xeon® Processor X5492 And X5482 (C-Step)Thermal Profile

    Table 6-2 for discrete points that constitute the thermal profile. Implementation of the Quad-Core Intel® Xeon® Processor X5482 Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.

  • Page 82: Quad-Core Intel® Xeon® Processor X5492 And X5482 (C-Step)Thermal Profile Table

    Thermal Specifications Table 6-2. Quad-Core Intel® Xeon® Processor X5492 and X5482 (C-step)Thermal Profile Table Power (W) (°C) CASE_MAX 35.0 35.9 36.9 37.8 38.7 39.7 40.6 41.5 42.5 43.0 44.4 45.3 46.2 47.2 48.1 49.0 50.0 50.9 51.8 52.8 53.7 54.6 55.6...

  • Page 83: Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profiles A And B

    Table 6-4 discrete points that constitute the thermal profile. Implementation of the Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss.

  • Page 84: Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table

    Thermal Specifications Table 6-4. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile A Table Power (W) (°C) CASE_MAX 42.8 43.6 44.5 45.3 46.2 47.0 47.8 48.7 49.5 50.0 51.2 52.0 52.9 53.7 54.6 55.4 56.2 57.1 57.9 58.8 59.6 60.4 61.3...

  • Page 85: Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile B Table

    Thermal Specifications Table 6-5. Quad-Core Intel® Xeon® Processor X5400 Series Thermal Profile B Table Power (W) (°C) CASE_MAX 43.5 44.6 45.7 46.8 47.9 49.0 50.1 51.2 52.3 53.4 54.6 55.7 56.8 57.9 59.0 60.1 61.2 62.3 63.4 64.5 65.6 66.7 67.8...

  • Page 86: Quad-Core Intel® Xeon® Processor E5400 Series Thermal Profile

    Table 6-7 for discrete points that constitute the thermal profile. Implementation of the Quad-Core Intel® Xeon® Processor 5400 Series Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.

  • Page 87: Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile

    Table 6-9 for discrete points that constitute the thermal profile. Implementation of the Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.

  • Page 88: Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile Table

    Thermal Specifications Table 6-9. Quad-Core Intel® Xeon® Processor L5400 Series Thermal Profile Table Power (W) (°C) CASE_MAX 42.1 43.6 45.1 46.6 48.1 49.6 51.0 52.5 54.0 55.5 57.0 Table 6-10. Quad-Core Intel® Xeon® Processor L5408 Thermal Specifications Thermal Design Minimum...

  • Page 89: Quad-Core Intel® Xeon® Processor L5408 Thermal Profile

    Table 6-11 for discrete points that constitute the thermal profile. Implementation of the Quad-Core Intel® Xeon® Processor L5408 Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet the processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss.

  • Page 90: Thermal Metrology

    Monitor 1 and Intel® Thermal Monitor 2 must both be enabled in BIOS for the processor to be operating within specifications. When both are enabled, Intel® Thermal Monitor 2 will be activated first and Intel® Thermal Monitor 1 will be added if Intel® Thermal Monitor 2 is not effective.
  • Page 91 Thermal/Mechanical Design Guidelines (TMDG) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Intel® Thermal Monitor 1, is factory configured and cannot be modified. The Intel® Thermal Monitor 1 does not require any additional hardware, software drivers, or interrupt handling routines.

  • Page 92: On-Demand Mode

    This mechanism is referred to as “On- Demand” mode and is distinct from the Intel® Thermal Monitor 1 and Intel® Thermal Monitor 2 features. On-Demand mode is intended as a means to reduce system level...

  • Page 93: Prochot# Signal

    The FORCEPR# (force power reduction) input can be used by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to activate the TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal.

  • Page 94: Thermtrip# Signal

    6.2.5 THERMTRIP# Signal Regardless of whether or not Intel® Thermal Monitor 1 or Intel® Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the...

  • Page 95: Conceptual Fan Control Diagram Of Peci-Based Platforms

    Thermal Specifications should utilize the relative temperature value delivered over PECI in conjunction with the MSR value to control or optimize fan speeds. Figure 6-9 shows a conceptual CONTROL fan control diagram using PECI temperatures. The relative temperature value reported over PECI represents the data below the onset of thermal control circuit (TCC) activation as needed by PROCHOT# assertions.

  • Page 96: Peci Specifications

    Thermal Specifications 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The PECI device address for socket 0 is 0x30 and socket 1 is 0x31. Please note that each address also supports two domains (Domain0 and Domain1). For more information on PECI domains, please refer to the Platform Environment Control Interface (PECI) Specification.

  • Page 97: Features

    Address lands not identified in this table as configuration options should not be asserted during RESET#. Disabling of any of the cores within the Quad-Core Intel® Xeon® Processor 5400 Series must be handled by configuring the EXT_CONFIG Model Specific Register (MSR).

  • Page 98: Normal State

    RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either ® Normal Mode or the HALT state. See the Intel 64 and IA-32 Architecture Software Developer's Manual.

  • Page 99: Quad-Core Intel® Xeon® Processor X5400 Series

    Notes 1 Extended HALT State EXTENDED_HALT Power Quad-Core Intel® Xeon® Processor X5482 Extended HALT State EXTENDED_HALT Power Quad-Core Intel® Xeon® Processor X5400 Series Extended HALT State 16/20 EXTENDED_HALT Power Quad-Core Intel® Xeon® Processor E5400 Series Extended HALT State EXTENDED_HALT Power Quad-Core Intel®...

  • Page 100: Stop-Grant State

    20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle. By default, the Quad-Core Intel® Xeon® Processor 5400 Series will issue two Stop Grant Acknowledge special bus cycles, one for each die.

  • Page 101: Extended Halt Snoop Or Halt Snoop State, Stop Grant Snoop State

    Note: Not all Quad-Core Intel® Xeon® Processor 5400 Series are capable of supporting Enhanced Intel SpeedStep Technology. More details on which processor frequencies will support this feature will be provided in the Quad-Core Intel® Xeon® Processor 5400 Series Specification Update.
  • Page 102 This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The Quad-Core Intel® Xeon® Processor 5400 Series has hardware logic that coordinates the requested voltage (VID) between the processor cores.

  • Page 103: Boxed Processor Specifications

    The Quad-Core Intel® Xeon® Processor 5400 Series will be offered as an Intel boxed processor. Intel will offer the Quad-Core Intel® Xeon® Processor 5400 Series with two heat sink configurations available for each processor frequency: 1U passive/3U+ active combination solution and a 2U passive only solution.

  • Page 104: Boxed Quad-Core Intel® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan)

    Boxed Processor Specifications Figure 8-1. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan) Figure 8-2. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 2U Passive Heat Sink...

  • Page 105: Mechanical Specifications

    Boxed Processor Specifications Figure 8-3. 2U Passive Quad-Core Intel® Xeon® Processor 5400 Series Thermal Solution (Exploded View) Notes: The heat sinks represented in these images are for reference only, and may not represent the final boxed processor heat sinks. The screws, springs, and standoffs will be captive to the heat sink. This image shows all of the components in an exploded view.

  • Page 106: Top Side Board Keepout Zones (Part 1)

    Boxed Processor Specifications Figure 8-4. Top Side Board Keepout Zones (Part 1)

  • Page 107: Top Side Board Keepout Zones (Part 2)

    Boxed Processor Specifications Figure 8-5. Top Side Board Keepout Zones (Part 2)

  • Page 108: Bottom Side Board Keepout Zones

    Boxed Processor Specifications Figure 8-6. Bottom Side Board Keepout Zones...

  • Page 109: Board Mounting-Hole Keepout Zones

    Boxed Processor Specifications Figure 8-7. Board Mounting-Hole Keepout Zones...

  • Page 110: Volumetric Height Keep-Ins

    Boxed Processor Specifications Figure 8-8. Volumetric Height Keep-Ins...

  • Page 111: Pin Fan Cable Connector (For Active Cek Heat Sink)

    Boxed Processor Specifications Figure 8-9. 4-Pin Fan Cable Connector (For Active CEK Heat Sink)

  • Page 112: Pin Base Board Fan Header (For Active Cek Heat Sink)

    Boxed Processor Specifications Figure 8-10. 4-Pin Base Board Fan Header (For Active CEK Heat Sink)

  • Page 113: Boxed Processor Heat Sink Weight

    Boxed Processor Specifications 8.2.2 Boxed Processor Heat Sink Weight 8.2.2.1 Thermal Solution Weight The 1U passive/3U+ active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams. Note that this is per processor, a dual processor system will have up to 2010 grams total mass in the heat sinks.

  • Page 114: Boxed Processor Cooling Requirements

    Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself. The baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket.

  • Page 115: Boxed Processor Contents

    5°C with an external ambient temperature RISE of 35°C. These specifications apply to both copper and aluminum heatsink solutions. Following these guidelines allows the designer to meet Quad-Core Intel® Xeon® Processor 5400 Series Thermal Profile and conform to the thermal requirements of the processor.
  • Page 116 Boxed Processor Specifications §...

  • Page 117: Debug Tools Specifications

    Debug Port System Requirements The Quad-Core Intel® Xeon® Processor 5400 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug. The debug port, which is connected to the FSB, is a combination of the system, JTAG and execution signals.

  • Page 118: Mechanical Considerations

    Debug Tools Specifications 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI plugs into the socket, while the processor plugs into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer.

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