1MRK 502 066-UUS B
V
Vpickup>
ANSI10000100 V2 EN-US
Figure 342: Detailed logic diagram for step 1, Definite time delay, DT operation
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000037 V2 EN-US
Figure 343: Example for Definite Time Delay stage 1 reset
Technical manual
tReset1
a
a>b
b
OFF
Delay
t1
t
t
ON
Delay
Voltage protection
PU_ST1
TRST1
AND
ANSI10000100-2-en.vsd
ANSI10000037-2-en.vsd
Section 9
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