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7542 Group
f(X
) oscillation: enabled
IN
State 2
On-chip oscillator: enabled
MISRG
=1
1
2
MISRG
(MISRG
f(X
) oscillation: enabled
IN
State 2'
On-chip oscillator: enabled
State 2'a (Note 5)
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG
is set to "1".
3
Internal RESET does not occur.
Prohibitive state
MUC will be locked when Ceramic
or RC oscillation is stopped.
MISRG
=1
MISRG
2
2
State 2'b
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG
is set to "1".
3
Internal RESET occurs.
Oscillation stop detection circuit is in active. (Note 6)
Operation clock source: f(X
Notes on switch of clock
(1) In operation clock = f(X
f(X
)/2 (High-speed mode)
IN
f(X
)/8 (Middle-speed mode)
IN
f(X
) (Double-speed mode, only at a ceramic oscillation)
IN
(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.
R
/1 (On-chip oscillator double-speed mode)
OSC
R
/2 (On-chip oscillator high-speed mode)
OSC
R
/8 (On-chip oscillator middle-speed mode)
OSC
R
/128 (On-chip oscillator low-speed mode)
OSC
(3) Executing the state transition state 3 to 2 or state 3 to 3' after stabilizing X
(4) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2' → state 3',
R
/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.
OSC
(5) MCU cannot be returned by On-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected.
Accordingly, do not execute the transition to state 2'a.
(6) STP instruction cannot be used when oscillation stop detection circuit is in active.
Fig. 83 State transition 2
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
CPUM
=10
76
2
(Note 4)
CPUM
=00
76
2
01
2
11
2
=0
1
2
(Note 3)
is cleared to "0".)
3
CPUM
=10
76
2
CPUM
=00
76
2
01
2
11
2
=0
2
2
CPUM
=10
76
2
(Note 4)
CPUM
=00
76
2
01
2
11
2
) (Note 1)
IN
), the following can be selected for the CPU clock division ratio.
IN
Page 66 of 134
f(X
) oscillation: enabled
IN
State 3
On-chip oscillator: enabled
MISRG
=1
MISRG
=0
1
2
1
2
(Note 3)
(MISRG
is cleared to "0".)
3
f(X
) oscillation: enabled
IN
State 3'
On-chip oscillator: enabled
State 3'a
Oscillation stop reset disabled
When oscillation stop is detected;
MISRG
is set to "1".
3
Internal RESET does not occur.
State 3'c
Release from internal reset
MISRG
is set to "1".
3
Oscillation status can be
confirmed by reading MISRG
.
3
MISRG
=1
MISRG
=0
2
2
2
2
State 3'b
Oscillation stop reset enabled
When oscillation stop is detected;
MISRG
is set to "1".
3
Internal RESET occurs.
Operation clock source: On-chip oscillator (Note 2)
oscillation.
IN
Reset
released
RESET state 1
(Note 4)
f(X
) oscillation: enabled
IN
On-chip oscillator: enabled
Applied "L" to RESET pin
(external reset)
MISRG
is cleared to "0".
3
Reset
RESET state 2
released
f(X
) oscillation: enabled
IN
(Note 4)
On-chip oscillator: enabled
Oscillation stop is detected
(internal reset)
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