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7542 Group
(2) Asynchronous Serial I/O2 (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O2 mode selection bit of the serial I/O2 control
register to "0".
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
P0
/R
D
ST detector
4
X
2
P0
/S
6
CLK2
BRG count source selection bit
X
IN
1/4
P0
/T
D
5
X
2
Fig. 62 Block diagram of UART serial I/O2
Transmit or receive clock
Transmit buffer 2
write signal
TBE=0
TSC=0
TBE=1
Serial output T
D
2
X
Receive buffer 2
read signal
Serial input R
D
X
2
Notes
1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O2 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1."
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 63 Operation of UART serial I/O2 function
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Data bus
Address 002E
Receive buffer register 2
OE
Character length selection bit
7 bits
Receive shift register 2
8 bits
PE FE
Serial I/O2 synchronous clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 2
ST/SP/PA generator
Character length selection bit
Data bus
TBE=0
ST
D
D
0
1
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
ST
D
D
0
1
Page 52 of 134
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
16
Serial I/O2 control register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
SP detector
Clock control circuit
Address 0032
16
1/16
Transmit interrupt source selection bit
Transmit shift register 2
Transmit buffer register 2
Address
002E
16
TBE=1
ST
SP
RBF=1
SP
ST
Address 0030
16
1/16
UART2 control register
Address 0031
Transmit shift completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address
Serial I/O2 status register
D
D
0
1
Generated at 2nd bit in 2-stop-bit mode
RBF=0
D
D
0
1
16
002F
16
TSC=1
SP
RBF=1
SP
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