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7542 Group
Serial I/O
The 7542 Group has Serial I/O1 and Serial I/O2. Except that Serial
I/O1 has the bus collision detection function and the T
structure for Serial I/O2 is CMOS only, they have the same function.
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
P 1
/ R
D
/ C A P
0
X
1
0
P 1
/ S
2
C L K 1
BRG count source selection bit
X
IN
P 1
/ S
3
R D Y 1
P 1
/ T
D
1
X
1
Fig. 52 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Receive enable signal S
RDY1
Write pulse to receive/transmit
buffer register 1 (address 0018
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Fig. 53 Operation of clock synchronous serial I/O1 function
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
D
X
2
Receive buffer register 1
R e c e i v e s h i f t r e g i s t e r 1
1 / 4
Falling-edge detector
F / F
Transmit shift register 1
T r a n s m i t b u f f e r r e g i s t e r 1
1
D
0
D
1
0
)
16
TBE = 0
TBE = 1
TSC = 0
pin.
1
Page 46 of 134
(1) Clock Synchronous Serial I/O1 Mode
Clock synchronous serial I/O1 mode can be selected by setting
output
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6) to "1".
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O1 control register
A d d r e s s 0 0 1 8
1 6
S h i f t c l o c k
Clock control circuit
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator 1
Address 001C
16
C l o c k c o n t r o l c i r c u i t
Shift clock
A d d r e s s 0 0 1 8
1 6
Data bus
D
D
D
1
2
3
D
D
D
1
2
3
A d d r e s s 0 0 1 A
R e c e i v e b u f f e r f u l l f l a g ( R B F )
Receive interrupt request (RI)
1 / 4
T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C )
Transmit interrupt source selection bit
T r a n s m i t i n t e r r u p t r e q u e s t ( T I )
T r a n s m i t b u f f e r e m p t y f l a g ( T B E )
S e r i a l I / O 1 s t a t u s r e g i s t e r
D
D
D
4
5
6
D
D
D
4
5
6
Overrun error (OE)
detection
1 6
Address 0019
16
D
7
D
7
RBF = 1
TSC = 1
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