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7542 Group
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 0039
) is not set after reset. Writing an optional
16
value to the watchdog timer control register (address 0039
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 0039
) can be set before an underflow occurs.
16
When the watchdog timer control register (address 0039
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction function selection bit and watchdog timer H count
source selection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 0039
), the watchdog timer H is set to "FF
16
watchdog timer L is set to "FF
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 0039
"0", the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(X
When this bit is "1", the count source becomes f(X
case, the detection time is 512 µs at f(X
This bit is cleared to "0" after reset.
Source clock selection
(auto-switch depending on setting of CPUM)
XIN clock
On-chip oscillator
STP Instruction function selection bit
RESET
Fig. 68 Block diagram of watchdog timer
b7
Fig. 69 Structure of watchdog timer control register
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
" and the
16
".
16
). When this bit is
16
)=8 MHz.
IN
)/16. In this
IN
)=8 MHz.
IN
Write "FF
" to the
16
watchdog timer
control register
Watchdog timer L (8)
1/16
STP Instruction
b0
Watchdog timer control register
(WDTCON: address 0039
Watchdog timer H (read only for high-order 6-bit)
STP instruction function selection bit
0 : System enters into the stop mode
1 : Internal reset occurs at the STP instruction execution
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(X
Page 57 of 134
Operation of STP instruction function selection bit
When "0" is set to STP instruction function selection bit, system
enters into the stop mode at the STP instruction execution.
When "1" is set to this bit, internal reset occurs at the STP instruc-
tion execution.
This bit is set to "1" by program, but it cannot be changed to "0" .
This bit is cleared to "0" after reset.
Notes on Watchdog Timer
)
1. The watchdog timer is operating during the wait mode. Write data
16
to the watchdog timer control register to prevent timer underflow.
2. The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the oscillation stabilizing time
) is
after the STP instruction is released. In order to avoid the under-
16
flow of the watchdog timer, the watchdog timer control register
must be written just before executing the STP instruction.
3. The STP instruction function selection bit (bit 6 of watchdog
timer control register (address 0039
once after releasing reset. After rewriting it is disable to write
any data to this bit.
4. A count source of watchdog timer is affected by the clock divi-
sion selection bit of the CPU mode register.
The f(X
) clock is supplied to the watchdog timer when select-
IN
ing f(X
) as the CPU clock.
IN
The on-chip oscillator output is supplied to the watchdog timer
when selecting the on-chip oscillator output as the CPU clock.
"0"
"1"
Watchdog timer H count
source selection bit
, initial value: 3F
16
at the STP instruction execution
)/16 or on-chip oscillator/16
IN
)) can be rewritten only
16
Data bus
Write "FF
watchdog timer
control register
Watchdog timer H (8)
Reset
Internal
circuit
reset
)
16
" to the
16
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