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Renesas V850E/D 3 Series User Manual

32-bit single-chip microcontroller

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Hardware

V850E/Dx3 - DJ3/DL3

32

32-bit Single-Chip Microcontroller

μPD70F3421

μPD70F3422

μPD70F3423

μPD70F3424

μPD70F3425

μPD70F3426A

μPD70F3427

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

R01UH0129ED0701, Rev. 7.01

Jun 27, 2012

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Summary of Contents for Renesas V850E/D 3 Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
Page 3 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.
Page 4 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 5 Block diagrams do not necessarily show the exact wiring in hardware but the functional structure. Timing diagrams are for functional explanation purposes only, without any relevance to the real hardware implementation. Further Information For further information see http://www.renesas.eu/. R01UH0129ED0701 Rev. 7.01 User Manual...
Page 6: Table Of Contents
Table of Contents Chapter 1 Introduction ..........18 General .
Page 7 Table of Contents Chapter 3 CPU System Functions ....... 106 Overview.
Page 8 Table of Contents 5.2.3 Non-maskable interrupt status flag (NP) ......207 5.2.4 NMI0 control ..........207 Maskable Interrupts.
Page 9 Table of Contents 7.2.7 Initialization for access to external devices ......268 7.2.8 External bus mute function ........268 Registers .
Page 10 Table of Contents Chapter 9 ROM Correction Function (ROMC) ....344 Overview............344 “Data Replacement”...
Page 11 Table of Contents 13.1 Features of Timer G..........458 13.2 Function Overview of Each Timer Gn .
Page 12 Table of Contents 17.5.6 Continuous transmission procedure ......554 17.5.7 UART reception..........556 17.5.8 Reception errors .
Page 13 Table of Contents 19.8 C Bus Definitions and Control Methods ....... 629 19.8.1 Start condition .
Page 14 Table of Contents 20.5.1 CAN module register and message buffer addresses ....705 20.5.2 CAN Controller configuration ........706 20.5.3 CAN registers overview.
Page 15 Table of Contents 21.4.4 Power-fail compare mode ........834 21.5 Cautions .
Page 16 Table of Contents 25.4 Sound Generator Application Hints........907 25.4.1 Initialization .
Page 17 Table of Contents Timer Z ............946 Timer Y .
Page 18: Chapter 1 Introduction
Chapter 1 Introduction V850E/Dx3 series The V850E/Dx3 is a product series in Renesas Electronics’ V850 family of single-chip microcontrollers designed for automotive applications. Beside the V850E/Dx3 - DJ3/DL3 the product series comprises the V850E/DG3 devices. For further information about V850E/DG3 refer to the user’s manual “V850E/Dx3 - DG3”...
Page 19: Features Summary
Chapter 1 Introduction On-chip flash memory The V850E/Dx3 - DJ3/DL3 microcontrollers have on-chip flash memory. It is possible to program the controllers directly in the target environment where they are mounted. With this feature, system development time can be reduced and system maintainability after shipping can be markedly improved.
Page 20 Chapter 1 Introduction Table 1-1 V850E/Dx3 - DJ3/DL3 features summary (2/4) Internal data RAM Size • 84 KB (µPD70F3426A) • 60 KB (µPD70F3427) • 32 KB (µPD70F3425) • 24 KB (µPD70F3424) • 20 KB (µPD70F3423) • 20 KB (µPD70F3422) • 12 KB (µPD70F3421) Clock Generator Internal spread-spectrum PLL (SSCG) 12-fold/16-fold, up to 64 MHz ±...
Page 21 Chapter 1 Introduction Table 1-1 V850E/Dx3 - DJ3/DL3 features summary (3/4) Serial interfaces Synchronous: CSI (CSIB) • 3 channels (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427) • 2 channels (µPD70F3421, µPD70F3422, µPD70F3423) Asynchronous: UART (UARTA) 2 channels with LIN support C (IIC) 2 channels CAN (CAN) •...
Page 22 Chapter 1 Introduction Table 1-1 V850E/Dx3 - DJ3/DL3 features summary (4/4) Interrupts and exceptions Non-maskable interrupts 2 sources Maskable interrupts • 92 sources (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427) • 84 sources (µPD70F3421, µPD70F3422, µPD70F3423) Software exceptions 32 sources Exception trap 2 sources ROM Correction Number of channels 8 channels by DBTRAP...
Page 23: Product Series Overview
Chapter 1 Introduction 1.3 Product Series Overview Table 1-2 shows the common and different features of the microcontrollers. Table 1-2 V850E/Dx3 - DJ3/DL3 product series overview V850E/DL3 V850E/DJ3 Part number µPD70F3427 µPD70F3426A µPD70F3425 µPD70F3424 µPD70F3423 µPD70F3422 µPD70F3421 Internal Flash 1 MB + 1 MB 1 MB 512 KB...
Page 24: Description
Chapter 1 Introduction 1.4 Description Figure 1-1 provides a functional block diagram of the V850E/DJ3 (µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A) microcontrollers. Power and Reset 2 x Voltage VCMP0, VCMP1 Reset Power supply Comparator VCMPO0, VCMPO1 Memory Note 7 Note 1 Flash Interrupt INTP0 to INTP6...
Page 25 Chapter 1 Introduction Table 1-3 summarizes the different features of the of the V850E/DJ3 (µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A) microcontrollers, marked as “Notes” in Figure 1-1. Table 1-3 Feature set differences µPD70F3426 Note Feature µPD70F3425 µPD70F3424 µPD70F3423 µPD70F3422 µPD70F3421 √...
Page 26 Chapter 1 Introduction Power and Reset 2 x Voltage VCMP0, VCMP1 Reset Power supply Comparator VCMPO0, VCMPO1 Memory Flash Interrupt Correction Controller CPU Core INTP0 to INTP7 A0 to A23 Serial Interfaces System Controller D0 to D15 RXDA0, RXDA1 D16 to D31 2 x UARTA CS0, CS1 TXDA0, TXDA1...
Page 27 Chapter 1 Introduction Structure of the This manual explains how to use the V850E/Dx3 - DJ3/DL3 microcontroller manual devices. It provides comprehensive information about the building blocks, their features, and how to set registers in order to enable or disable specific functions.
Page 28: Ordering Information
Chapter 1 Introduction 1.5 Ordering Information Table 1-4 V850E/Dx3 ordering information Product order code Pin/package Memory size Remarks UPD70F3421GJ(A)-GAE-QS-AX 144 pin LQFP 256 KB flash – UPD70F3422GJ(A)-GAE-QS-AX 144 pin LQFP 384 KB flash – UPD70F3423GJ(A)-GAE-QS-AX 144 pin LQFP 512 KB flash –...
Page 29: Chapter 2 Pin Functions
Chapter 2 Pin Functions This chapter lists the ports of the microcontroller. It presents the configuration of the ports for alternative functions. Noise elimination on input signals is explained and a recommendation for the connection of unused pins is given at the end of the chapter.
Page 30: Description
Chapter 2 Pin Functions 2.1.1 Description This microcontroller has the port groups shown below. Port group 0 Port group 7 P715 Port group 1 Port group 8 Port group 2 Port group 9 P100 Port group 3 Port group 10 P107 P110 Port group 4...
Page 31 Chapter 2 Pin Functions Port group overview Table 2-1 gives an overview of the port groups. For each port group it shows the supported functions in port mode and in alternative mode. Any port group can operate in 8-bit or 1-bit units. Port group 7 can additionally operate in 16-bit units.
Page 32 Chapter 2 Pin Functions Table 2-1 Functions of each port group (2/2) Port Function group Port mode Alternative mode name 8-bit input/output • Clocked Serial Interface CSIB2 data/clock line (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 only) • LCD controller segment signal output (µPD70F3421, µPD70F3422, µPD70F3423 only) •...
Page 33 Chapter 2 Pin Functions Pin configuration To define the function and the electrical characteristics of a pin, several control registers are provided. • For a general description of the registers, see “Port Group Configuration Registers“ on page 35. • For every port, detailed information on the configuration registers is given in “Port Group Configuration“...
Page 34: Terms
Chapter 2 Pin Functions 2.1.2 Terms In this section, the following terms are used: • Pin Denotes the physical pin. Every pin is uniquely denoted by its pin number. A pin can be used in several modes. Depending on the selected mode, a pin name is allocated to the pin.
Page 35: Port Group Configuration Registers
Chapter 2 Pin Functions 2.2 Port Group Configuration Registers This section starts with an overview of all configuration registers and then presents all registers in detail. The configuration registers are classified in the following groups: • “Pin function configuration“ on page 36 •...
Page 36: Pin Function Configuration
Chapter 2 Pin Functions 2.2.2 Pin function configuration The registers for pin function configuration define the general function of a pin: • input mode or output mode • port mode or alternative mode • selection of one of the alternative output functions ALT1-OUT/ALT2-OUT •...
Page 37 Chapter 2 Pin Functions PMn - Port mode register The 8-bit PMn register specifies whether the individual pins of the port group n are in input mode or in output mode. Access This register can be read/written in 8-bit and 1-bit units. Address see “Port Group Configuration“...
Page 38 Chapter 2 Pin Functions PMCn - Port mode control register The PMCn register specifies whether the individual pins of port group n are in port mode or in alternative mode. For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 39 Chapter 2 Pin Functions PLCDCn - Port LCD control register Some port groups comprise pins for signal output of the LCD Controller Driver. For those port groups, the 8-bit PLCDCn register specifies whether an individual pin of port group n serves as an output pin of the LCD Controller/ Driver or not.
Page 40 Chapter 2 Pin Functions OCDM - On-chip debug mode register The 8-bit OCDM register specifies whether dedicated pins of the microcontroller operate in normal operation mode or can be used for on-chip debugging (N-Wire interface). The setting of this register concerns only those pins that can be used for the N-Wire interface: P05/DRST, P52/DDI, P53/DDO, P54/DCK, and P55/DMS.
Page 41: Pin Data Input/Output
Chapter 2 Pin Functions 2.2.3 Pin data input/output If a pin is in port mode, the registers for pin data input/output specify the input and output data. Pn - Port register In port mode (PMCn.PMCnm=0), data is input from or output to an external device by writing or reading the Pn register.
Page 42 Chapter 2 Pin Functions PRCn - Port read control register In input mode (PMn.PMnm = 1), the 8-bit PRCn register specifies whether the pin status or the contents of register Pn are read (see also Table 2-10). Each PRCn register contains only one control bit which defines the read source of all ports of the entire port group n.
Page 43: Configuration Of Electrical Characteristics
Chapter 2 Pin Functions 2.2.4 Configuration of electrical characteristics The registers for the configuration of electrical characteristics are briefly described in the following. For details refer to the Data Sheet. PDSCn - Port drive strength control register The 8-bit PDSCn register selects the output current limiting function for high- or low-drive strength.
Page 44 Chapter 2 Pin Functions PILCn - Port input level control register The PILCn register selects between different input characteristics for Schmitt Trigger (PICCn.PICCnm = 1) and non-Schmitt Trigger (PICCn.PICCnm = 0). For port groups with up to eight ports, this is an 8-bit register. For port groups with up to 16 ports, this is a 16-bit register.
Page 45 Chapter 2 Pin Functions PODCn - Port open drain control register The PODCn register selects the output buffer function as push-pull or open- drain emulation. Access This register can be read/written in 8-bit and 1-bit units. Address see “Port Group Configuration“ on page 56 Initial Value .
Page 46: Alternative Input Selection
Chapter 2 Pin Functions 2.2.5 Alternative input selection Alternative input functions of CSIB0…CSIB2, UART0…UART1, I C0, I INTP6, INTP7, TMP0…TMP3 and TMG0…TMG2 are provided on two pins each. Thus you can select on which pin the alternative function should appear. For this purpose, four peripheral function select registers PFSRk (k = 0 to 3) are provided.
Page 47 Chapter 2 Pin Functions PFSR0 - Peripheral function select register The 8-bit PFSR0 register selects the alternative input paths for the peripheral functions CSIB0…2, I C0, I C1, INTP6 and INTP7. Access This register can be read/written in 8-bit units. Address FFFF F720 Initial Value...
Page 48 Chapter 2 Pin Functions PFSR1 - Peripheral function select register The 8-bit PFSR1 register selects the alternative input paths for the peripheral functions TMP0…3. Access This register can be read/written in 8-bit units. Address FFFF F722 Initial Value . This register is initialized by any reset. PFSR17 PFSR16 PFSR15 PFSR14 PFSR13 PFSR12 PFSR11 PFSR10 Table 2-18 PFSR1 register contents...
Page 49 Chapter 2 Pin Functions PFSR2 - Peripheral function select register The 8-bit PFSR2 register selects the alternative input paths for the peripheral functions TMG0 and TMG1. Access This register can be read/written in 8-bit units. Address FFFF F724 Initial Value .
Page 50 Chapter 2 Pin Functions PFSR3 - Peripheral function select register The 8-bit PFSR3 register selects the alternative input paths for the peripheral functions TMG2, UARTA0 and UARTA1. Access This register can be read/written in 8-bit units. Address FFFF F726 Initial Value .
Page 51: Port Types Diagrams
Chapter 2 Pin Functions 2.3 Port Types Diagrams The control circuits that evaluate the settings of the configuration registers are of different types. This chapter presents the block diagrams of all port types. Port type M Note 4 PDSCnm Note 5 PICCnm Note 6 PILCnm...
Page 52 Chapter 2 Pin Functions Figure 2-2 Block diagram: port type M Note The analog filter is provided only for alternative external interrupt ports P00–04, P06, P07, P40. The µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 provides analog filters additionally at P50 and P84. Bit PLCDCn.PLCDCnm is only provided with µPD70F3421, µPD70F3422 and µPD70F3423 for pins with an alternative function as LCD Controller/ Driver output ports P20–27, P32–37, P43–45, P60–67, P80–83, P85–87,...
Page 53 Chapter 2 Pin Functions Port type Q Note 1 PDSCnm Note 2 PICCnm Note 3 PILCnm PMCnm PMnm PODCnm PFCnm ENABLE ALT1-OUT ALT2-OUT ENABLE PRCn0 internal RESET LCD Bus LCD Bus I/F read I/F write Figure 2-3 Block diagram: port type Q Note The PDSC9 register is not available for µPD70F3427.
Page 54 Chapter 2 Pin Functions Port type R This port type holds for pins that can be used for on-chip debugging with the N-Wire interface. PDSCnm PICCnm PILCnm OCDM PMnm PODCnm PFCnm ENABLE PRCn0 internal RESET PFC0.PDC05 DDI, DMS, DCK, DRST Figure 2-4 Block diagram: port type R Note...
Page 55 Chapter 2 Pin Functions Port type B This port type holds for pins that only work in input mode. Pins of port type B are used for the corresponding alternative input function A/D converter input. At the same time, the pin status can also be read via the port register Pn, so that the pin also works in port function.
Page 56: Port Group Configuration
Chapter 2 Pin Functions 2.4 Port Group Configuration This section provides an overview of the port groups (Table 2-21, Table 2-22) and of the pin functions (Table 2-23 on page 64). In Table 2-61 on page 101 it is listed how the pin functions change if the microcontroller is reset or if it is in one of the standby modes.
Page 57: Port Group Configuration Lists
Chapter 2 Pin Functions 2.4.1 Port group configuration lists Following tables provide overviews of the functions available at each port pin: • Table 2-21 for µPD70F3421, µPD70F3422, µPD70F3423 • Table 2-22 for µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 Table 2-21 Port group list for µPD70F3421, µPD70F3422, µPD70F3423 (1/4) Alternative outputs Port group Alternative...
Page 58 Chapter 2 Pin Functions Table 2-21 Port group list for µPD70F3421, µPD70F3422, µPD70F3423 (2/4) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT FOUT/SGOA – – – – – – – RXDA1/CRXD1 TXDA1/CTXD1 – TOP00/SEG12 TIP00/TIG20 TOP01/TOG21/SEG13 TIP01/TIG21 TOP10/SEG14...
Page 59 Chapter 2 Pin Functions Table 2-21 Port group list for µPD70F3421, µPD70F3422, µPD70F3423 (3/4) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT DBD0/SEG36 DBD0/SIB1 DBD1/SEG37/SOB1 DBD1 DBD2/SEG38/SCKB1 DBD2/SCKB1 DBD3/SEG39 DBD3 DBD4/COM0 DBD4 DBD5/COM1 DBD5 DBD6/COM2 DBD6 DBD7/COM3 DBD7...
Page 60 Chapter 2 Pin Functions Table 2-21 Port group list for µPD70F3421, µPD70F3422, µPD70F3423 (4/4) Alternative outputs Port group Alternative Port Port name ALT1_OUT/ALT2_OUT/ name inputs type LCD_OUT P130 SM31/TOG01 TIG01 P131 SM32/TOG02 TIG02 P132 SM33/TOG03 TIG03 P133 SM34/TOG04 TIG04 P134 SM41/TOG11 TIG11 P135...
Page 61 Chapter 2 Pin Functions Table 2-22 Port group list for µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 (2/4) Port group Alternative outputs Alternative Port Port name name ALT1_OUT/ALT2_OUT inputs type – SIB0/INTP6 SOB0 – SCKB0 SCKB0 – SIB1 SOB1 – SCKB1 SCKB1 – CRXD0 CTXD0 –...
Page 62 Chapter 2 Pin Functions Table 2-22 Port group list for µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 (3/4) Port group Alternative outputs Alternative Port Port name name ALT1_OUT/ALT2_OUT inputs type – SIB2 SOB2 – SCKB2 SCKB2 TOY0/FOUT – TOY0 INTP7 FOUT – TXDA0/D16 RXDA0/D17 DBD0/D24 DBD0/SIB1/...
Page 63 Chapter 2 Pin Functions Table 2-22 Port group list for µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 (4/4) Port group Alternative outputs Alternative Port Port name name ALT1_OUT/ALT2_OUT inputs type P120 SM51 – P121 SM52 – P122 SM53 – P123 SM54 – P124 SM61 –...
Page 64: Alphabetic Pin Function List
Chapter 2 Pin Functions 2.4.2 Alphabetic pin function list Table 2-23 provides a list of all pin function names in alphabetic order. Table 2-23 Alphabetic pin functions list (1/6) Port µPD70F3421, µPD70F3424, µPD70F3426A µPD70F3427 Pin name I/O Pin function µPD70F3422, µPD70F3425 µPD70F3423 A0 to A23...
Page 65 Chapter 2 Pin Functions Table 2-23 Alphabetic pin functions list (2/6) Port µPD70F3421, µPD70F3424, µPD70F3426A µPD70F3427 Pin name I/O Pin function µPD70F3422, µPD70F3425 µPD70F3423 I/O External memory interface – data lines 16 to 31 D20 to D23 P104 to P107 D24 to D31 P90 to P97 DBD0 to...
Page 66 Chapter 2 Pin Functions Table 2-23 Alphabetic pin functions list (3/6) Port µPD70F3421, µPD70F3424, µPD70F3426A µPD70F3427 Pin name I/O Pin function µPD70F3422, µPD70F3425 µPD70F3423 External memory interface – no ports read strobe REGC0 to – External capacitor no ports REGC2 connection RESET Reset input...
Page 67 Chapter 2 Pin Functions Table 2-23 Alphabetic pin functions list (4/6) Port µPD70F3421, µPD70F3424, µPD70F3426A µPD70F3427 Pin name I/O Pin function µPD70F3422, µPD70F3425 µPD70F3423 SGOA Sound Generator P50, P115 amplitude PWM output SIB0 Clocked Serial Interface P40, P105 CSIB0 data input SIB1 Clocked Serial Interface P43, P90...
Page 68 Chapter 2 Pin Functions Table 2-23 Alphabetic pin functions list (5/6) Port µPD70F3421, µPD70F3424, µPD70F3426A µPD70F3427 Pin name I/O Pin function µPD70F3422, µPD70F3425 µPD70F3423 TIG01 to Timer TMG0 channels 1 to P20 to P23, P130 to P133 TIG04 4 input TIG11 to Timer TMG1 channels 1 to P24 to P27, P134 to P137...
Page 69 Chapter 2 Pin Functions Table 2-23 Alphabetic pin functions list (6/6) Port µPD70F3421, µPD70F3424, µPD70F3426A µPD70F3427 Pin name I/O Pin function µPD70F3422, µPD70F3425 µPD70F3423 TOP21 Timer TMP2 channel 1 P35, P66, P103 output TOP30 Timer TMP3 channel 0 P65, P103 output TOP31 Timer TMP3 channel 1...
Page 70: External Memory Interface Of Μpd70F3427
Chapter 2 Pin Functions 2.4.3 External memory interface of µPD70F3427 The µPD70F3427 is equipped with an external memory interface. The data bus width can be chosen between 16-bit D[15:0] and 32-bit D[31:0]. The signals of the external memory interface are partly shared with ports respectively alternative functions and are controlled by different means, as listed in Table 2-24.
Page 71: Port Group 0
Chapter 2 Pin Functions 2.4.4 Port group 0 • Port group 0 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP0 to INTP6) • Non-maskable interrupt (NMI) • N-Wire debug interface reset (DRST) •...
Page 72 Chapter 2 Pin Functions Table 2-26 Port group 0: configuration registers Initial Register Address Used bits value FFFF F420 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 PMC0 FFFF F440 PMC07 PMC06 PMC04 PMC03 PMC02 PMC01 PMC00 PFC0 FFFF F460 PFC07 PDC05 OCDM...
Page 73: Port Group 1
Chapter 2 Pin Functions 2.4.5 Port group 1 Port group 1 is a 2-bit port group. In alternative mode, it comprises pins for the following functions: • I C0 data/clock line (SDA0/SCL0) Port group 1 includes the following pins: Table 2-27 Port group 1: pin functions and port types Pin functions in different modes Port mode...
Page 74: Port Group 2
Chapter 2 Pin Functions 2.4.6 Port group 2 Port group 2 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Timer TMG0 to TMG1 channels (TIG01 to TIG04, TOG01 to TOG04, TIG11 to TIG14, TOG11 to TOG14) •...
Page 75 Chapter 2 Pin Functions Table 2-30 Port group 2: Configuration registers Initial Register Address Used bits value FFFF F424 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PMC2 FFFF F444 PMC27 PMC26 PMC25 PMC24 PMC23 PMC22 PMC21 PMC20 PFC2 FFFF F464 PFC21 PFC20 PLCDC2...
Page 76: Port Group 3
Chapter 2 Pin Functions 2.4.7 Port group 3 Port group 3 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • UARTA0 transmit/receive data (TXDA0, RXDA0) • UARTA1 transmit/receive data (TXDA1, RXDA1) • I C1 data/clock line (SDA1, SCL1) •...
Page 77 Chapter 2 Pin Functions Table 2-32 Port group 3: configuration registers Initial Register Address Used bits value FFFF F426 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PMC3 FFFF F446 PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PFC3 FFFF F466 PFC37 PFC36 PFC35...
Page 78: Port Group 4
Chapter 2 Pin Functions 2.4.8 Port group 4 Port group 4 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Clocked Serial Interface CSIB0 data/clock line (SIB0, SOB0, SCKB0) • Clocked Serial Interface CSIB1 data/clock line (SIB1, SOB1, SCKB1) •...
Page 79 Chapter 2 Pin Functions Table 2-34 Port group 4: configuration registers Initial Register Address Used bits value FFFF F428 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 PMC4 FFFF F448 PMC47 PMC46 PMC45 PMC44 PMC43 PMC42 PMC41 PMC40 PLCDC4 FFFF F348 PLCDC45 PLCDC44 PLCDC43...
Page 80: Port Group 5
Chapter 2 Pin Functions 2.4.9 Port group 5 Port group 5 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • External interrupt (INTP7) (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 only) • Sound Generator outputs (SGO, SGOA) •...
Page 81 Chapter 2 Pin Functions Table 2-36 Port group 5: configuration registers Initial Register Address Used bits value FFFF F42A PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PMC5 FFFF F44A PMC57 PMC56 PMC51 PMC50 PFC5 FFFF F46A PFC57 PFC50 OCDM FFFF F9FC OCDM0 FFFF F40A...
Page 82: Port Group 6
Chapter 2 Pin Functions 2.4.10 Port group 6 Port group 6 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Timer TMP0 to TMP3 channels (TIP00 to TIP31, TOP00 to TOP31) • Timer TMG2 channels (TIG20 to TIG25, TOG21 to TOG24) •...
Page 83 Chapter 2 Pin Functions Table 2-38 Port group 6: configuration registers Initial Register Address Used bits value FFFF F42C PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PMC6 FFFF F44C PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 PFC6 FFFF F46C PFC67 PFC66 PFC65...
Page 84: Port Group 7
Chapter 2 Pin Functions 2.4.11 Port group 7 Port group 7 is a 16-bit port group. It includes pins for the A/D Converter input. The pins of this port group only work in input mode (port type B). They are used for their alternative input function A/D converter input.
Page 85 Chapter 2 Pin Functions Table 2-40 Port group 7: configuration registers Initial Register Address Used bits value PMC7L FFFF F44E PMC77 PMC76 PMC75 PMC74 PMC73 PMC72 PMC71 PMC70 PMC7H FFFF F44F PMC715 PMC714 PMC713 PMC712 PMC711 PMC710 PMC79 PMC78 PMC7 FFFF F44E 0000 PMC715 to PMC78 (PMC7H)
Page 86: Port Group 8
Chapter 2 Pin Functions 2.4.12 Port group 8 Port group 8 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Clocked Serial Interface CSIB2 data/clock line (SIB2, SOB2, SCKB2) (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 only) •...
Page 87 Chapter 2 Pin Functions Table 2-42 Port group 8: configuration registers Initial Register Address Used bits value FFFF F430 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 PMC8 FFFF F450 PMC87 PMC86 PMC85 PMC84 PMC83 PMC82 PMC81 PMC80 PFC8 FFFF F470 PFC83 PLCDC8 FFFF F350...
Page 88: Port Group 9
Chapter 2 Pin Functions 2.4.13 Port group 9 Port group 9 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • LCD Bus Interface data lines (DBD0 to DBD7) (µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 only) •...
Page 89 Chapter 2 Pin Functions Table 2-44 Port group 9: configuration registers Initial Register Address Used bits value FFFF F432 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PMC9 FFFF F452 PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PFC9 FFFF F472 PFC96 PFC95 PFC92...
Page 90: Port Group 10
Chapter 2 Pin Functions 2.4.14 Port group 10 Port group 10 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Timer TMP0 to TMP3 (TOP00 to TOP31, TIP00 to TIP31) • LCD Bus Interface read/write strobe (DBRD, DBWR) •...
Page 91 Chapter 2 Pin Functions Table 2-46 Port group 10: configuration registers Initial Register Address Used bits value PM10 FFFF F434 PM107 PM106 PM105 PM104 PM103 PM102 PM101 PM100 PMC10 FFFF F454 PMC107 PMC106 PMC105 PMC104 PMC103 PMC102 PMC101 PMC100 PFC10 FFFF F474 PFC103 PFC102...
Page 92: Port Group 11
Chapter 2 Pin Functions 2.4.15 Port group 11 Port group 11 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Stepper Motor Controller/Driver outputs (SM11 to SM14, SM21 to SM24) • Timer TMG2 channels (TOG21 to TOG24) •...
Page 93 Chapter 2 Pin Functions Table 2-48 Port group 11: configuration registers Initial Register Address Used bits value PM11 FFFF F436 PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110 PMC11 FFFF F456 PMC117 PMC116 PMC115 PMC114 PMC113 PMC112 PMC111 PMC110 PFC11 FFFF F476 PFC115 PFC114...
Page 94: Port Group 12
Chapter 2 Pin Functions 2.4.16 Port group 12 Port group 12 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Stepper Motor Controller/Driver outputs (SM51 to SM54, SM61 to SM64) Port group 12 includes the following pins: Table 2-49 Port group 12: pin functions and port types Pin functions in different modes...
Page 95: Port Group 13
Chapter 2 Pin Functions 2.4.17 Port group 13 Port group 13 is an 8-bit port group. In alternative mode, it comprises pins for the following functions: • Stepper Motor Controller/Driver outputs (SM31 to SM34, SM41 to SM44) • Timer TMG0 to TMG1 channels (TIG01 to TIG04, TOG01 to TOG04, TIG11 to TIG14, TOG11 to TOG14) Port group 13 includes the following pins: Table 2-51...
Page 96: Port Group 14 (Μpd70F3427 Only)
Chapter 2 Pin Functions 2.4.18 Port group 14 (µPD70F3427 only) Port group 14 is a 3-bit port group. In alternative mode, it comprises pins for the following functions: • External memory interface bus clock BCLK • External memory interface byte enable signals BE2, BE3 Port group 14 includes the following pins: Table 2-53 Port group 14: pin functions and port types...
Page 97: Noise Elimination
Chapter 2 Pin Functions 2.5 Noise Elimination The input signals at some pins are passed through a filter to remove noise and glitches. The microcontroller supports both analog and digital filters. The analog filters are always applied to the input signals, whereas the digital filters can be enabled/disabled by control registers.
Page 98 Chapter 2 Pin Functions Filter operation The input terminal signal is sampled with the sampling frequency f . Spikes shorter than 2 sampling cycles are suppressed and no internal signal is generated. Pulses longer than 3 sampling cycles are recognized as valid pulses and an internal signal is generated.
Page 99 Chapter 2 Pin Functions DFEN0 - Digital filter enable register The 16-bit DFEN0 register enables/disables the digital filter for TMP0 to TMP3 and TMG0 input channels and for CSIB0 to CSIB2 input channels. Access This register can be read/written in 16-bit, 8-bit and 1-bit units. Address FFFF F710 Initial Value...
Page 100 Chapter 2 Pin Functions DFEN1 - Digital filter enable register The 16-bit DFEN1 register enables/disables the digital filter for TMG0 to TMG2 and TMP0 to TMP1 input channels. Access This register can be read/written in 16-bit, 8-bit and 1-bit units. Address FFFF F712 Initial Value...
Page 101: Pin Functions In Reset And Power Save Modes
Chapter 2 Pin Functions 2.6 Pin Functions in Reset and Power Save Modes The following table summarizes the status of the pins during reset and power save modes and after release of these operating states in normal operation mode, i.e. = 0. The reset source makes a difference concerning the N-Wire debugger interface pins DRST, DDI, DDO, DCK and DMS after reset release.
Page 102: Recommended Connection Of Unused Pins
Chapter 2 Pin Functions 2.7 Recommended Connection of unused Pins If a pin is not used, it is recommended to connect it as follows: • output pins: leave open • input pins: connect to V or V Sub oscillator If no sub oscillator crystal is connected , connect XT1 to V and leave XT2 connection open.
Page 103: Package Pins Assignment
Chapter 2 Pin Functions 2.8 Package Pins Assignment The following sections show the location of pins in top view. Every pin is labelled with its pin number and all possible pin names. 2.8.1 µPD70F3421, µPD70F3422, µPD70F3423 P92/SCKB1/DBD2/SEG38 P23/TIG04/TOG04/SEG3 P93/DBD3/SEG39 P22/TIG03/TOG03/SEG2 P94/DBD4/COM0 P21/TIG02/TOG02/SCL1/SEG1 P95/DBD5/COM1...
Page 104: Μpd70F3424, Μpd70F3425, Μpd70F3426A
Chapter 2 Pin Functions 2.8.2 µPD70F3424, µPD70F3425, µPD70F3426A P92/SCKB1/DBD2 P23/TIG04/TOG04 P93/DBD3 P22/TIG03/TOG03 P94/SIB2/DBD4 P21/TIG02/TOG02/SCL1 P95/SOB2/DBD5 P20/TIG01/TOG01/SDA1 Note P96/SCK2/DBD6 P17/SCL0/CRXD2 Note P97/DBD7 P16/SDA0/CTXD2 DVDD50 VSS51 DVSS50 REGC1 VDD52 VDD51 REGC2 P30/TXDA0/SDA1 VSS52 P31/RXDA0/SCL1 FLMD0 P47/CTXD0 P46/CRXD0 V850E / DJ3 P57/TXDA1/CTXD1 RESET P56/RXDA1/CRXD1 P42/SCKB0 µPD70F3424...
Page 105: Μpd70F3427
Chapter 2 Pin Functions 2.8.3 µPD70F3427 P26/TIG13/TOG13 P27/TIG14/TOG14 P34/TIG21/TOG21/TOP01 MVSS53 P35/TIG22/TOG22/TOP21 MVDD53 P36/TIG23/TOG23/TOP31 VSS51 P37/TIG24/TOG24/TOP11 REGC1 P60/TIG20/TIP00/TOP00 VDD51 P61/TIG21/TIP01/TOG21/TOP01 BVDD51 BVSS51 P62/TIG25/TIP10/TOP10 P63/TIG24/TIP11/TOG24/TOP11 P64/TIP20/TOP20/SCL0 P65/TIP30/TOP30/SDA0 P66/TIG22/TIP21/TOG22/TOP21 P67/TIG23/TIP31/TOG23/TOP31 P45/SCKB1 P44/SOB1 MVSS52 P43/SIB1 MVDD52 P83/TOY0/FOUT P82/SCKB2 P81/SOB2 P80/SIB2 P85/FOUT V850E/DL3 VDD52 REGC2 VSS52 µPD70F3427 FLMD0...
Page 106: Chapter 3 Cpu System Functions
Chapter 3 CPU System Functions This chapter describes the registers of the CPU, the operation modes, the address space and the memory areas. 3.1 Overview The CPU is founded on Harvard architecture and it supports a RISC instruction set. Basic instructions can be executed in one clock period. Optimized five- stage pipelining is supported.
Page 107: Description
Chapter 3 CPU System Functions 3.1.1 Description The figure below shows a block diagram of the microcontroller, focusing on the CPU and modules that interact with the CPU directly. Table 3-1 lists the bus types. RCU interface System controller Instruction queue Multiplier (32 ×...
Page 108: Cpu Register Set
Chapter 3 CPU System Functions 3.2 CPU Register Set There are two categories of registers: • General purpose registers • System registers All registers are 32-bit registers. An overview is given in the figure below. For details, refer to V850E1 User’s Manual Architecture. (Zero Register) EIPC (Status Saving Register during interrupt)
Page 109: General Purpose Registers (R0 To R31)
Chapter 3 CPU System Functions 3.2.1 General purpose registers (r0 to r31) Each of the 32 general purpose registers can be used as a data variable or address variable. However, the registers r0, r1, r3 to r5, r30, and r31 may implicitly be used by the assembler/compiler (see table Table 3-2).
Page 110: System Register Set
Chapter 3 CPU System Functions 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Additionally, the program counter holds the instruction address during program execution. To read/write the system registers, use instructions LDSR (load to system register) or STSR (store contents of system register), respectively, with a specific system register number (regID) indicated below.
Page 111 Chapter 3 CPU System Functions PC - Program counter The program counter holds the instruction address during program execution. The lower 26 bits are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to 26, it is ignored. Branching to an odd address cannot be performed.
Page 112 Chapter 3 CPU System Functions PSW - Program status word The 32-bit program status word is a collection of flags that indicates the status of the program (result of instruction execution) and the status of the CPU. If the bits in the register are modified by the LDSR instruction, the PSW will take on the new value immediately after the LDSR instruction has been executed.
Page 113 Chapter 3 CPU System Functions In the case of saturate instructions, the SAT, S, and OV flags will be set according to the result of the operation as shown in the table below. Note that the SAT flag is set only when the OV flag has been set during a satu- rated operation.
Page 114 Chapter 3 CPU System Functions Caution Bits 31 to 26 of EIPC and bits 31 to 12 and 10 to 8 of EIPSW are reserved for future function expansion (fixed to 0).When setting the value of EIPC, FEPC, or CTPC, use even values (bit 0 = 0). If bit 0 is set to 1, the setting of this bit is ignored.
Page 115 Chapter 3 CPU System Functions Table 3-9 Interrupt/execution codes (2/2) Interrupt/Exception Source Value Exception Handler Classification restored to Code Address Name Trigger EIPC/FEPC Exception trap (ILGOP) Illegal Exception 0060 0000 0060 next PC instruction code Debug trap DBTRAP Exception 0060 0000 0060 next PC instruction...
Page 116: Operation Modes
Chapter 3 CPU System Functions 3.3 Operation Modes This section describes the operation modes of the CPU and how the modes are specified. The following operation modes are available: • Normal operation mode • Flash programming mode After reset release, the microcontroller starts to fetch instructions from an internal boot ROM which contains the internal firmware.
Page 117: Address Space
Chapter 3 CPU System Functions 3.4 Address Space In the following sections, the address space of the CPU is explained. Size and addresses of CPU address space and physical address space are explained. The address range of data space and program space together with their wrap- around properties are presented.
Page 118 Chapter 3 CPU System Functions CPU address space FFFF FFFFH Image FC00 0000H FBFF FFFFH Image Physical address space x3FF FFFFH F800 0000H Peripheral I/O x3FF F000H F7FF FFFFH VDB RAM x3FF 0000H Image VSB area 0800 0000H (Flash, RAM 07FF FFFFH external memory) Image...
Page 119: Program And Data Space
Chapter 3 CPU System Functions 3.4.2 Program and data space The CPU allows the following assignment of data and instructions to the CPU address space: • 4 GB as data space The entire CPU address space can be used for operand addresses. •...
Page 120 Chapter 3 CPU System Functions Wrap-around of data space If an operand address calculation exceeds 32 bits, only the lower 32 bits of the result are considered. Therefore, the addresses 0000 0000 and FFFF FFFF are contiguous addresses. This results in a wrap-around of the data space: Data space FFFF FFFEH FFFF FFFFH...
Page 121: Memory
Chapter 3 CPU System Functions 3.5 Memory In the following sections, the memory of the CPU is introduced. Specific memory areas are described and a recommendation for the usage of the address space is given. 3.5.1 Memory areas The internal memory of the CPU provides several areas: •...
Page 122 Chapter 3 CPU System Functions Table 3-12 Internal VDB RAM areas Block Device RAM size Number Size Address µPD70F3421 12 KB 4 KB 03FF 0000 – 03FF 0FFF 8 KB 03FF 1000 – 03FF 2FFF µPD70F3422 20 KB 8 KB 03FF 0000 –...
Page 123 Chapter 3 CPU System Functions External memory area (µPD70F3427 only) All address areas that do not address any internal memory or peripheral I/O registers can be used as external memory area. Access to the external memory area uses the chip select (CS) signals assigned to each memory area.
Page 124: Fixed Peripheral I/O Area
Chapter 3 CPU System Functions 3.5.2 Fixed peripheral I/O area The 4 KB area between addresses 03FF F000 and 03FF FFFF is provided as the fixed peripheral I/O area. Accesses to these addresses are passed over to the NPB bus (internal bus). The following registers are memory-mapped to the peripheral I/O area: •...
Page 125: Recommended Use Of Data Address Space
Chapter 3 CPU System Functions 3.5.3 Recommended use of data address space When accessing operand data in the data space, one register has to be used for address generation. This register is called pointer register. With relative addressing, an instruction can access operand data at all addresses that lie in the range of ±32 KB relative to the address in the pointer register.
Page 126: Write Protected Registers
Chapter 3 CPU System Functions 3.6 Write Protected Registers Write protected registers are protected from inadvertent write access due to erroneous program execution, etc. Write access to a write protected register is only given immediately after writing to a corresponding write enable register. For a write access to the write protected registers you have to use the following instructions: 1.
Page 127 Chapter 3 CPU System Functions Example Start the Watchdog Timer The following example shows how to write to the write protected register WDTM. The example starts the Watchdog Timer. do { _WPRERR = 0; DI(); WCMD = 0x5A; WDTM = 0x80; EI();...
Page 128: Instructions And Data Access Times
Chapter 3 CPU System Functions 3.7 Instructions and Data Access Times The below Table 3-16 and Table 3-17 list the instruction execution and data access cycles, required when accessing instructions or data in VFB flash, VDB RAM and VSB flash/RAM. The access time depends on the •...
Page 129 Chapter 3 CPU System Functions means 3 additional cycles are necessary for each unsuccessful VSB flash instruction fetch. Table 3-16 Single-cycle instructions execution times in CPU clock cycles μPD70F3421 μPD70F3424 μPD70F3427 μPD70F3426A μPD70F3422 Memory Access type μPD70F3425 μPD70F3423 VFB flash Consecutive Random VDB RAM...
Page 130: Chapter 4 Clock Generator
Chapter 4 Clock Generator Chapter 4 Clock Generator The clock generator provides the clock signals needed by the CPU and the on-chip peripherals. 4.1 Overview The clock generator can generate the required clock signals from the following sources: • Main oscillator - a built-in oscillator with external crystal and a nominal frequency of 4 MHz •...
Page 131: Description
Chapter 4 Clock Generator 4.1.1 Description The clock generator is built up as illustrated in the following figure. CKC.SCEN PCC.CKS[1:0] CKC.PLLEN PCC.CLS PLLCLK PCC.MFRC CPU System Standby VBCLK MainOSC MOCLK 4 MHz SSCCLK SSCG Standby PCLK0 AFCAN Int.OSC ROCLK n=1,2,3,4,6,8 PCLK1 UARTA CKC.DEN...
Page 132 Chapter 4 Clock Generator CPU clocks The CPU can be clocked directly by any of the oscillators, or by the output of one of the PLLs. The following table gives an overview of the available CPU clocks. Table 4-1 Clock sources and frequencies for the CPU Clock source Frequency Device Description...
Page 133: Clock Monitors
Chapter 4 Clock Generator IICLK clock The clock IICLK for the I C interface has it’s own programmable frequency divider. The clock source can be chosen from the PLL, SSCG or main oscillator. Special clocks The figure shows also some special clock signals. These are dedicated clocks for the LCD controller/driver, Watch Timer, Watchdog Timer, and Watch Calibration Timer.
Page 134: Power Save Modes Overview
Chapter 4 Clock Generator 4.1.3 Power save modes overview The microcontroller provides the following stand-by modes: HALT, IDLE, WATCH, Sub-WATCH, and STOP. Application systems which are designed in a way that they switch between these modes according to operation purposes, reduce power consumption efficiently.
Page 135: Start Conditions
Chapter 4 Clock Generator 4.1.4 Start conditions After any reset release, the internal oscillator is always selected as the clock source. The oscillation stabilization time for the internal oscillator is ensured by hardware. The CPU clock VBCLK is derived from the internal oscillator. Several clocks are operating based on the internal oscillator clock after reset.
Page 136: Start-Up Guideline
Chapter 4 Clock Generator 4.1.5 Start-up guideline After reset release, the internal firmware starts the main oscillator, but hands over control to the user’s software without ensuring that the main oscillator has stabilized. After that, the user’s software will typically: 1.
Page 137: Clock Generator Registers
Chapter 4 Clock Generator 4.2 Clock Generator Registers The Clock Generator is controlled and operated by means of the following registers (the list is sorted according to memory allocation): Table 4-3 Clock Generator register overview Write-protected Register name Shortcut Address by register PSC write protection register PRCMD...
Page 138 Chapter 4 Clock Generator The subsequent register descriptions are grouped as follows: • General Clock Generator Registers: – “CKC - Clock Generator control register“ on page 139 – “CGSTAT - Clock Generator status register“ on page 140 – “PHCMD - Command protection register“ on page 141 –...
Page 139: General Clock Generator Registers
Chapter 4 Clock Generator 4.2.1 General clock generator registers The general Clock Generator registers control and reflect the operation of the Clock Generator. CKC - Clock Generator control register The 8-bit CKC register controls the clock management. Access This register can be read/written in 8-bit units. Writing to this register is protected by a special sequence of instructions.
Page 140 Chapter 4 Clock Generator CGSTAT - Clock Generator status register The 8-bit CGSTAT register is read-only. It indicates the status of the main oscillator and the status of the clock generator after wake-up from power save mode. Access This register can be read in 8-bit units. Address FFFF F824 Initial Value...
Page 141 Chapter 4 Clock Generator PHCMD - Command protection register The 8-bit PHCMD register is write-only. It is used to protect other registers from unintended writing. Access This register must be written in 8-bit units. Address FFFF F800 Initial Value The contents of this register is undefined. PHCMD protects the registers that may have a significant influence on the application system from inadvertent write access, so that the system does not stop in case of a program hang-up.
Page 142 Chapter 4 Clock Generator PHS - Peripheral status register The 8-bit PHS register indicates the status of a write attempt to a register protected by PHCMD (see also “PHCMD - Command protection register“ on page 141). Access This register can be read/written in 8-bit units. Address FFFF F802 Initial Value...
Page 143 Chapter 4 Clock Generator PCC - Processor clock control register The 8-bit PCC register controls the CPU clock. This register can be changed only once after reset or power save mode release. Access This register can be read/written in 8-bit units. Writing to this register is protected by a special sequence of instructions.
Page 144 Chapter 4 Clock Generator Table 4-7 PCC register contents (2/2) Bit position Bit name Function 1 to 0 CKS[1:0] Processor clock connection: CKS1 CKS0 Selected clock connection Main oscillator SSCG PLL (main oscillator frequency x4) PLL (main oscillator frequency x8) As long as PCC.CLS = 1 these bits are ignored.
Page 145 Chapter 4 Clock Generator SDC - Set default clock register The 8-bit SDC register can be used to reset the Clock Generator to default state. This is the state that is set after power save mode release. Depending on the flags PSM.OSCDIS and PCC.SOSCP, the main, sub, or internal oscillator becomes the CPU clock source.
Page 146: Sscg Control Registers
Chapter 4 Clock Generator 4.2.2 SSCG control registers This section describes the registers used for controlling the spread spectrum Clock Generator SSCG. For modulating the SSCG output clock it’s dithering mode must be enabled by CKC.DEN = 1. Reconfiguration of The SSCG control registers SCFC0, SCFC1 and SCFMC can only be rewritten SSCG registers with new settings if the SSCG is switched off, i.e.
Page 147 Chapter 4 Clock Generator SCFC0 - SSCG frequency control register 0 The 8-bit SCFC0 register controls the frequency modulation of the SSCG. It determines the SSCG output frequency and is used in conjunction with register SCFC1. = (4 MHz × N/M) / 2. This The center SSCG output frequency is f SSCGc register defines the divisor “m”...
Page 148 Chapter 4 Clock Generator SCFC1 - SSCG frequency control register 1 The 8-bit SCFC1 register controls the frequency multiplication of the SSCG. It determines the SSCG output frequency and is used in conjunction with register SCFC0. = (4 MHz × N/M) / 2. This The center SSCG output frequency is f SSCGc register defines the factor “n”...
Page 149 Chapter 4 Clock Generator SCFMC - SSCG frequency modulation control register The 8-bit SCFMC register controls the frequency modulation of the SSCG in dithering mode (when CKC.DEN = 1). Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F82A Initial Value...
Page 150 Chapter 4 Clock Generator Example • SCFC0 = 2B , SCFC1 = DF : center frequency f = 48 MHz SSCGc • [SCFMC[4:2]] = 101 : FM range = 5 % • [SCFMC[1:0]] = 01 : modulation frequency = 50 KHz Then: •...
Page 151 Chapter 4 Clock Generator SCPS - SSCG post scaler control register The 8-bit SCPS register controls the two independent SSCG post scalers (frequency dividers) for the CPU system clock VBCLKand for the modulated peripheral clocks SPCLK. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F830 Initial Value...
Page 152: Control Registers For Peripheral Clocks
Chapter 4 Clock Generator 4.2.3 Control registers for peripheral clocks This section describes the registers used for specifying the sources and operation modes for the clocks provided for the on-chip peripherals. These clocks are the clocks for the Watchdog and Watch Timers, the SPCLKn clocks, FOUTCLK, and IICLK.
Page 153 Chapter 4 Clock Generator Table 4-14 WCC register contents (2/2) Bit position Bit name Function 2, 0 SOSCW, Watchdog Timer clock source selection: WDTSEL0 SOSCW WDTSEL0 WDT clock source Internal oscillator Sub oscillator Main oscillator Setting prohibited By default, the sub oscillator is disabled in STOP mode (see bit SOSTP). If SOSTP is 1, choose main or internal oscillator before entering STOP mode.
Page 154 Chapter 4 Clock Generator TCC - Watch Timer clock control register The 8-bit TCC register determines the Watch Timer and LCD controller clock source and the setting of the associated clock dividers. This register can be changed only once after Power-On-Clear reset or external RESET. Access This register can be read/written in 8-bit units.
Page 155 Chapter 4 Clock Generator Note Only POC and external RESET can clear the TCC register. Only one write access to TCC is allowed after reset release. Once the TCC has been written, it ignores new write accesses until the next POC or external RESET is issued. Write protection Write protection of this register is achieved in two ways: •...
Page 156 Chapter 4 Clock Generator SCC - SPCLK control register The 8-bit SCC register selects the SPCLK sources. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PHCMD - Command protection register“...
Page 157 Chapter 4 Clock Generator FCC - FOUTCLK control register The 8-bit FCC register configures the output clock FOUTCLK that can be used for external devices. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PHCMD - Command protection register“...
Page 158 Chapter 4 Clock Generator Note FOUTCLK is not influenced by stand-by modes of the microcontroller. It runs as long as it is enabled and the selected clock source operates. Application software must stop FOUTCLK by clearing the FOEN bit to minimize power consumption in stand-by modes.
Page 159 Chapter 4 Clock Generator ICC - IIC clock control register The 8-bit ICC register determines the I C clock source and the clock divider setting for IICLK. Access This register can be read/written in 8-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PHCMD - Command protection register“...
Page 160: Control Registers For Power Save Modes
Chapter 4 Clock Generator 4.2.4 Control registers for power save modes The registers described in this section control the begin and end of the power save modes IDLE, WATCH, Sub-WATCH, and STOP. Please refer to “Power save mode activation“ on page 183 for instructions and an example on how to enter a power save mode.
Page 161 Chapter 4 Clock Generator Table 4-19 PSM register contents (2/3) Bit position Bit name Function OSCDIS Main oscillator disable/enable control during and after power save mode: 0: Main oscillator enabled. 1: Main oscillator disabled. Caution: If OSCDIS is set to 1, the main oscillator clock supply for the Watch Timer and the LCD Controller/Driver are stopped immediately.
Page 162 Chapter 4 Clock Generator Table 4-19 PSM register contents (3/3) Bit position Bit name Function 1 to 0 PSM[1:0] Power save mode selection: PSM1 PSM0 Power save mode IDLE STOP WATCH Sub-WATCH mode (main oscillator shut down) It is not possible to switch to IDLE or WATCH mode when the CPU is operated by a sub clock.
Page 163 Chapter 4 Clock Generator PSC - Power save control register The 8-bit PSC register is used to enter or leave the power save mode specified in register PSM. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PRCMD - PSC write protection register“...
Page 164 Chapter 4 Clock Generator PRCMD - PSC write protection register The 8-bit PRCMD register protects the register PSC from inadvertent write access, so that the system does not stop in case of a program hang-up. After data has been written to the PRCMD register, the first write access to register PSC is valid.
Page 165 Chapter 4 Clock Generator STBCTL- Stand-by control register The 8-bit STBCTL register is used to control the stand-by function of the voltage regulators. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “STBCTLP - Stand-by control protection register“...
Page 166: Clock Monitor Registers
Chapter 4 Clock Generator 4.2.5 Clock monitor registers The following registers are used to control the monitor circuits of the main oscillator clock and the sub oscillator clock. Please refer to “Operation of the Clock Monitors“ on page 191 for supplementary information.
Page 167 Chapter 4 Clock Generator PRCMDCMM - CLMM write protection register The 8-bit PRCMDCMM register protects the register CLMM from inadvertent write access, so that the system does not stop in case of a program hang-up. After data has been written to the PRCMDCMM register, the first write access to register CLMM is valid.
Page 168 Chapter 4 Clock Generator CLMS - Sub oscillator clock monitor register The 8-bit CLMS register is used to enable the monitor for the sub oscillator clock. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “PRCMDCMS - CLMS write protection register“...
Page 169 Chapter 4 Clock Generator PRCMDCMS - CLMS write protection register The 8-bit PRCMDCMS register protects the register CLMS from inadvertent write access, so that the system does not stop in case of a program hang-up. After data has been written to the PRCMDCMS register, the first write access to register CLMS is valid.
Page 170 Chapter 4 Clock Generator CLMCS - Sub oscillator clock monitor control register The 8-bit CLMCS register is used to start the monitor of the sub oscillator clock. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F71A Initial Value .
Page 171: Power Save Modes
Chapter 4 Clock Generator 4.3 Power Save Modes This chapter describes the various power save modes and how they are operated. For details see: • “Power save modes description“ on page 171 • “Power save mode activation“ on page 183 •...
Page 172 Chapter 4 Clock Generator – Watch Timer interrupts INTWTnUV The Watch Timer clock WTCLK must be active and the Watch Timer must be enabled. – Watch Calibration Timer interrupt INTTM01 The Watch Calibration Timer clock WCTCLK must be active and the Watch Calibration Timer must be enabled.
Page 173 Chapter 4 Clock Generator HALT mode The HALT mode can be entered from normal run mode. In HALT mode, all clock settings remain unchanged. Only the CPU clock is suspended and hence program execution. Table 4-25 Clock Generator status in HALT mode Item Status Remarks...
Page 174 Chapter 4 Clock Generator IDLE mode The IDLE mode can be entered from any run mode. The main oscillator must be operating. IDLE mode can not be entered if the CPU is clocked by the sub or internal oscillator. In IDLE mode, the clock distribution is stopped (refer to the “Standby” switches in Figure 4-1, “Block diagram of the Clock Generator,”...
Page 175 Chapter 4 Clock Generator WATCH mode In WATCH mode, the clock supply for the CPU system and the majority of peripherals is stopped. The main oscillator continues operation. PLL and SSCG are stopped. By default, internal oscillator and sub oscillator operation is not affected. For exceptions see “Internal and sub oscillator operation“...
Page 176 Chapter 4 Clock Generator Sub-WATCH mode In Sub-WATCH mode, the clock supply for the CPU and the majority of peripherals is stopped. Main oscillator, PLL, and SSCG are stopped. By default, internal oscillator and sub oscillator operation is not influenced. For exceptions see “Internal and sub oscillator operation“...
Page 177 Chapter 4 Clock Generator STOP mode In STOP mode, all clock sources are stopped, except sub and internal oscillator. These can be configured in register WCC to stop as well. No clock is available, and no internal self-timed processes operates. Table 4-29 Clock Generator status in STOP mode Item...
Page 178 R01UH0129ED0701 Rev. 7.01 User Manual...
Page 179 R01UH0129ED0701 Rev. 7.01 User Manual...
Page 180 R01UH0129ED0701 Rev. 7.01 User Manual...
Page 181: Clock Generator State Transitions
4.3.2 Clock Generator state transitions VBCLK state transitions R01UH0129ED0701 Rev. 7.01 User Manual...
Page 182 Main oscillator state transitions Reset MainOSC started by F/W PSM release from MainOSC - STOP (PSM[1:0] = 01 stabilization - SDC.SDCR = 1 and OSCDIS = 0 Stabilization counter expired PSM entry with PSM release from - PSM[1:0] = 01 (STOP) MainOSC MainOSC...
Page 183: Power Save Mode Activation
4.3.3 Power save mode activation In the following procedures for securely entering a power save mode are described. Stepper-C/D shut In order to minimize power consumption during power save modes the Stepper down Motor Controller/Driver needs to be shut down in a special sequence. Refer to “MCNTCn0, MCNTCn1 - Timer mode control registers“...
Page 184 Example The following example shows how to initialize and enter a WATCH, Sub- WATCH, STOP or IDLE power save mode. First the desired power save mode is specified (WATCH mode in this example, that means PSM.PSM[1:0] = 10 The PSC register is a write-protected register, and the PRCMD register is the corresponding write-enable register.
Page 185 At least 5 “nop” instructions must follow the power down mode setting, that means after the write to PSC. The microcontroller requires this time to enter power down mode. The data written to the PRCMD register must be the same data that shall be written to the write-protected register afterwards.
Page 186: Cpu Operation After Power Save Mode Release
4.3.4 CPU operation after power save mode release Clock Generator re- The clock for the CPU system can be switched only once after reset, power configuration save mode release, or the default clock setup request (SDC.SDCR = 1). The clocks for the Watchdog Timer, Watch Timer, and LCD Controller/Driver can be switched only once after system reset.
Page 187 Table 4-31 Power save mode wake-up configurations CGSTAT.CMPLPSM Registers and Configuration after wake-up clock paths before PSM-RQ after wake-up not changed PSM-RQ not accepted changed PSM-RQ accepted configuration done, but PLL/ SSCG operating not changed not possible changed PSM-RQ accepted configuration done, PLL/SSCG not changed not possible...
Page 188 remains active. After WATCH mode release the main oscillator is chosen as the CPU system clock. • If PSM.OSCDIS was 1 before entering WATCH mode the main oscillator is stopped during WATCH mode. After WATCH mode release the main oscillator is automatically started, the oscillator stabilization time is waited and the main oscillator is chosen as the CPU system clock.
Page 189: Clock Generator Operation
4.4 Clock Generator Operation 4.4.1 Internal and sub oscillator operation By default, sub and internal oscillator operate during all power save modes. However, it can be specified in the WCC register that the sub oscillator stops in STOP mode (WCC.SOSTP). It can also be specified that the internal oscillator stops in WATCH, Sub- WATCH, and STOP mode (WCC.ROSTP).
Page 190: Default Clock Generator Setup
4.4.4 Default clock generator setup The Clock Generator can be reset to the clock settings that are used by default after power save mode release. This is done by setting bit SDC.SDCR. For this kind of reset, it is not necessary to enter a power save mode, and no wake-up signal is required.
Page 191: Operation Of The Clock Monitors
4.4.5 Operation of the Clock Monitors The microcontroller provides two separate clock monitors to watch the activity of the main oscillator and the sub oscillator. Description The functional block diagram is shown below. CLKM_MAIN main osc CGSTAT.OSCSTAT start output RESCMM CLMM.CLMEM CLKM_SUB sub osc...
Page 192 Since CLMCS.CMRT = 1 is synchronized with the internal oscillator any change of this bit has to be maintained for at least 65 internal oscillator periods = 1/f to become effective. Therefore a wait period has to be ROSC ROSC assured before this bit is changed again.
Page 193: Chapter 5 Interrupt Controller (Intc)
Chapter 5 Interrupt Controller (INTC) This controller is provided with a dedicated Interrupt Controller (INTC) for interrupt servicing and can process a large amount of maskable and two non- maskable interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 194 Chapter 5 Interrupt Controller (INTC) Table 5-1 µPD70F3421, µPD70F3422, µPD70F3423 interrupt/exception source list (1/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Reset Interrupt RESET RESET input – 0000 00000000 undef. Non- Interrupt NMI0...
Page 195 Chapter 5 Interrupt Controller (INTC) Table 5-1 µPD70F3421, µPD70F3422, µPD70F3423 interrupt/exception source list (2/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTP2OV TMP2 overflow 0210 00000210 next PC Interrupt INTTP2CC0 TMP2 capture compare...
Page 196 Chapter 5 Interrupt Controller (INTC) Table 5-1 µPD70F3421, µPD70F3422, µPD70F3423 interrupt/exception source list (3/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTC0ERR CAN0 error interrupt 03A0 000003A0 next PC Interrupt INTC0WUP CAN0 wake up interrupt...
Page 197 Chapter 5 Interrupt Controller (INTC) Table 5-1 µPD70F3421, µPD70F3422, µPD70F3423 interrupt/exception source list (4/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTG2OV0 TMG2 overflow interrupt 0 0590 00000590 next PC Interrupt INTTG2OV1...
Page 198 Chapter 5 Interrupt Controller (INTC) Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 interrupt/ exception source list (1/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Reset Interrupt RESET RESET input – 0000 00000000 undef.
Page 199 Chapter 5 Interrupt Controller (INTC) Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 interrupt/ exception source list (2/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTP2OV TMP2 overflow 0210 00000210 next PC Interrupt INTTP2CC0...
Page 200 Chapter 5 Interrupt Controller (INTC) Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 interrupt/ exception source list (3/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTC0ERR CAN0 error interrupt 03A0 000003A0 next PC Interrupt...
Page 201 Chapter 5 Interrupt Controller (INTC) Table 5-2 µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 interrupt/ exception source list (4/4) Interrupt/Exception Source Classific Default Exception Handler Restored Type Generating ation Priority Code Address Name Generating Source Unit Maskable Interrupt INTTG2OV0 TMG2 overflow interrupt 0 0590 00000590 next PC...
Page 202: Non-Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.2 Non-Maskable Interrupts A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. Non-maskable interrupts of this microcontroller are available for the following two requests: • NMI0: NMI pin input •...
Page 203 Chapter 5 Interrupt Controller (INTC) NMI0 and NMIWDT requests generated simultaneously Main routine NMIWDT servicing NMI0 and NMIWDT requests System reset (generated simultaneously) Figure 5-1 Example of non-maskable interrupt request acknowledgement operation: multiple NMI requests generated at the same time R01UH0129ED0701 Rev.
Page 204 Chapter 5 Interrupt Controller (INTC) NMI being NMI request generated during NMI servicing serviced NMI0 NMIWDT NMI0 request generated during NMIWDT request generated NMI0 NMI0 servicing during NMI0 servicing (NP = 1 retained before NMI1 request) Main routine Main routine NMI0 servicing NMI0 servicing NMIWDT request...
Page 205: Operation
Chapter 5 Interrupt Controller (INTC) 5.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010 to the higher halfword (FECC) of ECR.
Page 206: Restore
Chapter 5 Interrupt Controller (INTC) 5.2.2 Restore NMI0 Execution is restored from the non-maskable interrupt (NMI0) processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 207: Non-Maskable Interrupt Status Flag (Np)
Chapter 5 Interrupt Controller (INTC) 5.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) processing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 208: Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control).
Page 209 Chapter 5 Interrupt Controller (INTC) INT input INTC accepted xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently processed? Priority higher than that of other interrupt request? Highest default priority of interrupt requests with the same priority? Maskable interrupt request Interrupt request pending...
Page 210: Restore
Chapter 5 Interrupt Controller (INTC) 5.3.2 Restore Recovery from maskable interrupt processing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 211 Chapter 5 Interrupt Controller (INTC) There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 212 Chapter 5 Interrupt Controller (INTC) Main routine Processing of a Processing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are enabled.
Page 213 Chapter 5 Interrupt Controller (INTC) Main routine Processing of i Processing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i. (level 1) k that occurs after j is acknowledged because it has the higher priority.
Page 214 Chapter 5 Interrupt Controller (INTC) Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Note Lower default priority Higher default priority Main routine...
Page 215: Xxic - Maskable Interrupts Control Register
Chapter 5 Interrupt Controller (INTC) 5.3.4 xxIC - Maskable interrupts control register An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F110 to FFFF F18E...
Page 216 Chapter 5 Interrupt Controller (INTC) Table 5-4 Addresses and bits of interrupt control registers (1/3) Address Register FFFFF110 VC0IC VC0IF VC0MK VC0PR2 VC0PR1 VC0PR0 FFFFF112 VC1IC VC1IF VC1MK VC1PR2 VC1PR1 VC1PR0 FFFFF114 WT0UVIC WT0UVIF WT0UVMK WT0UVPR2 WT0UVPR1 WT0UVPR0 FFFFF116 WT1UVIC WT1UVIF WT1UVMK WT1UVPR2...
Page 217 Chapter 5 Interrupt Controller (INTC) Table 5-4 Addresses and bits of interrupt control registers (2/3) Address Register FFFFF162 TG1CC0C TG1CC0IF TG1CC0MK TG1CC0PR2 TG1CC0PR1 TG1CC0PR0 FFFFF164 TG1CC1IC TG1CC1IF TG1CC1MK TG1CC1PR2 TG1CC1PR1 TG1CC1PR0 FFFFF166 TG1CC2IC TG1CC2IF TG1CC2MK TG1CC2PR2 TG1CC2PR1 TG1CC2PR0 FFFFF168 TG1CC3IC TG1CC3IF TG1CC3MK TG1CC3PR2...
Page 218 Chapter 5 Interrupt Controller (INTC) Table 5-4 Addresses and bits of interrupt control registers (3/3) Address Register FFFFF1B2 TG2OV0IC TG2OV0IF TG2OV0MK TG2OV0PR2 TG2OV0PR1 TG2OV0PR0 FFFFF1B4 TG2OV1IC TG2OV1IF TG2OV1MK TG2OV1PR2 TG2OV1PR1 TG2OV1PR0 FFFFF1B6 TG2CC0IC TG2CC0IF TG2CC0MK TG2CC0PR2 TG2CC0PR1 TG2CC0PR0 FFFFF1B8 TG2CC1IC TG2CC1IF TG2CC1MK TG2CC1PR2...
Page 219: Imr0 To Imr6 - Interrupt Mask Registers
Chapter 5 Interrupt Controller (INTC) 5.3.5 IMR0 to IMR6 - Interrupt mask registers These registers set the interrupt mask state for the maskable interrupts. The xxMK bit of the IMRm (m = 0 to 6) registers is equivalent to the xxMK bit of the xxIC register.
Page 220 Chapter 5 Interrupt Controller (INTC) IMR3 IIC0MK UA1TMK UA1RMK UA1REMK UA0TMK UA0RMK UA0REMK CB0TMK CB0RMK CB0REMK C0TRXMK C0RECMK C0WUPMK C0ERRMK ADMK TY0UV1MK IMR4 TZ8UVMK TZ7UVMK TZ6UVMK C1TRXMK C1RECMK C1WUPMK C1ERRMK P7MK INT71MK INT70MK DMA3MK DMA2MK DMA1MK DMA0MK SG0MK IIC1MK IMR5 LCDMK CB2TMK CB2RMK...
Page 221 Chapter 5 Interrupt Controller (INTC) For µPD70F3424, µPD70F3425, µPD70F3426A, µPD70F3427 only: IMR4 TZ8UVMK TZ7UVMK TZ6UVMK C1TRXMK C1RECMK C1WUPMK C1ERRMK P7MK INT71MK INT70MK DMA3MK DMA2MK DMA1MK DMA0MK SG0MK IIC1MK IMR5 LCDMK CB2TMK CB2RMK CB2REMK CB1TMK CB1RMK CB1REMK TG2CC5MK TG2CC4MK TG2CC3MK TG2CC2MK TG2CC1MK TG2CC0MK TG2OV1MK TG2OV0MK TZ9UVMK For µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3427 only: IMR6...
Page 222: Ispr - In-Service Priority Register
Chapter 5 Interrupt Controller (INTC) 5.3.6 ISPR - In-service priority register This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 223: External Maskable Interrupts
Chapter 5 Interrupt Controller (INTC) 5.3.8 External maskable interrupts This microcontroller provides maskable external interrupts INTPn with the following features: • Analog input filter (refer to “Analog filtered inputs“ on page 97) • Interrupt detection selectable for each interrupt input: –...
Page 224: Edge And Level Detection Configuration
Chapter 5 Interrupt Controller (INTC) 5.4 Edge and Level Detection Configuration The microcontroller provides the maskable external interrupts INTPn and one non-maskable interrupt (NMI). INTPn can be configured to generate interrupts upon edges or levels, the NMI can be set up to react on edges. INTM0 to INTM3 - External interrupt configuration register External interrupt function is configured by the registers INTM0…INTM3.
Page 225 Chapter 5 Interrupt Controller (INTC) The NMI and INTP0 share the same pin. The register bits NMIEN, ESEL0, ESEL01 and ESEL00 configure the NMI and INTP0 interrupt function: Function NMIEN ESEL0 ESEL01 ESEL00 INTP0 falling edge rising edge prohibited both edges masked low level high level...
Page 226: Software Exception
Chapter 5 Interrupt Controller (INTC) 5.5 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 5.5.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to EIPC.
Page 227: Restore
Chapter 5 Interrupt Controller (INTC) 5.5.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1.
Page 228: Exception Status Flag (Ep)
Chapter 5 Interrupt Controller (INTC) 5.5.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. Initial Value 0000 0020 .
Page 229: Exception Trap
Chapter 5 Interrupt Controller (INTC) 5.6 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. For this microcontroller, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 5.6.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111 , a sub-opcode...
Page 230 Chapter 5 Interrupt Controller (INTC) Exception trap (ILGOP) occurs DBPC restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing Figure 5-12 Exception trap processing Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 231: Debug Trap
Chapter 5 Interrupt Controller (INTC) 5.6.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. Operation When the debug trap is generated, the CPU performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode.
Page 232 Chapter 5 Interrupt Controller (INTC) Restore Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 233: Multiple Interrupt Processing Control
Chapter 5 Interrupt Controller (INTC) 5.7 Multiple Interrupt Processing Control Multiple interrupt processing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first.
Page 234 Chapter 5 Interrupt Controller (INTC) Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction TRAP/exception acknowledgment • Saved value restored to EIPSW •...
Page 235: Interrupt Response Time
Chapter 5 Interrupt Controller (INTC) 5.8 Interrupt Response Time The following table describes the interrupt response time (from interrupt generation to start of interrupt processing). Except in the following cases, the interrupt response time is a minimum of 5 clocks. •...
Page 236: Periods In Which Interrupts Are Not Acknowledged
Chapter 5 Interrupt Controller (INTC) 5.9 Periods in Which Interrupts Are Not Acknowledged An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction. The interrupt request non-sampling instructions are as follows: •...
Page 237: Chapter 6 Flash Memory
Chapter 6 Flash Memory The µPD70F3421, µPD70F3422, µPD70F3423, µPD70F3424, µPD70F3425, µPD70F3426A and µPD70F3427 microcontrollers are equipped with internal flash memory. The flash memory is attached to the V850 Fetch Bus (VFB) interface of the V850E CPU core, or in case of more than 1 MB flash memory for the µPD70F3426A additionally to the V850 System Bus (VSB).
Page 238: Overview
Chapter 6 Flash Memory 6.1 Overview Features summary • Internal VFB flash memory: – µPD70F3427, µPD70F3426A, µPD70F3425: 1 MB – µPD70F3424, µPD70F3423: 512 KB – µPD70F3422: 384 KB – µPD70F3421: 256 KB • Internal VSB flash memory: – µPD70F3426A: 1 MB •...
Page 239: Flash Memory Address Assignment
Chapter 6 Flash Memory 6.1.1 Flash memory address assignment The 1 MB VFB flash memory of µPD70F3427, µPD70F3426A, and µPD70F3425 is made up of 256 blocks. Figure 6-1 shows the address assignment of the flash memory blocks. 0010 0000 Block 255 (4 KB) 000F F000 Block 254 (4 KB) 000F E000...
Page 240 Chapter 6 Flash Memory The 512 KB flash memory of µPD70F3424, and µPD70F3423 is made up of 128 blocks. Figure 6-2 shows the address assignment of the flash memory blocks. 0008 0000 Block 127 (4 KB) 0007 F000 Block 126 (4 KB) 0007 E000 0000 2000 Block 1 (4 KB)
Page 241: Flash Memory Erasure And Rewrite
Chapter 6 Flash Memory The 256 KB flash memory of µPD70F3421 is made up of 64 blocks. Figure 6-4 shows the address assignment of the flash memory blocks. 0004 0000 Block 63 (4 KB) 0003 F000 Block 62 (4 KB) 0003 E000 0000 2000 Block 1 (4 KB)
Page 242: Flash Memory Programming
For comprehensive information concerning secure boot block swapping refer to the application note “Self-Programming” (document no. U16929EE), which explains also the functions of the self-programming library. The latest version of this document can be loaded via the URL http://www.renesas.eu/updates R01UH0129ED0701 Rev. 7.01 User Manual...
Page 243: Flash Self-Programming
This feature enables the user’s application to re-program the flash memory. The self-programming functions are part of the internal firmware, which resides in an extra internal ROM. The user’s application can call the self- programming functions via the self-programming library, provided by Renesas Electronics. Caution During self-programming make sure to disable all ROM correction facilities, as enabled ROM corrections may conflict with the internal firmware.
Page 244 Chapter 6 Flash Memory SELFEN - Self-programming enable control register The 8-bit SELFEN register enables the self-programming functions by software. It is an internal substitute to enabling self-programming by rising the FLMD0 pin to high level. Access This registers can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions.
Page 245: Interrupt Handling During Flash Self-Programming
The latest version of this document can be loaded via the URL http://www.renesas.eu/updates Since neither the interrupt vector table nor the interrupt handler routines, which are normally located in the flash memory, are accessible during self- programming, interrupt acknowledges have to be re-routed to non-flash memory, i.e.
Page 246: Flash Programming Via N-Wire
Chapter 6 Flash Memory 6.3 Flash Programming via N-Wire The microcontroller’s flash memory is programmable via the N-Wire debug interface. Programming of the flash memory can be performed by the debug tool running on the host machine. Caution Programming the flash memory during debug sessions by the debug tool adds to the performed number of write/erase cycles of the flash memory.
Page 247: Flash Programming With Flash Programmer
Chapter 6 Flash Memory 6.4 Flash Programming with Flash Programmer A dedicated flash programmer can be used for on-board or off-board writing of the flash memory. On-board programming The contents of the flash memory can be rewritten with the microcontroller mounted on the target system.
Page 248: Communication Mode
Chapter 6 Flash Memory If the CSIB interface is used with handshake, the flash programmer’s HS signal is connected to a certain V850 port. The port used as the handshake port is given in Table 6-2. Flash memory programming off-board requires a dedicated program adapter. UARTA0 or CSIB0 is used as the interface between the flash programmer and the microcontroller.
Page 249 Chapter 6 Flash Memory FLMD0 (FLMD1 Note Note FLMD0 (FLMD1 RESET RESET V850 SOB0 microcontroller flash programmer SIB0 SCKB0 Note: FLMD1 connection may be replaced by a pull-down resistor on the board Figure 6-7 Communication with flash programmer via CSIB0 without handshake CSIB0 with handshake (CSIB0 + HS) Serial clock: Up to 2.5 MHz (MSB first) FLMD0 (FLMD1...
Page 250 Chapter 6 Flash Memory Table 6-2 Signals generated by flash programmer PG-FP5 PG-FP5 Controller Connection Signal Pin function Pin name UARTA0 CSIB0 CSIB0 + HS name FLMD0 Output Write enable/disable, FLMD0 mode setting × × × FLMD1 Output Mode setting FLMD1 voltage generation/voltage monitor...
Page 251: Pin Connection
Chapter 6 Flash Memory 6.4.3 Pin connection A connector must be mounted on the target system to connect the flash programmer for on-board writing. In addition, a function to switch between the normal operation mode and flash memory programming mode must be provided on the board.
Page 252 Chapter 6 Flash Memory Connection to flash programmer In the normal operation mode, 0 V is input to the FLMD0 pin. The pull-down resistor at the FLMD0 pin ensures normal operation mode if no flash programmer is connected. In the flash memory programming mode, the V write voltage is supplied to the FLMD0 pin.
Page 253 Chapter 6 Flash Memory maximum driver capability in order to maximize the transmission data rate to the flash programmer. Caution Since the output drive strength control of the pins TXDA0, SOB0 and P84 is disabled during programming these pins are not short-circuit proof any more.
Page 254: Programming Method
Chapter 6 Flash Memory 6.4.4 Programming method In the following the flash programming flow is described, if the CSI or the UART is used as the communication interface. Flash memory control The procedure to manipulate the flash memory is illustrated below. Figure 6-10 Flash memory manipulation procedure Flash memory programming mode...
Page 255 Chapter 6 Flash Memory RESET (input) FLMD1 (input) FLMD0 (input) (Note) RXDA0 (input) TXDA0 (output) Oscillation Communication stabilization mode selection Power Reset Flash control command communication supply release (such as erase and write) Figure 6-11 Flash memory programming mode start-up Note The number of clocks to be inserted differs depending on the chosen communication mode.
Page 256 Chapter 6 Flash Memory Communication commands The microcontroller communicates with the flash programmer via commands. The commands sent to the microcontroller are called commands, and the response signals sent by the microcontroller to the flash programmer are called response commands. Command Response command...
Page 257 Chapter 6 Flash Memory The microcontroller returns a response command to the command issued by the flash programmer. The response commands sent by the microcontroller are listed below. Table 6-7 Response commands Response command name Function Acknowledges command/data. Acknowledges illegal command/data. R01UH0129ED0701 Rev.
Page 258: Chapter 7 Bus And Memory Control (Bcu, Memc)
Chapter 7 Bus and Memory Control (BCU, MEMC) Besides providing access to on-chip peripheral I/Os, the µPD70F3427 microcontroller device supports access to external memory devices (such as external ROM and RAM) and external I/O. The Bus Control Unit BCU and Memory Controller MEMC control the access to on-chip peripheral I/Os and to external devices.
Page 259: Description
Chapter 7 Bus and Memory Control (BCU, MEMC) • Page ROM controller – Direct connection to 8-bit/16-bit/32-bit page ROM supported – Page ROM controller handles page widths from 8 to 128 bytes – On-page judgement function – Masking addresses can be changed by register setting –...
Page 260 Chapter 7 Bus and Memory Control (BCU, MEMC) Busses The busses are abbreviated as follows: • NPB: Peripheral bus • VSB: V850 system bus • VDB: V850 data bus • VFB: V850 fetch bus The Bus Control Unit (BCU) controls the access to on-chip peripherals, to external memory controller (MEMC), the VSB RAM and VSB Flash of the µPD70F3426A device.
Page 261: Memory Banks And Chip Select Signals
Chapter 7 Bus and Memory Control (BCU, MEMC) All port pins are in input port mode after reset. Refer to “Pin Functions“ on page 29. ROMC To access external ROM with page access function (page ROM), the Page ROM Controller (ROMC) is provided. It can handle page widths from 8 to 128 bytes.
Page 262 Chapter 7 Bus and Memory Control (BCU, MEMC) 03FF FFFFH 03FF FFFFH Bank 15 Peripheral I/O area (2 MB) (4 KB) 03E0 0000H 03FF F000H Bank 14 VDB RAM (2 MB) (60 KB) 03C0 0000H 03FF 0000H Bank 13 Programmable peripheral (2 MB) I/O area (PPA) 03A0 0000H...
Page 263 Chapter 7 Bus and Memory Control (BCU, MEMC) 03FF FFFFH 03FF FFFFH Bank 15 Peripheral I/O area (2 MB) (4 KB) 03E0 0000H 03FF F000H Bank 14 VDB RAM (2 MB) (60 KB) 03C0 0000H 03FF 0000H Programmable peripheral Bank 13 I/O area (PPA) (2 MB) 03A0 0000H...
Page 264: Chips Select Priority Control
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.2.2 Chips select priority control The chip select signals CS0 to CS7 can be assigned to overlapping memory areas by setting the chip select area control registers CSC0 and CSC1. The chip select priority control rules the generation of chip select signals in this case.
Page 265 Chapter 7 Bus and Memory Control (BCU, MEMC) Programmable peripheral I/O area (PPA) The usage and the address range of the PPA is configurable. The PPA extends the fixed peripheral I/O area and assigns an additional 12 KB address space for accessing on-chip peripherals.
Page 266: Npb Access Timing
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.2.4 NPB access timing All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register (refer to “Registers Access Times“...
Page 267: Boundary Operation Conditions
Chapter 7 Bus and Memory Control (BCU, MEMC) Table 7-4 Bus priority order Priority External bus cycle Bus master High DMA cycle DMA Controller Operand data access Instruction fetch Bus access The number of CPU clocks necessary for accessing each resource – independent of the bus width –...
Page 268: Initialization For Access To External Devices
Chapter 7 Bus and Memory Control (BCU, MEMC) are performed. In total it takes 3 bus cycles. – When the LSBs of the address are A[1:0] =10 , two halfword accesses are performed. Note Accessing data on misaligned addresses takes more than one bus cycle to complete data read/write.
Page 269: Registers
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.3 Registers Access to on-chip peripherals, to external memory, and to external I/O is controlled and operated by registers of the Bus Control Unit (BCU) and of the Memory Controller (MEMC): Table 7-6 Bus and memory control register overview Module Register name...
Page 270: Bcu Registers
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.3.1 BCU registers The following registers are part of the BCU. They define the usage of the programmable peripheral I/O area (PPA), the data bus width, the endian format of word data, and they control access to external devices. BPC - Peripheral area selection control register The 16-bit BPC register defines whether the programmable peripheral I/O area (PPA) is used or not and determines the starting address of the PPA.
Page 271 Chapter 7 Bus and Memory Control (BCU, MEMC) Note The recommended setting for the BPC register is 8FFB . With this configuration the programmable peripheral area is mapped to the address range 03FE C000 to 03FE FFFF . With this setting the CAN message buffer registers are accessible via the addresses given in “CAN Controller (CAN)“...
Page 272 Chapter 7 Bus and Memory Control (BCU, MEMC) The following setups are recommended for VSWC: Table 7-10 Recommended timing for internal bus System ≤ 16 MHz ≤ 25 MHz ≤ 33 MHz ≤ 50 MHz ≤ 66 MHz clock VBCLK SUWL VSWL VSWC...
Page 273 Chapter 7 Bus and Memory Control (BCU, MEMC) CSCn - Chip area select control registers The 16-bit registers CSC0 and CSC1 assign the chip select signals CS0 to CS3 and CS4 to CS7 to memory blanks (see also “Memory banks and chip select signals“...
Page 274 Chapter 7 Bus and Memory Control (BCU, MEMC) Table 7-11 CSC0 register contents Chip select Bit Position Bit Name Access to memory bank signal CS33 CS32 CS31 4 or 5 CS30 0, 1, 2 or 3 CS23 CS22 CS21 CS20 CS13 CS12 CS11...
Page 275 Chapter 7 Bus and Memory Control (BCU, MEMC) Initialization Initialize the CSCn registers as shown in • Table 7-13 for µPD70F3426A • Table 7-14 for µPD70F3427 Table 7-13 Initialization of the µPD70F3426A CSCn registers Bits Set to value Comment CSC0.CS0[3:0] 0001 CS0 assigned to bank 0 to VSB Flash memory 010 0000...
Page 276 Chapter 7 Bus and Memory Control (BCU, MEMC) Table 7-14 Initialization of the µPD70F3427 CSCn registers Bits Set to value Comment CSC0.CS0[3:0] xx00 Set CSC0.CS0[3:2] as required to assign CS0 to bank 2 to 3 to external memory 040 0000 - 07F FFFF Caution: CSC0.CS0[1:0] must be changed...
Page 277 Chapter 7 Bus and Memory Control (BCU, MEMC) BEC - Endian configuration register The 16-bit BEC register defines the endian format in which word data in the memory is processed. Each chip select area is controlled separately. Access This register can be read/written in 16-bit units. Address FFFF F068 Initial Value...
Page 278 Chapter 7 Bus and Memory Control (BCU, MEMC) Initialization Initialize the BEC register as shown in • Table 7-16 for µPD70F3426A • Table 7-17 for µPD70F3427 Table 7-16 Initialization of the µPD70F3426A BEC register Bits Set to value Comment BEC.BE00 Endian format for VSB Flash memory: little endian BEC.BE00 must be left with their default value...
Page 279: Memory Controller Registers (Μpd70F3427 Only)
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.3.2 Memory controller registers (µPD70F3427 only) The following registers are part of the Memory Controller. They specify the type of external device that is connected, the number of data wait states, the number of address wait states, the number of idle states, and they control features for page ROM.
Page 280 Chapter 7 Bus and Memory Control (BCU, MEMC) – bits BCTn.BTm are set to 0 – bits BCTn.MEm are retained – bus clock is stopped • entering normal operation mode by setting BMC.PWDN = 0 – bits BCTn.MEm are set to 0 –...
Page 281 Chapter 7 Bus and Memory Control (BCU, MEMC) ASC - Address setup wait control register The 16-bit ASC register controls the number of wait states between address setup and the first access cycle (T1). Each chip select area is controlled separately.
Page 282 Chapter 7 Bus and Memory Control (BCU, MEMC) DWCn - Data wait control registers The 16-bit DWCn registers control the number of wait states after the first access cycle (T1). Each chip select area is controlled separately. A maximum of seven data wait states is possible. Access This register can be read/written in 16-bit units.
Page 283 Chapter 7 Bus and Memory Control (BCU, MEMC) BCC - Bus cycle control register The 16-bit BCC register controls the number of idle states inserted after the T2 cycle. Each chip select area is controlled separately. A maximum of three idle states is possible.
Page 284 Chapter 7 Bus and Memory Control (BCU, MEMC) BMC- Bus mode control register The 8-bit BMC register controls the operation of the memory interface and its clock supply. Access This register can be read/written in 8- and 1-bit units. Address FFFF F498 Initial Value PDWN...
Page 285 Chapter 7 Bus and Memory Control (BCU, MEMC) Example for setting the BMC.CMK0 bit ld.b VSWC[r0],r11 // save the origin VSWC register setting 0x07,r11,r10 // set VSWC.VSWL[2:0] bits to 1 st.b r10,VSWC[r0] set1 0,BMC[r0] // set the CMK0 bit to 1 st.b r11,VSWC[r0] // restore the origin VSWC register setting...
Page 286 Chapter 7 Bus and Memory Control (BCU, MEMC) PRC - Page ROM configuration register The 16-bit PRC register controls whether a page ROM cycle is on-page or off-page. The register specifies the address mask. Masked address bits are not considered when deciding between on-page or off-page access. Set the mask according to the number of continuously readable bits.
Page 287 Chapter 7 Bus and Memory Control (BCU, MEMC) Note To initialize an external memory area after a reset, register PRC has to be set if page ROM mode is selected. Do not change this register after initialization. Do not access external page ROM devices before initialization is finished. Caution To initialize an external memory area after a reset, this register has to be set.
Page 288: Page Rom Controller
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.4 Page ROM Controller In page ROM mode the microcontroller reads consecutive data from one page by inserting the wait cycles defined by PRC.PRW[2:0] instead of wait cycles defined in registers DWC0 and DWC1. The page ROM controller decides whether a page ROM cycle is on-page or off-page.
Page 289 Chapter 7 Bus and Memory Control (BCU, MEMC) 16-bit data bus width The page size or the number of continuously readable bits is 8 x 16 bit. To provide 8 addresses, a 3-bit on-page address is required. Therefore, set PRC.MA[6:3] = 0001 Note For a 16-bit data bus, bit A0 of the output address is not used.
Page 290: Configuration Of Memory Access
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.5 Configuration of Memory Access The microcontroller device supports interfacing with various memory devices. Therefore, the endian format, wait functions and idle state insertions can be configured. 7.5.1 Endian format The endian format is specified with the endian configuration register (BEC). It defines the byte order in which word data is stored.
Page 291 Chapter 7 Bus and Memory Control (BCU, MEMC) Programmable wait function With the purpose of realizing easy interfacing with low-speed memory or with I/Os, it is possible to insert up to seven data wait states after the first access cycle (T1 state). The number of wait states can be specified by data wait control registers DWC0 and DWC1.
Page 292: Idle State Insertion
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.5.3 Idle state insertion To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted between two bus cycles, that means after the T2 state. Idle states are inserted to meet the data output float delay time on memory read access for each CS space.
Page 293: Writing To External Devices
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.6.1 Writing to external devices This section shows typical sequences of writing data to external devices. Write with external wait cycle BCLK A[23:0]/BE[3:0] Address /BE[3:0] Address /BE[3:0] (output) CSk (output) RD (output) WR (output) D]31:0] (I/O) Data...
Page 294 Chapter 7 Bus and Memory Control (BCU, MEMC) Write with address setup wait and idle state insertion TASW BCLK A[23:0]/BE[3:0] Address /BE[3:0] (output) CSk (output) RD (output) WR (output) D[31:0] (I/O) Data WAIT (input) Figure 7-12 Timing: write data with address setup wait and idle state insertion Register settings: •...
Page 295: Reading From External Devices
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.6.2 Reading from external devices This section shows typical sequences of reading data from external devices. Read with external wait cycle BCLK A[23:0]/BE[3:0] Address /BE[3:0] Address /BE[3:0] (output) CSk (output) RD (output) WR (output) D[31:0] (I/O) Data...
Page 296 Chapter 7 Bus and Memory Control (BCU, MEMC) Read with address setup wait and idle state insertion TASW BCLK A[23:0]/BE[3:0] Address /BE[3:0] (output) CSk (output) RD (output) WR (output) D[31:0] (I/O) Data WAIT (input) Figure 7-14 Timing: read data with address setup wait and idle state insertion Register settings: •...
Page 297: Read-Write Operation On External Devices
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.6.3 Read-write operation on external devices BCLK A[23:0]/BE[3:0] Address /BE[3:0] (output) CSk (output) RD (output) WR (output) D[31:0] (I/O) DataData WAIT (input) Figure 7-15 Read-write operation Register settings: • BCTm.BTk0 = 0 (connected external device is SRAM or external I/O) •...
Page 298: Write-Read Operation On External Devices
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.6.4 Write-read operation on external devices BCLK A[23:0]/BE[3:0] Address/BE[3:0] (output) CSk (output) RD (output) WR (output) Data D[31:0] (I/O) Data WAIT (input) Figure 7-16 Write-read operation Register settings: • BCTm.BTk0 = 0 (connected external device is SRAM or external I/O) •...
Page 299: Page Rom Access Timing
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.7 Page ROM Access Timing This section presents examples of read operations on page ROM. The states are abbreviated as: • T1 and T2 states: Basic states for access. • TW state: Wait state that is inserted according to the DWC0 and DWC1 register settings and according to the WAIT input.
Page 300: Half Word/Word Access With 8-Bit Bus Or Word Access With 16-Bit Bus
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.7.1 Half word/word access with 8-bit bus or word access with 16- bit bus Read operation Note that during on-page access, less data wait states are inserted than during off-page access. BCLK A[23:0]/BE[3:0] Off-page address/BE[3:0] On-page address/BE[3:0]...
Page 301 Chapter 7 Bus and Memory Control (BCU, MEMC) Read operation with address setup wait states and idle state insertion TASW TASW BCLK A[23:0] /BE[3:0] Off-page address /BE[3:0] On-page address /BE[3:0] (output) CSk (output) RD (output) WR (output) D[7:0] (I/O) Data Data D[15:0] (I/O) WAIT (input)
Page 302: Byte Access With 8-Bit Bus Or Byte/Half Word Access With 16-Bit Bus
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.7.2 Byte access with 8-bit bus or byte/half word access with 16- bit bus Read operation Note that during on-page access, less data wait states are inserted than during off-page access. BCLK A[23:0] /BE[3:0] Off-page address/BE[3:0] On-page address/BE[3:0]...
Page 303 Chapter 7 Bus and Memory Control (BCU, MEMC) Read operation with address setup wait states and idle state insertion TASW TASW BCLK A[23:0] /BE[3:0] Off-page address/BE[3:0] On-page address/BE[3:0] (output) CSk (output) RD (output) WR (output) D[7:0] (I/O) Data Data D[15:0] (I/O) WAIT (input) BCC.BCk[1:0] Figure 7-20...
Page 304: Data Access Order
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.8 Data Access Order 7.8.1 Access to 8-bit data busses This section shows how byte, half word and word accesses are performed for an 8-bit data bus. Byte access (8 bits) (a) Little endian Address Address 2n + 1...
Page 305 Chapter 7 Bus and Memory Control (BCU, MEMC) Halfword access (16 bits) (a) Little endian 1-st Access 1-st Access 2-nd Access 2-nd Access Address Address Address Address 2n + 1 2n + 1 2n + 2 Halfword External Halfword External Halfword External Halfword...
Page 306 Chapter 7 Bus and Memory Control (BCU, MEMC) Word access (32 bits) (a) Little endian 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data External Word data External...
Page 307 Chapter 7 Bus and Memory Control (BCU, MEMC) 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External Word data External...
Page 308 Chapter 7 Bus and Memory Control (BCU, MEMC) (b) Big endian 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External Word data External Word data External Word data External...
Page 309 Chapter 7 Bus and Memory Control (BCU, MEMC) 1-st Access 2-nd Access 3-rd Access 4-th Access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External Word data External Word data External Word data External...
Page 310: Access To 16-Bit Data Busses
Chapter 7 Bus and Memory Control (BCU, MEMC) 7.8.2 Access to 16-bit data busses This section shows how byte, half word and word accesses are performed for a 16 bit data bus. Access all data in order starting from the lower order side. Byte access (8 bits) (a) Little endian Address...
Page 311 Chapter 7 Bus and Memory Control (BCU, MEMC) Halfword access (16 bits) (a) Little endian 1-st Access 2-nd Access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword External Halfword External Halfword External data data bus data data bus data...
Page 312 Chapter 7 Bus and Memory Control (BCU, MEMC) Word access (32 bits) (a) Little endian 1-st Access 2-nd Access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data External data bus data bus Figure 7-37 Access to address 4n 1-st Access...
Page 313 Chapter 7 Bus and Memory Control (BCU, MEMC) 1-st Access 2-nd Access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data External data bus data bus Figure 7-39 Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access...
Page 314 Chapter 7 Bus and Memory Control (BCU, MEMC) (b) Big endian 1-st Access 2-nd Access Address Address 4n + 2 4n + 1 4n + 3 Word data External Word data External data bus data bus Figure 7-41 Access to address 4n 3-rd Access 1-st Access 2-nd Access...
Page 315 Chapter 7 Bus and Memory Control (BCU, MEMC) 1-st Access 2-nd Access Address Address 4n + 2 4n + 4 4n + 3 4n + 5 Word data External Word data External data bus data bus Figure 7-43 Access to address 4n + 2 1-st Access 2-nd Access 3-rd Access...
Page 316: Chapter 8 Dma Controller (Dmac)
Chapter 8 DMA Controller (DMAC) The microcontroller includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfers. Note Throughout this chapter, the individual channels of the DMA Controller are identified by “n”. The DMAC controls data transfer between memory and I/O or among I/Os, based on DMA requests issued by the on-chip peripheral I/O, or software triggers.
Page 317 Chapter 8 DMA Controller (DMAC) Caution Special care must be taken when using the internal RAM as DMA source or destination. Refer to “Simultaneous program execution and DMA transfer with internal RAM“ on page 342. • DMA transfer completion flag •...
Page 318: Peripheral And Cpu Clock Settings
Chapter 8 DMA Controller (DMAC) 8.2 Peripheral and CPU Clock Settings In order to ensure safe capture of DMA trigger signals from the involved peripheral functions, a certain minimum relation between the operation clock of the concerned peripheral function and the CPU system has to be regarded. In the following table the minimum CPU system clock frequency f is given VBCLK...
Page 319 Chapter 8 DMA Controller (DMAC) Table 8-1 Peripheral functions and CPU system clocks for DMA transfers (2/2) SPCLKn, PCLKn Minimum Input clock configuration Peripheral Clock controller settings VBCLK [MHz] [MHz] Peripheral clock Source ICC = 00 IICLK MainOsc 6.00 ICC = 72 PLL / 4.5 7.11 10.67...
Page 320: Dmac Registers
Chapter 8 DMA Controller (DMAC) 8.3 DMAC Registers 8.3.1 DMA Source address registers These registers are used to set the DMA source addresses (28 bits each) for DMA channel n. They are divided into two 16-bit registers, DSAHn and DSALn. Since these registers are configured as 2-stage FIFO buffer registers, a new source address for DMA transfer can be specified during DMA transfer (refer to “Automatic Restart Function“...
Page 321 Chapter 8 DMA Controller (DMAC) DSALn - DMA source address registers Ln Access These registers can be read/written in 16-bit units. Address DSAL0: FFFF F080 DSAL1: FFFF F088 DSAL2: FFFF F090 DSAL3: FFFF F098 Initial Value undefined SA15 SA14 SA13 SA12 SA11 SA10 SA9 Table 8-3 DSALn register contents Bit position...
Page 322: Dma Destination Address Registers
Chapter 8 DMA Controller (DMAC) 8.3.2 DMA destination address registers These registers are used to set the DMA destination address (28 bits each) for DMA channel n. They are divided into two 16-bit registers, DDAHn and DDALn. Since these registers are configured as 2-stage FIFO buffer registers, a new destination address for DMA transfer can be specified during DMA transfer (refer to “Automatic Restart Function“...
Page 323 Chapter 8 DMA Controller (DMAC) DDALn - DMA destination address registers Ln Access These registers can be read/written in 16-bit units. Address DDAL0: FFFF F084 DDAL1: FFFF F08C DDAL2: FFFF F094 DDAL3: FFFF F09C Initial Value undefined DA15 DA14 DA13 DA12 DA11 DA10 DA9 Table 8-5 DDALn regsiter contents Bit position...
Page 324: Dbcn - Dma Transfer Count Registers
Chapter 8 DMA Controller (DMAC) 8.3.3 DBCn - DMA transfer count registers These 16-bit registers are used to set the transfer counts for DMA channels n. They store the remaining transfer counts during DMA transfer. Since these registers are configured as 2-stage FIFO buffer registers, a new DMA transfer count for DMA transfer can be specified during DMA transfer (refer to “Automatic Restart Function“...
Page 325: Dadcn - Dma Addressing Control Registers
Chapter 8 DMA Controller (DMAC) 8.3.4 DADCn - DMA addressing control registers These 16-bit registers are used to control the DMA transfer modes for DMA channel n. Access These registers can be read/written in 16-bit units. Address DADC0: FFFF F0D0 DADC1: FFFF F0D2 DADC2: FFFF F0D4 DADC3: FFFF F0D6...
Page 326 Chapter 8 DMA Controller (DMAC) Caution These registers cannot be accessed during DMA operation. R01UH0129ED0701 Rev. 7.01 User Manual...
Page 327: Dchcn - Dma Channel Control Registers
Chapter 8 DMA Controller (DMAC) 8.3.5 DCHCn - DMA channel control registers These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n. Access These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 328: Drst - Dma Restart Register
Chapter 8 DMA Controller (DMAC) 8.3.6 DRST - DMA restart register The ENn bit of this register and the ENn bit of the DCHCn register are linked to each other. This provides a fast way to check the status of all DMA channels. Access This register can be read/written in 8-bit or 1-bit units.
Page 329: Dtfrn - Dma Trigger Source Select Register
Chapter 8 DMA Controller (DMAC) 8.3.7 DTFRn - DMA trigger source select register The 8-bit DMA trigger source selection registers are used to control the DMA transfer triggers for the individual DMA channels. These triggers initiate DMA transfer requests received from built-in peripheral hardware. Interrupt signals are used as DMA transfer requests.
Page 330 Chapter 8 DMA Controller (DMAC) 2. Set the DMA request bit DTFRn.DRQn = 0 in parallel to changing DTFRn.IFCn[2:0], i.e. within the same write operation. Thus DTFRn must be written in 8-bit access mode. Do not change DTFRn.IFCn[2:0] with single-bit instructions. The following list details the functions of the individual DMA trigger sources referenced in the above table.
Page 331 Chapter 8 DMA Controller (DMAC) DMACTn DMA active count DMACTn=0 must be set if internal RAM is not specified as source or destination DMACTn=1 must be set if internal RAM is specified as source or destination Set DMACTn according to the following table: Source \ VSB Flash VSB RAM...
Page 332: Dma Setup And Retrigger
Chapter 8 DMA Controller (DMAC) 8.4 DMA setup and retrigger The following describes the correct initial DMA setup and the process for retriggering the DMA process. 8.4.1 DMA initial setup (status after system reset) 1. Disable DMA interrupts INTDMAn in interrupt control registers by setting DMAnIC.DMAnMK = 1.
Page 333: Automatic Restart Function
Chapter 8 DMA Controller (DMAC) 8.5 Automatic Restart Function The DMA source address registers (DSAHn, DSALn), DMA destination address registers (DDAHn, DDALn), and DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO structure, named master and slave register.
Page 334: Transfer Type
Chapter 8 DMA Controller (DMAC) Caution DMA transfer with activated MLE function can only be used in conjunction with hardware requests. Therefore it is not allowed to start a DMA transfer by software trigger (DCHCn.STGn) when DCHCn.MLEn is set. DMA channel transfer may stuck if the MLEn bit is modified during DMA channel operation.
Page 335: Dma Channel Priorities
Chapter 8 DMA Controller (DMAC) 8.8 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > … > DMA channel n In the single-step transfer mode, the DMA Controller releases the buses after each byte/half-word/word transfer.
Page 336: Forcible Interruption
Chapter 8 DMA Controller (DMAC) 8.10 Forcible Interruption DMA transfer can be forcibly interrupted by NMI input during DMA transfer. At such a time, the DMAC clears the ENn bit of the DCHCn register of all channels and the DMA transfer disabled state is entered. An NMI request can then be acknowledged after the DMA transfer executed during NMI input is terminated.
Page 337: Forcible Termination
Chapter 8 DMA Controller (DMAC) 8.11 Forcible Termination In addition to the forcible interruption operation by means of the NMI input, DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register. The following is an example of the operation of a forcible termination. Figure 8-3 shows a block transfer of channel 3 which begins during the DMA block transfer of DMA channel 2.
Page 338: Dma Transfer Completion
Chapter 8 DMA Controller (DMAC) DSAL1, DSAH1, DSAL1, DSAH1, DCHC1 DADC1, DDAL1, DDAH1 DDAL1, DDAH1 (INIT1 bit = 1) DCHC1 Set register Set register Set register Set register DMA Transfer Request CH1 → → → EN1 bit = 1 EN1 bit EN1 bit EN1 bit →...
Page 339: Transfer Mode
Chapter 8 DMA Controller (DMAC) 8.13 Transfer Mode 8.13.1 Single transfer mode In single transfer mode, the DMAC releases the bus after each byte/halfword/ word transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 340 Chapter 8 DMA Controller (DMAC) Figure 8-6 shows DMAC transfers in single transfer mode in which a higher priority DMA transfer request is generated. DMA channels 0 to 2 are used for a block transfer and channel 3 is used for a single transfer. DMA Transfer Request CH0 DMA Transfer...
Page 341: Block Transfer Mode
Chapter 8 DMA Controller (DMAC) Figure 8-8 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within one clock after the end of a single transfer. DMA channels 0, 2 and 3 are used for this single transfer example.
Page 342: Cautions
Chapter 8 DMA Controller (DMAC) 8.14 Cautions 8.14.1 Simultaneous program execution and DMA transfer with internal RAM Details When a DMA transfer with the internal RAM as source or destination and one of the following instructions are fetched from the internal RAM and executed, the CPU may deadlock: •...
Page 343: Mle Bit Usage
Chapter 8 DMA Controller (DMAC) 8.14.2 MLE Bit Usage Details Do not modify the setting of the MLEn bit in the DCHCn register while the DMA channel n is activated and DMA transfers of channel n are executed in the background.
Page 344: Chapter 9 Rom Correction Function (Romc)
Chapter 9 ROM Correction Function (ROMC) This microcontroller features following ROM correction facilities: • “Data Replacement” ROM correction: – 1 x 6 channels for VFB flash memory and ROM The individual channels of each “Data Replacement” ROM correction are identified by “n” (n = 0 to 5) •...
Page 345: Data Replacement" Rom Correction Unit
Chapter 9 ROM Correction Function (ROMC) 9.2 “Data Replacement” ROM Correction Unit 9.2.1 Features • 6 correction channels for VFB flash/ROM (n = 0 to 5) • Programmable correction address for each channel • Programmable correction value for each channel (the value can be an instructions as well as data) •...
Page 346: Data Replacement" Rom Correction Operation
Chapter 9 ROM Correction Function (ROMC) 9.2.2 “Data Replacement” ROM correction operation The “Data Replacement” ROM correction unit compares the address on the V850 fetch bus (VFB) with the contents of the programmable correction address registers CORADRn. If an address matches, a programmable value (instructions or data) is put on the V850 fetch bus instead of the ROM contents.
Page 347 Chapter 9 ROM Correction Function (ROMC) 32-bit word unaligned data replacement The 32-bit wide code/data is not aligned to a word boundary. For the first VFB access the upper half word is replaced by the lower 16-bit of the correction value (refer to Figure 9-4 (a)).
Page 348 Chapter 9 ROM Correction Function (ROMC) 16-bit halfword aligned data replacement The 16-bit wide code/data can be replaced directly by the 16-bit correction value. The upper halfword is not replaced but the original ROM contents is put on the fetch bus. Dat a o n VFB 0xCCCC CORENn...
Page 349: Setting Of Rom Correction Addresses
Chapter 9 ROM Correction Function (ROMC) 9.2.3 Setting of ROM correction addresses The CPU supports access to (32-bit) word and (16-bit) half word aligned and unaligned instructions and data. Aligned words have an address with the lowest two address bits equal 00 , i.e.
Page 350 Chapter 9 ROM Correction Function (ROMC) Unaligned word and halfword correction HWORD1 WORD0_H x100 WORD0_L HWORD0 x000 combine for 2 aligned corrections CORADRn = x000 CORVALn = WORD0_L << 16 + HWORD0 CORADRm = x100 CORVALm = HWORD1 << 16 + WORD0_H Halfwords correction HWORD3 HWORD2...
Page 351: Data Replacement" Rom Correction Registers
Chapter 9 ROM Correction Function (ROMC) 9.2.4 “Data Replacement” ROM correction registers CORCTL0 - VFB flash/ROM “Data Replacement” ROM correction control register 0 This register enables or disables the “Data Replacement” VFB flash/ROM ROM correction of each channel. Access This register can be read/written in 8- and 1-bit units. Address FFFF F900 Initial Value...
Page 352 Chapter 9 ROM Correction Function (ROMC) CORADRnL - VFB flash/ROM “Data Replacement” ROM correction low address register These registers hold the lower 16 bit of the address where the VFB flash/ROM ROM correction should be performed. Access These registers can be read/written in 16- and 8-bit units. Address CORADR0L, CORADR0LL: FFFF F910 CORADR0LH: FFFF F911...
Page 353 Chapter 9 ROM Correction Function (ROMC) CORADRnH - VFB flash/ROM “Data Replacement” ROM correction high address register These registers hold the upper 6 bit of the address where the VFB flash/ROM ROM correction should be performed. Access These registers can be read/written in 16- and 8-bit units. Address CORADR0H, CORADR0HL: FFFF F912 CORADR0HH: FFFF F913...
Page 354 Chapter 9 ROM Correction Function (ROMC) CORVALnL - VFB flash/ROM “Data Replacement” ROM correction value register These registers hold the lower 16 bit of the value that shall replace the original value from the VFB flash/ROM. Access These registers can be read/written in 16-bit units. Address CORVAL0L: FFFF F930 CORVAL1L: FFFF F934...
Page 355 Chapter 9 ROM Correction Function (ROMC) CORVALnH - VFB flash/ROM “Data Replacement” ROM correction value register These registers hold the upper 16 bit of the value that shall replace the original value from the VFB flash/ROM. Access These registers can be read/written in 16-bit units. Address CORVAL0H: FFFF F932 CORVAL1H: FFFF F936...
Page 356: Dbtrap" Rom Correction Unit
Chapter 9 ROM Correction Function (ROMC) 9.3 “DBTRAP” ROM Correction Unit • 1x 8 channels for VFB flash memory and ROM • 1 x 8 channels for VSB flash memory (for µPD70F3426A only) • The individual channels of eachthe “DBTRAP” ROM correction unit are identified by “m”...
Page 357: Dbtrap" Rom Correction Operation
Chapter 9 ROM Correction Function (ROMC) 9.3.1 “DBTRAP” ROM correction operation The “DBTRAP” ROM correction unit compares the address on the V850 fetch bus (VFB) with the contents of the programmable correction address registers CORADm. If an address matches, the DBTRAP instruction opcode is put on the V850 fetch bus instead of the ROM contents.
Page 358: Dbtrap" Rom Correction Registers
Chapter 9 ROM Correction Function (ROMC) Reset & start Initialize microcontroller Set CORADm register Read data for setting ROM Load DBTRAP exception correction from external handler and ROM correction code Set CORCN register CORENm bit = 1? Execute fetch code Fetch address = CORADm? Execute fetch code...
Page 359 Chapter 9 ROM Correction Function (ROMC) This register enables or disables the VFB flash/ROM correction of each channel. Access This register can be read/written in 8- and 1-bit units. Address FFFF F880 Initial Value 0000 COREN7 COREN6 COREN5 COREN4 COREN3 COREN2 COREN1 COREN0...
Page 360 Chapter 9 ROM Correction Function (ROMC) CORADm - VFB flash/ROM “DBTRAP” ROM Correction address register These registers hold the address where the VFB flash/ROM correction should be performed. Access These registers can be read/written in 32-bit (CORADm) and 16-bit units (CORADmL for bits 15 to 0, CORADmH for bits 31 to 16).
Page 361 Chapter 9 ROM Correction Function (ROMC) COR2ADm - VSB flash “DBTRAP” ROM Correction address register (µPD70F3426A only) These registers hold the address where the VSB flash memory correction should be performed. Access These registers can be read/written in 32-bit (COR2ADm) and 16-bit units (COR2ADmL for bits 15 to 0, COR2ADmH for bits 31 to 16).
Page 362: Chapter 10 Code Protection And Security
Chapter 10 Code Protection and Security 10.1 Overview The microcontroller supports various methods for protecting the program code in the flash memory from undesired access, such as illegal read-out or illegal reprogramming. Some interfaces offer in general access to the internal flash memory: N-Wire debug interface, external flash programmer interface, self-programming facilities and test interfaces.
Page 363 Chapter 10 Code Protection and Security Table 10-1 Possible results of ID code comparison N-Wire use enable flag ID code Protection Level Level 2: Full protection N-Wire debug interface cannot be used. user-specific Level 1: ID code protection ID code N-Wire debug interface can only be used if the user enters the correct ID code.
Page 364: Flash Writer And Self-Programming Protection
Chapter 10 Code Protection and Security 10.4 Flash Writer and Self-Programming Protection In general, illegal read-out and re-programming of the flash memory contents is possible via the flash writer interface and the self-programming feature. For protection of the flash memory, the following flags provide various protection levels.
Page 365: Additional Firmware Functions
Chapter 10 Code Protection and Security 10.5 Additional Firmware Functions The internal firmware provides several additional features related to protection and security. These are listed above. 10.5.1 ID-field A dedicated 64-byte ID-field is provided to hold user defined information, like for instance S/W versions.
Page 366: Chapter 11 16-Bit Timer/Event Counter P (Tmp)
Chapter 11 16-bit Timer/Event Counter P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the 16- bit timer/event counter TMP: All devices Instances Names TMP0 to TMP3 Throughout this chapter, the individual instances of Timer P are identified by “n”, for example TMPn, or TPnCTL0 for the TMPn control register 0.
Page 367: Functions
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.2 Functions TMPn has the following functions. • Interval timer • External event counter • External trigger pulse output • One-shot pulse output • PWM output • Free-running timer • Pulse width measurement •...
Page 368 Chapter 11 16-bit Timer/Event Counter P (TMP) • PCLK01 = PCLK0/2 = 2 MHz • PCLK02 = PCLK0/4 = 1 MHz For information about PCLKx, please refer to “Clock Generator“ on page 130. 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register.
Page 369: Tmp Registers
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.4 TMP Registers The TMPn are controlled and operated by means of the following registers: Table 11-1 TMPn registers overview Register name Shortcut Address TMPn control registers 0 TPnCTL0 <base> TMPn control registers 1 TPnCTL1 <base>...
Page 370 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnCTL0 - TMPn control register 0 The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. Access This register can be read/written in 8-bit or 1-bit units. Address <base> Initial Value .
Page 371 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnCTL1 - TMPn control register 1 The TPnCTL1 register is an 8-bit register that controls the operation of TMPn. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 1 Initial Value .
Page 372 Chapter 11 16-bit Timer/Event Counter P (TMP) Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE bit = 1.) The operation is not guaranteed when rewriting is performed with the TPnCE bit = 1.
Page 373 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnIOC1 - TMPn I/O control register 1 The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 374 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnIOC2 - TMPn I/O control register 2 The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin).
Page 375 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnOPT0 - TMPn option register 0 The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 376 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnCCR0 - TMPn capture/compare register 0 The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit.
Page 377 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) Function as capture register When the TPnCCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TPnCCR0 register if the valid edge of the capture trigger input pin (TIPn0 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TPnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIPn0) is detected.
Page 378 Chapter 11 16-bit Timer/Event Counter P (TMP) TPnCCR1 - TMPn capture/compare register 1 The TPnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit.
Page 379 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) Function as capture register When the TPnCCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TPnCCR1 register if the valid edge of the capture trigger input pin (TIPn1 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is stored in the TPnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIPn1) is detected.
Page 380: Operation
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5 Operation TMPn can perform the following operations. TPnCTL1.TPnEST Bit TIPn0 Pin Capture/ Compare Compare Register Operation (Software Trigger Bit) (Ext. Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write External event count Invalid...
Page 381 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal Interval (D + 1) Interval (D + 1) Interval (D + 1) Interval (D + 1) Figure 11-3 Basic timing of operation in interval timer mode When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting.
Page 382 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0 TPnCTL1 0, 0, 0: Interval timer mode (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level with operation of TOPn0 pin disabled...
Page 383 Chapter 11 16-bit Timer/Event Counter P (TMP) Interval timer mode operation flow FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting before setting the TPnCE bit to 1.
Page 384 Chapter 11 16-bit Timer/Event Counter P (TMP) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock, and the output of the TOPn0 pin is inverted. The value of the 16-bit counter is always 0000H.
Page 385 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) Notes on rewriting TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 386 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) Operation of TPnCCR1 register TPnCCR1 register Output TOPn1 pin CCR1 buffer register controller Match signal INTTPnCC1 signal Clear Count clock Output 16-bit counter TOPn0 pin selection controller Match signal INTTPnCC0 signal CCR0 buffer register TPnCE bit TPnCCR0 register Figure 11-5...
Page 387 Chapter 11 16-bit Timer/Event Counter P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed.
Page 388: External Event Count Mode (Tpnmd2 To Tpnmd0 = 001)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.2 External event count mode (TPnMD2 to TPnMD0 = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number of edges have been counted.
Page 389 Chapter 11 16-bit Timer/Event Counter P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 390 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input (e) TMPn counter read buffer register (TPnCNT) The count value of the 16-bit counter can be read by reading the TPnCNT register.
Page 391 Chapter 11 16-bit Timer/Event Counter P (TMP) External event count mode operation flow FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 392 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation timing in external event count mode (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated each time the valid signal of the external event count signal has been detected. The 16-bit counter is always 0000H.
Page 393 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) Notes on rewriting the TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 394 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) Operation of TPnCCR1 register TPnCCR1 register Output TOPn1 pin CCR1 buffer register controller Match signal INTTPnCC1 signal Clear Edge TIPn0 pin 16-bit counter detector Match signal INTTPnCC0 signal TPnCE bit CCR0 buffer register TPnCCR0 register Figure 11-11 Configuration of TPnCCR1 register...
Page 395 Chapter 11 16-bit Timer/Event Counter P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match.
Page 396: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 = 010)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
Page 397 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (software trigger) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Wait Active level Active level Active level width (D width (D...
Page 398 Chapter 11 16-bit Timer/Event Counter P (TMP) Setting of registers in external trigger pulse output mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 399 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input Select valid edge of external event count input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 400 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in external trigger pulse output mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output (software trigger) TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output...
Page 401 Chapter 11 16-bit Timer/Event Counter P (TMP) <1> Count operation start flow <3> PnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the Setting of TPnCCR1 register TPnCCRm register is transferred...
Page 402 Chapter 11 16-bit Timer/Event Counter P (TMP) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected.
Page 403 Chapter 11 16-bit Timer/Event Counter P (TMP) value of the CCRm buffer register may become undefined because the timing of transferring data from the TPnCCRm register to the CCRm buffer register conflicts with writing the TPnCCRm register. (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H.
Page 404 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) Conflict between trigger detection and match with TPnCCR1 register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting.
Page 405 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) Conflict between trigger detection and match with TPnCCR0 register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection.
Page 406 Chapter 11 16-bit Timer/Event Counter P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 407: One-Shot Pulse Output Mode (Tpnmd2 To Tpnmd0 = 011)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin.
Page 408 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register INTTPnCC1 signal TOPn1 pin output Delay Active Delay Active Delay Active level width level width level width −...
Page 409 Chapter 11 16-bit Timer/Event Counter P (TMP) Setting of registers in one-shot pulse output mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 410 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level while operation of TOPn0 pin is disabled 0: Low level 1: High level 0: Disable TOPn1 pin output...
Page 411 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in one-shot pulse output mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is...
Page 412 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the set value. If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 413 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 414: Pwm Output Mode (Tpnmd2 To Tpnmd0 = 100)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.5 PWM output mode (TPnMD2 to TPnMD0 = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOPn0 pin.
Page 415 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register NTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output Active period Cycle Inactive period − D + 1) + 1) Figure 11-22...
Page 416 Chapter 11 16-bit Timer/Event Counter P (TMP) Setting of registers in PWM output mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 417 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input. (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) If D is set to the TPnCCR0 register and D...
Page 418 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in PWM output mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output <1> <2>...
Page 419 Chapter 11 16-bit Timer/Event Counter P (TMP) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed. When the counter is cleared after setting, the Setting of TPnCCR1 register value of compare register m...
Page 420 Chapter 11 16-bit Timer/Event Counter P (TMP) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected.
Page 421 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock −...
Page 422 Chapter 11 16-bit Timer/Event Counter P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 423: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 = 101)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.6 Free-running timer mode (TPnMD2 to TPnMD0 = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Page 424 Chapter 11 16-bit Timer/Event Counter P (TMP) When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the TOPnm pin is inverted.
Page 425 Chapter 11 16-bit Timer/Event Counter P (TMP) When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated.
Page 426 Chapter 11 16-bit Timer/Event Counter P (TMP) Register setting in free-running timer mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1 (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 427 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) TMPn I/O control register 1 (TPnIOC1) TPnIS3 TPnIS2 TPnIS1 TPnIS0 TPnIOC1 Select valid edge of TIPn0 pin input Select valid edge of TIPn1 pin input (e) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2...
Page 428 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in free-running timer mode (a) When using capture/compare register as compare register FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register INTTPnCC1 signal TOPn1 pin output INTTPnOV signal TPnOVF bit <1>...
Page 429 Chapter 11 16-bit Timer/Event Counter P (TMP) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1. TPnCTL1, TPnIOC0, TPnIOC2, TPnOPT0, TPnCCR0, TPnCCR1 The TPnCKS0 to TPnCKS2 bits can be set at the same time...
Page 430 Chapter 11 16-bit Timer/Event Counter P (TMP) (b) When using capture/compare register as capture register FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000 0000 INTTPnCC0 signal TIPn1 pin input 0000 0000 TPnCCR1 register INTTPnCC1 signal INTTPnOV signal TPnOVF bit Cleared to 0 by Cleared to 0 by...
Page 431 Chapter 11 16-bit Timer/Event Counter P (TMP) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1. TPnCTL1, TPnIOC1, TPnOPT0 The TPnCKS0 to TPnCKS2 bits can be set at the same time when counting TPnCE bit = 1 has been started (TPnCE bit = 1).
Page 432 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected.
Page 433 Chapter 11 16-bit Timer/Event Counter P (TMP) capture register each time the INTTPnCCm signal has been detected and for calculating an interval. FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000H INTTPnCC0 signal Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval...
Page 434 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register TIPn1 pin input TPnCCR1 register INTTPnOV signal TPnOVF bit <1> <2> <3> <4> Figure 11-32 Example of incorrect processing when two capture registers are used The following problem may occur when two pulse widths are measured in the free-running timer mode.
Page 435 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1> <2> <3> <4> <5> <6> Figure 11-33 Example when two capture registers are used (using overflow interrupt) Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
Page 436 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1> <2> <3> <4> <5> <6> Figure 11-34 Example when two capture registers are used (without using overflow interrupt) Note...
Page 437 Chapter 11 16-bit Timer/Event Counter P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next.
Page 438 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register INTTPnOV signal TPnOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Figure 11-36 Example when capture trigger interval is long Note The overflow counter is set arbitrarily by software on the internal RAM.
Page 439 Chapter 11 16-bit Timer/Event Counter P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 440: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 = 110)
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
Page 441 Chapter 11 16-bit Timer/Event Counter P (TMP) FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input 0000H TPnCCRm register INTTPnCCm signal INTTPnOV signal Cleared to 0 by TPnOVF bit CLR instruction Figure 11-38 Basic timing in pulse width measurement mode When the TPnCE bit is set to 1, the 16-bit counter starts counting.
Page 442 Chapter 11 16-bit Timer/Event Counter P (TMP) Register setting in pulse width measurement mode (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note Setting is invalid when the TPnEEE bit = 1. (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 443 Chapter 11 16-bit Timer/Event Counter P (TMP) (e) TMPn option register 0 (TPnOPT0) TPnCCS1 TPnCCS0 TPnOVF TPnOPT0 Overflow flag (f) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (g) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPnm pin is detected.
Page 444 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation flow in pulse width measurement mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input 0000H 0000H TPnCCR0 register INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 is performed before setting the...
Page 445 Chapter 11 16-bit Timer/Event Counter P (TMP) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 446: Timer Output Operations
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.5.8 Timer output operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 11-11 Timer output control in each mode Operation Mode TOPn1 Pin TOPn0 Pin Interval timer mode Square wave output External event count mode...
Page 447: Operating Precautions
Chapter 11 16-bit Timer/Event Counter P (TMP) 11.6 Operating Precautions 11.6.1 Capture operation in pulse width measurement and free- running mode When the capture operation is used in pulse width measurement or free-run- ning mode the first captured counter value of the capture registers TPnCCR0/ TPnCCR, i.e.
Page 448: Chapter 12 16-Bit Interval Timer Z (Tmz)
Chapter 12 16-bit Interval Timer Z (TMZ) Timer Z (TMZ) is a general purpose 16-bit timer/counter. The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the general purpose Timer Z: µPD70F3427, µPD70F3426A µPD70F3423, µPD70F3422 µPD70F3425, µPD70F3424 µPD70F3421 Instances Names TMZ0 to TMZ9 TMZ0 to TMZ5 Throughout this chapter, the individual instances of Timer Z are identified by “n”, for example TMZn, or TZnCTL for the TMZn control register.
Page 449: Description
Chapter 12 16-bit Interval Timer Z (TMZ) 12.1.1 Description The TMZ has no external connections. It is built up as illustrated in the following figure. Internal bus TZnCTL TZnR TZCKS1 TZCKS0 TZCKS2 TZnCNT1 TZnCNT0 Reload buffer CNTCLK PCLK2 (4 MHz) 16-bit down counter INTTZnUV PCLK4 (1 MHz)
Page 450: Tmz Registers
Chapter 12 16-bit Interval Timer Z (TMZ) 12.2 TMZ Registers Each Timer Z is controlled and operated by means of the following four registers: Table 12-1 Timer Z registers overview Register name Shortcut Address Timer Z synchronized read register TZnCNT0 <base>...
Page 451 Chapter 12 16-bit Interval Timer Z (TMZ) TZnCTL - TMZn timer control register The 8-bit TZnCTL register controls the operation of the Timer Z. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 6 Initial Value .
Page 452 Chapter 12 16-bit Interval Timer Z (TMZ) TZnCNT0 - TMZn synchronized counter register The TZnCNT0 register is the synchronized register that can be used to read the present value of the 16-bit counter. “Synchronized” means that the read access via the internal bus is synchronized with the maximum counter clock (PCLK2).
Page 453 Chapter 12 16-bit Interval Timer Z (TMZ) TZnCNT1 - TMZn non-synchronized counter register The TZnCNT1 register is the non-synchronized register that can be used to read the present value of the corresponding 16-bit counter. “Non-synchronized” means that the read access via the internal bus is not synchronized with the counter clock.
Page 454 Chapter 12 16-bit Interval Timer Z (TMZ) TZnR - Reload register The TZnR register is a dedicated register for setting the reload value of the corresponding counter. Access This register can be read/written in 16-bit units. Address <base> + 4 Initial Value 0000 .
Page 455: Timing
Chapter 12 16-bit Interval Timer Z (TMZ) 12.3 Timing The contents of the reload register TZnR can be changed at any time, provided the timer is enabled. The contents is then copied to the reload buffer. However, the counter reloads its start value from the buffer when the counter reaches 0. Caution When specifying PCLK4, PLCK5, PCLK7 or PCLK9 as the count clock, a jitter of maximum ±...
Page 456: Timer Start And Stop
Chapter 12 16-bit Interval Timer Z (TMZ) 12.3.2 Timer start and stop Timer Z start The Timer TZn is enabled by setting TZnCTL.TZCE to 1. The subsequent write access to register TZnR with non-zero data starts the timer. After that, it is prepared to load the value written to register TZnR into the reload buffer and the counter.
Page 457 Chapter 12 16-bit Interval Timer Z (TMZ) Timer enabled Table 12-5 shows the interval times under following conditions: • timer is enabled by TZnCTL.TZCE = 1 • timer is started by setting TZnR > 0 after at least 2 PCLK2 clock periods after timer enable Table 12-5 TMZ interval times (timer enabled since minimum 2 PCLK2 clocks)
Page 458: Chapter 13 16-Bit Multi-Purpose Timer G (Tmg)
Chapter 13 16-bit Multi-Purpose Timer G (TMG) The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the 16- bit multi-purpose Timer G: All devices Instances Names TMG0 to TMG2 Throughout this chapter, the individual instances of Timer G are identified by “n”, for example TMGn, or TMGMn for the TMGn mode register.
Page 459: Function Overview Of Each Timer Gn
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.2 Function Overview of Each Timer Gn • 16-bit timer/counter (TMGn0, TMGn1): 2 channels • Bit length – Timer Gn registers (TMGn0, TMGn1): 16 bits • Capture/compare register (GCCny): 6 – 16-bit – 2 registers are assigned fix to the corresponding one of the 2 counters –...
Page 460 Chapter 13 16-bit Multi-Purpose Timer G (TMG) SCPLK0 SCPLK0 INTTGnOV0 SCPLK0 COUNT0 SCPLK0 TMGn0 (16-bit) SPCLK0 (16 MHz) Clear SCPLK0 (Note 1) SCPLK0 SCPLK0 INTTGnCC0 /128 SCPLK0 Noise Elimination GCCn0 (16-bit) TIGn0 capture/compare Edge Detection (Note 2) INTTGnCC1 TOGn1 Noise Elimination GCCn1 (16-bit) TIGn1 Edge Detection...
Page 461: Basic Configuration
Chapter 13 16-bit Multi-Purpose Timer G (TMG) Note TMGn0/TMGn1 are cleared by GCCn0/GCCn5 register compare match. TIGn0 differs: – n = 0: TIG00 not connected – n = 1: TIG10 not connected – n = 2: TIG20 available as external capture input TIGn5 differs: –...
Page 462: Tmg Registers
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.4 TMG Registers The Timers Gn are controlled and operated by means of the following registers: Table 13-2 TMGn registers overview Register name Shortcut Address Timer Gn mode register TMGMn <base> Timer Gn channel mode register TMGCMn <base>...
Page 463 Chapter 13 16-bit Multi-Purpose Timer G (TMG) TMGMn - Timer Gn mode register Access This register can be read/written in 16-bit, 8-bit or 1-bit units. The low byte TMGMn.bit[7:0] is accessible separately under the name TMGMnL, the high byte TMGMn.bit[15:8] under the name TMGMnH. Address TMGMn, TMGMnL:<base>...
Page 464 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Table 13-4 TMGMn register contents (2/2) Bit name Function position Specifies the mode of the TMGn0 (TMGn1)(CCSGn5 for TMGn1, CCSGn0 for TMGn0): 0: Free-run mode for TMGn1 (TMGn0), GCCn5 (GCCn0) in capture mode (an detected edge at pin TIGn5 (TIGn0) stores the value of TMGn1 (TMGn0) in GCCn5 (GCCn0) and an interrupt INTCCGn5 (INTCCGn0) is output) 1: Match and Clear mode of the TMGn1 (TMGn0), GCCn5 (GCCn0) in compare...
Page 465 Chapter 13 16-bit Multi-Purpose Timer G (TMG) TMGCMn - Timer Gn channel mode register This register specifies the assigned counter (TMGn0 or TMGn1) for the GCCnm register. Furthermore it specifies the edge detection for the TIGny input pins. Access This register can be read/written in 16-bit, 8-bit or 1-bit units. The low byte TMGCMn.bit[7:0] is accessible separately under the name TMGCMnL, the high byte TMGCMn.bit[15:8] under the name TMGCMnH.
Page 466 Chapter 13 16-bit Multi-Purpose Timer G (TMG) OCTLGn - Timer Gn output control register This register controls the timer output from the TOGnm pin and the capture or compare modus for the GCCnm register. Access This register can be read/written in 16-bit, 8-bit or 1-bit units. The low byte OCTLGn.bit[7:0] is accessible separately under the name OCTLGnL, the high byte OCTLGn.bit[15:8] under the name OCTLGnH.
Page 467 Chapter 13 16-bit Multi-Purpose Timer G (TMG) TMGSTn - Time base status register The TMGSTn register indicates the status of TMGn0 and TMGn1. For the CCFGny bit see “Operation in Free-Run Mode“ on page 473. Access This register can be read in 8-bit or 1-bit units. Address <base>...
Page 468 Chapter 13 16-bit Multi-Purpose Timer G (TMG) GCCn0, GCCn5 - Timer Gn capture/compare registers of the 2 counters The GCCn0, GCCn5 registers are 16-bit capture/compare registers of Timer Gn. These registers are fixed assigned to the counter registers: • GCCn0 is fixed assigned to timebase TMGn0 •...
Page 469 Chapter 13 16-bit Multi-Purpose Timer G (TMG) GCCn1 to GCCn4 - Timer G capture/compare registers with external PWW-output function The GCCn1 to GCCn4 registers are 16-bit capture/compare registers of Timer Gn. They can be assigned to one of the two counters either TMGn0 or TMGn1. Capture mode In the capture register mode, these registers capture the value of TMGn0 when the TBGnm bit (m = 1 to 4) of the TMGCMnH register = 0.
Page 470: Output Delay Operation
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.5 Output Delay Operation When the OLDEn bit is set, different delays of count clock period are added to the TOGnm pins: Delay Output pin COUNT TOGn1 TOGn2 TOGn3 TOGn4 The figure below shows the timing for the case where the count clock is set to /2.
Page 471: Explanation Of Basic Operation
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.6 Explanation of Basic Operation Overview of the mode settings The Timer Gn includes 2 channels of 16-bit counters (TMGn0/TMGn1), which can operate as independently timebases. TMGn0 (TMGn1) can be set by CCSGn0 bit (CCSGn5 bit) in the following modes: •...
Page 472 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Table 13-9 Interrupt output and timer output states dependent on the register setting values Register setting value State of each output pin CCSGn5 TBGnm SWFGnm CCSGnm INTTMGn1 INTCCGn5 INTCCGnm TOGnm TIm edge detection Tied to inactive GCCnm match level...
Page 473: Operation In Free-Run Mode
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.7 Operation in Free-Run Mode This operation mode is the standard mode for Timer Gn operations. In this mode the 2 counter TMGn0 and TMGn1 are counting up from 0000H to FFFFH, generates an overflow and start again. In the match and clear mode, which is described in Chapter 13.8 on page 483 the fixed assigned register GCCn0 (GCCn5) is used to reduce the bit-size of the counter TMGn0 (TMGn1).
Page 474 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Using CCFGny: When using GCCny as a capture register, use the procedure below. <1> After INTCCGny (edge detection interrupt) generation, read the corresponding GCCny register. <2> Check if the corresponding CCFGny bit of the TMGSTn register is set. <3>...
Page 475 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (b) Timing of capture trigger edge detection The Tin inputs are fitted with an edge-detection and noise-elimination circuit. Because of this circuit, 3 periods to less than 4 periods of the count clock are required from edge input until an interrupt signal is output and capture operation is performed.
Page 476 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (c) Timing of starting capture trigger edge detection A capture trigger input signal (TIGny) is synchronized in the noise eliminator for internal use. Edge detection starts when 1 count clock period (f ) has been input after COUNT timer count operation starts.
Page 477 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Compare operation (free run) Basic settings (m = 1 to 4): Value Remark CCSGn0 free run mode CCSGn5 SWFGnm disable TOGnm Compare mode for CCSGnm GCCnm assign counter for GCCnm TBGnm 0: TMGn0 1: TMGn1 (a) Example: Interval timer (free run) Setting method interval timer:...
Page 478 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (b) When the value 0000H is set in GCCnm INTCCGnm is activated when the value of the counter becomes 0001H. INTTMGn0/INTTMGn1 is activated when the value of the counter changes from FFFFH to 0000H. Note, however, that even if no data is set in GCCnm, INTCCGnm is activated immediately after the counter starts.
Page 479 Chapter 13 16-bit Multi-Purpose Timer G (TMG) PWM output (free run) Basic settings (m = 1 to 4): Value Remark CCSGn0 free run mode CCSGn5 Note SWFGnm enable TOGnm Compare mode for Note CCSGnm GCCnm assign counter for GCCnm TBGnm 0: TMGn0 1: TMGn1 Note...
Page 480 Chapter 13 16-bit Multi-Purpose Timer G (TMG) ENFG0 FFFFH FFFFH FFFFH Ma tch TM G n0 GCCn1 INTTGnCC1 INTTGnOV0 TOGn1 (ALVG1=1) TOGn1 (ALVG1=0) Figure 13-8 Timing of PWM operation (free run) Data N is set in GCCn1, counter TMGn0 is selected. (a) When 0000H is set in GCCnm (m = 1 to 4) When 0000H is set in GCCnm, TOGnm is tied to the inactive level.
Page 481 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (b) When FFFFH is set in GCCnm (m = 1 to 4) When FFFFH is set in GCCnm, TOGnm outputs the inactive level for one clock period immediately after each counter overflow (except the first overflow). The figure shows the state of TOGn1 when FFFFH is set in GCCn1, and TMGn0 is selected.
Page 482 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (c) When GCCnm is rewritten during operation (m = 1 to 4) When GCCn1 is rewritten from 5555H to AAAAH, the operation shown below is performed. The figure below shows a case where TMGn0 is selected for GCCn1. ENFG0 FFFFH FFFFH...
Page 483: Match And Clear Mode
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.8 Match and Clear Mode The match and clear mode is mainly used reduce the number of valid bits of the counters (TMGn0, TMGn1). Therefore the fixed assigned register GCCn0 (GCCn1) is used to compare its value with the counter TMGn0 (TMGn1).
Page 484 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (b) Example: Capture where both edges of TIGnm are valid (match and clear) For the timing chart TMGn0 is selected as the counter corresponding to TOGn1, and 0FFFH is set in GCCn0. COUNTx 0000H 0001H 0FF F H 0000H TMGn0...
Page 485 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Compare operation (match and clear) Basic settings (m = 1 to 4): Value Remark CCSGn0 match and clear mode CCSGn5 SWFGnm disable TOGnm Compare mode for CCSGnm GCCnm assign counter for GCCnm TBGnm 0: TMGn0 1: TMGn1 (a) Example: Interval timer (match and clear)
Page 486 Chapter 13 16-bit Multi-Purpose Timer G (TMG) ENFG0 0FFFH 0FFFH 0FFFH Ma tch TM G n0 GCCn1 INTTGnCC1 INTTGnCC0 Figure 13-13 Timing of compare operation (match and clear) In this example, the data N is set in GCCn1, and TMGn0 is selected. 0FFFH is set in GCCn0.
Page 487 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (f) When GCCnm (m = 1 to 4) is rewritten during operation (match and clear) When the value of GCCn1 is changed from 0555H to 0AAAH, the operation described below is performed. TMGn0 is selected as the counter, and 0FFFH is set in GCCn0. ENFG0 Ma tch Ma tch...
Page 488 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Setting Method: (1) An usable compare register is one of GCCn1 to GCCn4, and the corresponding counters TMGn0 or TMGn1 must be selected with the TBGnm bit (m = 1 to 4). (2) Select a count clock cycle with the CSE12 to CSE10 (TMGn1) bits or CSE02 to CSE00 (TMGn0) bits.
Page 489 Chapter 13 16-bit Multi-Purpose Timer G (TMG) Example Data N is set, and the counter TMGn0 is selected. 0FFFH is set in GCCn0 and N < 0FFFH. ENFG0 0FFFH 0FFFH 0FFFH Ma tch TM G n0 GCCn1 INTTGnCC1 INTTGnCC0 TOGn1(ALVG1=1) TOGn1(ALVG1=0) Figure 13-15 Timing of PWM operation (match and clear)
Page 490 Chapter 13 16-bit Multi-Purpose Timer G (TMG) ENFG0 0FFFH 0FFFH 0FFFH Ma tch TM G n0 GCCn1 0000H INTTGnCC1 INTGnCC0 TOGn1(ALVG1=1) TOGn1(ALVG1=0) High Figure 13-16 Timing when 0000H is set in GCCnm (match and clear) (c) When the same value as set in GCCn0 or GCCn5 is set in GCCnm (match and clear) When the same value as set in GCCn0 (GCCn5) is set in GCCnm, TOGnm outputs the inactive level for only one clock period immediately after each...
Page 491 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (d) When a value exceeding the value set in GCCn0 or GCCn5 is set in GCCnm (match and clear) When a value exceeding the value set in GCCn0 (GCCn5) is set in GCCnm, TOGnm starts and continues outputting the active level immediately after the first match and clear event (until count operation stops.) The figure shows the state of TOGn1 when 0FFFH is set in GCCn0, 1FFFH is...
Page 492 Chapter 13 16-bit Multi-Purpose Timer G (TMG) (e) When GCCnm is rewritten during operation (match and clear) When GCCn1 is rewritten from 0555H to 0AAAH, the operation shown below is performed. The figure below shows a case where 0FFFH is set in GCCn0, and TMGn0 is selected for GCCn1.
Page 493: Edge Noise Elimination
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.9 Edge Noise Elimination The edge detection circuit has a noise elimination function. This function regards: • a pulse not wider than 1 count clock period as a noise, and does not detect it as an edge. •...
Page 494: Precautions Timer Gn
Chapter 13 16-bit Multi-Purpose Timer G (TMG) 13.10 Precautions Timer Gn When POWERn bit of TMGMHn register is set The rewriting of the CSEn2 to CSEn0 bits of TMGMHn register is prohibited. These bits set the prescaler for the Timer Gn counter. The rewriting of the CCSGny bits (y = 0 to 5) is prohibited.
Page 495 Chapter 13 16-bit Multi-Purpose Timer G (TMG) If two or more overflows of TMGn0 or TMGn1 occur between captures, a software-based measure needs to be taken to count overflow interrupts (INTTMGn0 or INTTMGn1). If only one overflow is necessary, the CCFGny bits (y = 0 to 5) can be used for overflow detection.
Page 496: Chapter 14 16-Bit Timer Y (Tmy)
Chapter 14 16-bit Timer Y (TMY) Timer Y (TMY) is a two-stage 16-bit timer/counter. The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the two-stage 16-bit timer/counter TMY: All devices Instances Names TMY0 Throughout this chapter, the individual instances of TMY are identified by “n”, for example, TMYn, or TYnCTL for the TMYn control register.
Page 497: Description
Chapter 14 16-bit Timer Y (TMY) 14.1.1 Description The TMY is built up as illustrated below. Internal bus TYnIOC TYnCTL TYnR0 TYOL TYCKS12 TYCKS11 TYCKS10 TYCKS02 TYCKS01 TYCKS00 TYnCNT01 TYnCNT00 Reload buffer Reload INTTYnUV0 TYnCTL.TYCE SPCLK1 (8 MHz) Clear 16-bit down counter SPCLK3 (2 MHz) TYnCNT0 TYnCTL.TYCE...
Page 498: Principle Of Operation
Chapter 14 16-bit Timer Y (TMY) 14.1.2 Principle of Operation When TMYn is enabled, the down-counter 0 starts counting as soon as a non- zero value is written to the reload register TYnR0 and copied to the associated reload buffer. When counter 0 reaches zero, it generates the maskable interrupt INTTYnUV0, reloads its start value from its reload buffer, and starts counter 1.
Page 499 Chapter 14 16-bit Timer Y (TMY) TYnCTL - TMYn timer control register The 8-bit TYnCTL register controls the operation of the Timer Y. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + D Initial Value .
Page 500 Chapter 14 16-bit Timer Y (TMY) TYnIOC - TMYn I/O control register The TYnIOC register is an 8-bit register that controls the polarity of the timer output signal. Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 501 Chapter 14 16-bit Timer Y (TMY) TYnCNTm1 - TMYn non-synchronized counter registers The TYnCNTm1 register is the non-synchronized read register that can be used to read the present value of the concerned 16-bit counter m. Note m = 0 identifies counter 0; m = 1 identifies counter 1. “Non-synchronized”...
Page 502 Chapter 14 16-bit Timer Y (TMY) TYnRm - TMYn reload registers The TYnRm registers are two 16-bit registers for setting the reload value of the corresponding counters. Note m = 0 identifies counter 0; m = 1 identifies counter 1. Access These registers can be read/written in 16-bit units.
Page 503: Timing
Chapter 14 16-bit Timer Y (TMY) 14.3 Timing You can change the contents of the reload registers TYnRm at any time, provided TYnCTL.TYnCE is 1. However, the counters reload their start values when it reaches 0. The following figure illustrates the timer operation. TYnCNT0 0000H Underflow...
Page 504: Output Timing Calculations
Chapter 14 16-bit Timer Y (TMY) 14.4 Output Timing Calculations This section provides information on how to calculate the output pulse duration under various conditions. Caution When specifying SPCLK3, SPLCK4, SPCLK5 or SPCLK6 as the count clock, a jitter of maximum ± 1 period of SPCLK1 may be applied to the TYnCNT0 and TYnCNT1 counter’s count clock input.
Page 505 Chapter 14 16-bit Timer Y (TMY) Total PWM interval length is the time between two interrupts INTTZnUV0 (or INTTZnUV1). If both counters use the same clock ([TYnCKS0] = [TYnCKS1]): • First interval: – (([TYnR0] + [TYnR1]) × 2 ≤ T [TYnCKS0] ) x 1/f SPCLK1...
Page 506 Chapter 14 16-bit Timer Y (TMY) • All following intervals: = (([TYnR0] + 1) × 2 [TYnCKS0] – T ) x 1/f PWM10 SPCLK1 If both counters use different clocks: – ([TYnR0] × 2 [TYnCKS0] ≤ T + 1) x 1/f SPCLK1 PWM10 ≤...
Page 507: Chapter 15 Watch Timer (Wt)
Chapter 15 Watch Timer (WT) The Watch Timer (WT) generates interrupts at regular time intervals. These interrupts are generally used as ticks for updating the internal daytime and calendar. The Watch Timer includes two identical counters. Throughout this chapter, the counters are identified as WTn, where n = 0 to 1.
Page 508 Chapter 15 Watch Timer (WT) Features summary Special features of the Watch Timer are: • Periodic interrupts (clock ticks) generated by two down-counters • Two reload registers, one for each counter • Choice of oscillators to reduce power consumption in stand-by mode •...
Page 509: Description
Chapter 15 Watch Timer (WT) 15.1.1 Description The following figure shows the structure of the Watch Timer and its connection to the Watch Calibration Timer. Internal bus at c WT0R WT1R imer WT0CNT1 WT0CNT0 Reload buffer WT1CNT1 WT1CNT0 Reload buffer Reload Reload 16-bit down-counter...
Page 510: Principle Of Operation
Chapter 15 Watch Timer (WT) 15.1.2 Principle of operation In order to generate an interrupt every one or two seconds, WTCLK is usually set to a frequency around 30 KHz. Then, a load value around 2 will yield a running time of about 1 s. Operation control of WT0 The source and frequency of WTCLK are specified in the Clock Generator register TCC.
Page 511 Chapter 15 Watch Timer (WT) Operation of WCT The third counter WCT is used for clock correction. This counter is connected to PCLK1 (8 MHz) or directly to the 4 MHz main oscillator. It is used to measure the time between two INTWT0UV requests. For this measurement, WCT is configured as a capture timer.
Page 512: Watch Timer Registers
Chapter 15 Watch Timer (WT) 15.2 Watch Timer Registers The Watch Timer counters WT0 and WT1 are controlled and operated by means of the following registers: Table 15-2 WTn registers overview Register name Shortcut Address Watch timer synchronized read register WTnCNT0 <base>...
Page 513 Chapter 15 Watch Timer (WT) WTnCNT0 - WTn synchronized counter register The WTnCNT0 register is the synchronized register that can be used to read the present value of the 16-bit counter. “Synchronized” means that the read access via the internal bus is synchronized with the counter clock.
Page 514 Chapter 15 Watch Timer (WT) WTnCNT1 - WTn non-synchronized counter read register The WTnCNT1 register is the non-synchronized register that can be used to read the present value of the corresponding 16-bit counter. “Non-synchronized” means that the read access via the internal bus is not synchronized with the counter clock.
Page 515 Chapter 15 Watch Timer (WT) WTnR - WTn reload register The WTnR register is a dedicated register for setting the reload value of the corresponding counter. Access This register can be read/written in 16-bit units. Address <base> + 4 Initial Value 0000 .
Page 516: Watch Timer Operation
Chapter 15 Watch Timer (WT) 15.3 Watch Timer Operation This section describes the operation of the Watch Timer counters in detail. 15.3.1 Timing of steady operation The contents of the reload registers WTnR can be changed at any time, provided the corresponding counter is enabled. The contents is then copied to the reload buffer.
Page 517: Watch Timer Start-Up
Chapter 15 Watch Timer (WT) 15.3.2 Watch Timer start-up The first interval after starting WT0 and WT1 until their first underflow takes at least four additional input clock cycles. At this point in time, the values of the counter registers WTnCNT are not correct. After the first automatic reload of the WTnR value, the counter registers WTnCNT hold the correct number of clock cycles since the last underflow.
Page 518 Chapter 15 Watch Timer (WT) As a consequence, register WT1CNT does not show the correct number of INTWT0UV events after WT1R > 0, but a value of four less: – 1 INTWT0UV cycle 4 –> 5 taken for the cycle WT1R is written –...
Page 519: Watch Calibration Timer Registers
Chapter 15 Watch Timer (WT) 15.4 Watch Calibration Timer Registers The Watch Calibration Timer is controlled by means of the following registers: Table 15-5 WCT registers overview Register name Shortcut Address WCT timer / counter read register TM00 <base> WCT capture / compare register CR001 <base>...
Page 520 Chapter 15 Watch Timer (WT) TMC00 - WCT mode control register The 8-bit TMC00 register controls the operation of the WCT. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 6 Initial Value . This register is cleared by any reset. TMC003 TMC002 OVF00...
Page 521 Chapter 15 Watch Timer (WT) PRM00 - WCT prescaler mode register The 8-bit PRM00 register is used to select the “valid edge” of INTWT0UV for interval measurements. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 7 Initial Value .
Page 522 Chapter 15 Watch Timer (WT) CRC00 - WCT capture / compare control register The 8-bit CRC00 register controls the operation of the capture/compare register CR001. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 8 Initial Value .
Page 523 Chapter 15 Watch Timer (WT) CR001 - WCT capture / compare register 1 The 16-bit CR001 register can be used as a capture register or as a compare register. Whether it is used as a capture register or compare register is specified in bit CRC00.CRC002.
Page 524 Chapter 15 Watch Timer (WT) If the counter overflows, it sets the flag TMC00.OVF00 to 1 and continues with 0000 R01UH0129ED0701 Rev. 7.01 User Manual...
Page 525: Watch Calibration Timer Operation
Chapter 15 Watch Timer (WT) 15.5 Watch Calibration Timer Operation The Watch Calibration Timer WCT is used to measure the time between two successive occurrences of the Watch Timer WT0 underflow interrupt INTWT0UV. The WCT is supplied with the stable clock WCTCLK: •...
Page 526 Chapter 15 Watch Timer (WT) As shown in the figure, the interrupt INTTM01 can be used as a trigger for reading the register CR001. The interval duration must be calculated from the difference between the present and the previous value of CR001. Note If TM00 overflows between two occurrences of INTWT0UV, that means between two capture triggers, the overflow flag TMC00.OVF00 is set.
Page 527: Chapter 16 Watchdog Timer (Wdt)
Chapter 16 Watchdog Timer (WDT) The Watchdog Timer is used to escape from a system deadlock or program runaway. If it is not restarted within a certain time, the Watchdog Timer flows over and interrupts or even resets the microcontroller. 16.1 Overview The Watchdog Timer contains an up-counter that is driven by the Watchdog Timer clock WDTCLK.
Page 528: Principle Of Operation
Chapter 16 Watchdog Timer (WDT) As shown in the figure, the WDCS register controls the running time and the WDTM register the operating mode. The running time can be chosen between 2 and 2 times the period of the Watchdog Timer clock WDTCLK. The figure shows also, that the run and mode settings of the WDTM register are only cleared by SYSRESWDT.
Page 529: Reset Behavior
Chapter 16 Watchdog Timer (WDT) In this register, it is possible to choose the main, sub, or internal oscillator as the clock source (WCC.SOSCW, WCC.WDTSEL0). You can also choose a suitable frequency divider between 1 and 128 (WCC.WPS[2:0]). WDTCLK is subject to a stand-by mode control. WDTCLK can optionally be stopped in IDLE, WATCH, Sub-WATCH and STOP mode (WCC.WDTSEL1).
Page 530: Watchdog Timer Registers
Chapter 16 Watchdog Timer (WDT) 16.2 Watchdog Timer Registers The Watchdog Timer is controlled by means of the following registers: Table 16-1 Watchdog Timer registers overview Register name Shortcut Address Watchdog Timer clock selection register WDCS <base> Watchdog Timer command protection register WCMD <base>...
Page 531 Chapter 16 Watchdog Timer (WDT) WDCS - WDT clock selection register The 8-bit WDCS register is used to specify the running time of the Watchdog Timer. Access This register can be read/written in 8-bit or 1-bit units. Writing to this register is protected by a special sequence of instructions. Please refer to “WCMD - WDT command protection register“...
Page 532 Chapter 16 Watchdog Timer (WDT) These are just two examples for WDTCLK. The actual clock signal depends on the clock divider settings and the external oscillator resonators. Note Every reset sets the WDCS register to 07 , which means the longest time interval.
Page 533 Chapter 16 Watchdog Timer (WDT) WDTM - WDT mode register This register sets the operating mode of the Watchdog Timer and enables or disables counting. When the Watchdog Timer is running and shall not overflow, it is necessary to write to WDTM before the specified running time has elapsed. Access This register can be read/written in 8-bit units.
Page 534 Chapter 16 Watchdog Timer (WDT) WCMD - WDT command protection register The 8-bit WCMD register is write-only. It is used to protect the WDTM and WDCS registers from unintended writing. Access This register can be written in 8-bit units. Address <base>...
Page 535 Chapter 16 Watchdog Timer (WDT) WPHS - WDT command status register The WPHS register monitors the success of a write instruction to the WDTM and WDCS registers. If the write operation to WDTM or WDCS failed because WCMD was not written immediately before writing to WDTM or WDCS, the WPRERR flag is set.
Page 536: Chapter 17 Asynchronous Serial Interface (Uarta)
Chapter 17 Asynchronous Serial Interface (UARTA) The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the universal Asynchronous Serial Interface UARTA: UARTA All devices Instances Names UARTA0 to UARTA1 Throughout this chapter, the individual instances of UARTA are identified by “n”, for example, UARTAn, or UAnCTL0 for the UARTAn control register 0.
Page 537: Configuration
Chapter 17 Asynchronous Serial Interface (UARTA) • 13 to 20 bits selectable for the SBF (Sync Break Field) in the LIN (Local Interconnect Network) communication format – Recognition of 11 bits or more possible for SBF reception in LIN communication format –...
Page 538 Chapter 17 Asynchronous Serial Interface (UARTA) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn.
Page 539: Uarta Registers
Chapter 17 Asynchronous Serial Interface (UARTA) UARTAn transmit data register (UAnTX) The UAnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the UAnTX register. When data can be written to the UAnTX register (when data of one frame is transferred from the UAnTX register to the UARTAn transmit shift register), the transmission enable interrupt request signal (INTUAnT) is generated.
Page 540 Chapter 17 Asynchronous Serial Interface (UARTA) UAnCTL0 - UARTAn control register 0 The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. Access This register can be read/written in 8-bit or 1-bit units. Address <base> Initial Value .
Page 541 Chapter 17 Asynchronous Serial Interface (UARTA) Table 17-3 UAnCTL0 register contents (2/2) Bit position Bit name Function 3, 2 UAnPS[1:0] Parity selection Parity selection during UAnPS1 UAnPS0 transmission reception No parity output Reception with no parity 0 parity output Reception with 0 parity Odd parity output Odd parity check Even parity output Even parity check...
Page 542 Chapter 17 Asynchronous Serial Interface (UARTA) UAnOPT0 - UARTAn option control register 0 The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register. Access This register can be read/written in 8-bit or 1-bit units. Address <base>...
Page 543 Chapter 17 Asynchronous Serial Interface (UARTA) Table 17-4 UAnOPT0 register contents (2/2) Bit position Bit name Function UAnTDL Transmit data level bit 0: Normal output of transfer data 1: Inverted output of transfer data • The output level of the TXDAn pin can be inverted using the UAnTDL bit. •...
Page 544 Chapter 17 Asynchronous Serial Interface (UARTA) Table 17-5 UAnSTR register contents Bit position Bit name Function UAnTSF Transfer status flag: 0: – When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set. – When, following transfer completion, there was no next data transfer from UAnTX register 1: Write to UAnTXB bit...
Page 545 Chapter 17 Asynchronous Serial Interface (UARTA) UAnRX - UARTAn receive data register The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
Page 546: Interrupt Request Signals
Chapter 17 Asynchronous Serial Interface (UARTA) 17.4 Interrupt Request Signals The following three interrupt request signals are generated from UARTAn: • Reception complete interrupt request signal (INTUAnR) • Receive error interrupt request signal (INTUAnRE) • Transmission enable interrupt request signal (INTUAnT) Reception complete interrupt request signal (INTUAnR) A reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the UAnRX register in the reception...
Page 547: Operation
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5 Operation 17.5.1 Data format Full-duplex serial data reception and transmission is performed. As shown in the figures below, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of MSB/LSB-first transfer are performed using the UAnCTL0 register.
Page 548 Chapter 17 Asynchronous Serial Interface (UARTA) (c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDAn inversion 1 data frame Start Parity Stop (d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H 1 data frame Start Parity...
Page 549: Sbf Transmission/Reception Format
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5.2 SBF transmission/reception format The UARTA has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. About LIN LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial co mmunication protocol intended to aid the cost reduction of an automotive network.
Page 550 Chapter 17 Asynchronous Serial Interface (UARTA) A transmission enable interrupt request signal (INTUAnT) is output at the start of each transmission. The INTUAnT signal is also output at the start of each SBF transmission. Wake-up Synch Check signal break Synch Ident DATA DATA...
Page 551: Sbf Transmission
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSBL2 to UAnOPT0.UAnSBL0 bits is output.
Page 552 Chapter 17 Asynchronous Serial Interface (UARTA) (a) Normal SBF reception (detection of stop bit in more than 10.5 bits) 11.5 UAnSRF INTUAnR interrupt (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) 10.5 UA0SRF INTUAnR interrupt R01UH0129ED0701 Rev.
Page 553: Uart Transmission
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 554: Continuous Transmission Procedure
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 555 Chapter 17 Asynchronous Serial Interface (UARTA) Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn UAnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUAnT UAnTSF Figure 17-6 Continuous transmission operation timing —transmission start Stop UATTXD Parity...
Page 556: Uart Reception
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine.
Page 557: Reception Errors
Chapter 17 Asynchronous Serial Interface (UARTA) If receive completion processing (INTUAnR signal generation) of UARTAn and the UAnPWR bit = 0 or UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these being no data stored in the UAnRX register.
Page 558: Parity Types And Operations
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5.9 Parity types and operations Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 559: Receive Data Noise Filter
Chapter 17 Asynchronous Serial Interface (UARTA) 17.5.10 Receive data noise filter This filter samples the RXDAn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see Figure 17-10).
Page 560: Baud Rate Generator
Chapter 17 Asynchronous Serial Interface (UARTA) 17.6 Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 561: Baud Rate Generator Registers
Chapter 17 Asynchronous Serial Interface (UARTA) 17.6.2 Baud Rate Generator registers UAnCTL1 - UARTAn control register 1 The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. Access This register can be read or written in 8-bit units. Address <base>...
Page 562 Chapter 17 Asynchronous Serial Interface (UARTA) UAnCTL2 - UARTAn control register 2 The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. Access This register can be read or written in 8-bit units. Address <base>...
Page 563: Baud Rate Calculation
Chapter 17 Asynchronous Serial Interface (UARTA) 17.6.3 Baud rate calculation The baud rate is obtained by the following equation. UCLK Baud rate -------------- - [bps] × = Frequency of base clock selected by the UAnCTL1.UAnCKS[2:0] UCLK Value set using the UAnCTL2.UAnBRS[7:0] bits (k = 4, 5, 6, …, 255) 17.6.4 Baud rate error The baud rate error is obtained by the following equation.
Page 564: Allowable Baud Rate Range During Reception
Chapter 17 Asynchronous Serial Interface (UARTA) Table 17-9 Baud rate generator setting data (2/2) 38,400 38,461.54 0.16 76,800 76,923.08 0.16 153,600 153,846.15 0.16 312,500 307,692.31 –1.54 Note Table 17-9 assumes normal operation mode, i.e. PCLK1 = 8 MHz. 17.6.6 Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below.
Page 565 Chapter 17 Asynchronous Serial Interface (UARTA) When this is applied to 11-bit reception, the following is the theoretical result. FL = (Brate) Brate: UARTAn baud rate Setting value of UAnCTL2.UAnBRS[7:0] 1-bit data length Latch timing margin: 2 clocks Minimum allowable transfer rate: –...
Page 566: Baud Rate During Continuous Transmission
Chapter 17 Asynchronous Serial Interface (UARTA) 17.6.7 Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 567: Cautions
Chapter 17 Asynchronous Serial Interface (UARTA) 17.7 Cautions 17.7.1 UARTAn behaviour during and after power save mode When the clock supply to UARTAn is stopped (for example, in IDLE or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped.
Page 568: Uartan Operation Stop
Chapter 17 Asynchronous Serial Interface (UARTA) DMA transmission If the DMA controller is used to write transmission data to the UAnTX register, the DMA controller continues to do so in debugger break-mode. If the specified number of data units in the DBCn register has been transferred to the UARTAn the DCHCn.TCn is set and the DMA completion interrupt INTDMAn is generated.
Page 569: Chapter 18 Clocked Serial Interface (Csib)
Chapter 18 Clocked Serial Interface (CSIB) The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the clocked serial interface CSIB: µPD70F3427, µPD70F3426A, µPD70F3423, µPD70F3422, CSIB µPD70F3425, µPD70F3424 µPD70F3421 Instances Names CSIB0 to CSIB2 CSIB0 to CSIB1 Throughout this chapter, the individual instances of clocked serial interface are identified by “n”, for example CSIBn, or CBnCTL0 for the control register 0 of CSIBn.
Page 570: Configuration
Chapter 18 Clocked Serial Interface (CSIB) 18.2 Configuration The following shows the block diagram of CSIBn. Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR SPCLK1 (8 MHz) BRGn INTCBnT Controller INTCBnR INTCBnRE Note PCLK1 (8 MHz) PCLK2 (4 MHz) PCLK3 (2 MHz) Phase control PCLK4 (1 MHz) PCLK5 (500 KHz)
Page 571: Csib Control Registers
Chapter 18 Clocked Serial Interface (CSIB) 18.3 CSIB Control Registers The clocked serial interfaces CSIBn are controlled and operated by means of the following registers: Table 18-1 CSIBn registers overview Register name Shortcut Address CSIBn control register 0 CBnCTL0 <base> CSIBn control register 1 CBnCTL1 <base>...
Page 572 Chapter 18 Clocked Serial Interface (CSIB) CBnCTL0 - CSIBn control register 0 CBnCTL0 is a register that controls the CSIBn serial transfer operation. Access This register can be read/written in 8-bit or 1-bit units. Address <base> Initial Value . This register is cleared by any reset. CBnPWR CBnTXE CBnRXE CBnDIR...
Page 573 Chapter 18 Clocked Serial Interface (CSIB) Table 18-3 CBnCTL0 register contents (2/2) Bit position Bit name Function CBnDIR Transfer direction mode specification (MSB/LSB): 0: MSB first transfer 1: LSB first transfer CBnTMS Transfer mode specification (MSB/LSB): 0: Single transfer mode 1: Continuous transfer mode CBnSCE Specification of start transfer disable/enable:...
Page 574 Chapter 18 Clocked Serial Interface (CSIB) CBnCTL1 - CSIBn control register 1 CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 1 Initial Value .
Page 575 Chapter 18 Clocked Serial Interface (CSIB) Table 18-5 Specification of data transmission/reception timing in relation to SCKBn Communication type CBnCKP CBnDAP SIBn/SOBN timing in relation to SCKBn Communication type 1 SCKBn (I/O) SOBn (output) SIBn capture Communication type 2 SCKBn (I/O) SOBn (output)
Page 576 Chapter 18 Clocked Serial Interface (CSIB) CBnCTL2 - CSIBn control register 2 CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. Access This register can be read/written in 8-bit units. Address <base> + 2 Initial Value .
Page 577 Chapter 18 Clocked Serial Interface (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 578 Chapter 18 Clocked Serial Interface (CSIB) CBnSTR - CSIBn status register CBnSTR is an 8-bit register that displays the CSIBn status. Access This register can be read/written in 8-bit or 1-bit units. Bit CBnTSF is read-only. Address <base> + 3 Initial Value .
Page 579 Chapter 18 Clocked Serial Interface (CSIB) CBnRX - CSIBn receive data register The CBnRX register is a 16-bit buffer register that holds receive data. Access This register can be read-only in 16-bit units. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register.
Page 580: Operation
Chapter 18 Clocked Serial Interface (CSIB) 18.4 Operation 18.4.1 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2) CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX write (55H) CBnRX read (AAH) SCKBn...
Page 581 Chapter 18 Clocked Serial Interface (CSIB) In transmission mode or transmission/reception mode, communication is not started by reading the CBnRX register. Note In single transmission or single transmission/reception mode, the INTCBnT signal is not generated. When communication is complete, the INTCBnR signal is generated.
Page 582: Single Transfer Mode (Master Mode, Reception Mode)
Chapter 18 Clocked Serial Interface (CSIB) 18.4.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2) CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX write (55H) CBnRX read (AAH) SCKBn...
Page 583: Continuous Mode (Master Mode, Transmission/Reception Mode)
Chapter 18 Clocked Serial Interface (CSIB) 18.4.3 Continuous mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 3 (see 16.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX SCKBn SOBn...
Page 584: Continuous Mode (Master Mode, Reception Mode)
Chapter 18 Clocked Serial Interface (CSIB) (7) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception).
Page 585: Continuous Reception Mode (Error)
Chapter 18 Clocked Serial Interface (CSIB) (6) The reception complete interrupt request signal (INTCBnR) is output. Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0. (7) Set the CBnCTL0.CBnSCE bit = 0 while the last data being received to set the final receive data status.
Page 586 Chapter 18 Clocked Serial Interface (CSIB) (6) The reception complete interrupt request signal (INTCBnR) is output. (7) If the data could not be read before the end of the next transfer, the CBnSTR.CBnOVE flag is set to 1 upon the end of reception and the reception error interrupt INTCBnRE is output.
Page 587: Continuous Mode (Slave Mode, Transmission/Reception Mode)
Chapter 18 Clocked Serial Interface (CSIB) 18.4.6 Continuous mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 2 (see 16.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CSnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) CBnTX SCKBn SOBn...
Page 588 Chapter 18 Clocked Serial Interface (CSIB) (8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn (end of transmission/reception). To continue transfer, repeat steps (5) to (7) before (8). Note In order to start the entire data transfer the CBnTX register has to be written initially, as done in step (5) above.
Page 589: Continuous Mode (Slave Mode, Reception Mode)
Chapter 18 Clocked Serial Interface (CSIB) 18.4.7 Continuous mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 16.4 (2) CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0, 0, 0) SCKBn SIBn INTCBnR...
Page 590: Clock Timing
Chapter 18 Clocked Serial Interface (CSIB) 18.4.8 Clock timing SCKBn SIBn capture SOBn Reg-R/W Note 1 INTCBnT Note 2 INTCBnR CBnTSF Figure 18-5 (i) Communication type 1 (CBnCKP = 0, CBnDAP = 0) SCKBn SIBn capture SOBn Reg-R/W Note 1 INTCBnT INTCBnR Note 2...
Page 591 Chapter 18 Clocked Serial Interface (CSIB) SCKBn SIBn capture SOBn Reg-R/W Note 1 INTCBnT INTCBnR Note 2 CBnTSF Figure 18-8 (iv) Communication type 4 (CBnCKP = 1, CBnDAP = 1) Note The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes.
Page 592: Output Pins
Chapter 18 Clocked Serial Interface (CSIB) 18.5 Output Pins SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn pin output Don’t care Don’t care Don’t care Fixed to high level High impedance Other than above...
Page 593: Operation Flow
Chapter 18 Clocked Serial Interface (CSIB) 18.6 Operation Flow Single transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR generated? Transfer data exists? CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting. Caution In the slave mode, data cannot be correctly transmitted if the next transfer clock is input earlier than the CBnTX register is written.
Page 594 Chapter 18 Clocked Serial Interface (CSIB) Single reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnR generated? Last data? CBnRX register read CBnSCE bit = 0 (CBnCTL0) CBnRX register read CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 595 Chapter 18 Clocked Serial Interface (CSIB) Single transmission/reception START Note 1 Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnR generated? Transmission/reception Reception Transmission Read CBnRX register. Read CBnRX register. Transfer end? Transfer end? Transfer end? Note 2 Note 2 Note 2 Write CBnTX register...
Page 596 Chapter 18 Clocked Serial Interface (CSIB) Continuous transmission START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register (start transfer). INTCBnT generated? Exists data to be transferred next? CBnTSF bit = 0? (CBnSTR) CBnPWR bit = 0 (CBnCTL0) Note Set the CBnSCE bit to 1 in the initial setting.
Page 597 Chapter 18 Clocked Serial Interface (CSIB) Continuous reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) CBnRX register dummy read (start reception) INTCBnRE generated? CBnRX register read INTCBnR generated? Is data being CBnSCE bit = 0 received last data? (CBnCTL0) CBnRX register read CBnSCE bit = 0 (CBnCTL0)
Page 598 Chapter 18 Clocked Serial Interface (CSIB) Continuous transmission/reception START Note Initial setting (CBnCTL0 CBnCTL1 registers, etc.) Write CBnTX register. INTCBnT generated? Last data transferred? Write CBnTX register. INTCBnR generated? CBnRX register read INTCBnRE generated? Data received completely? CBnRX register read CBnOVE bit clear (CBnSTR) Note...
Page 599: Baud Rate Generator
Chapter 18 Clocked Serial Interface (CSIB) 18.7 Baud Rate Generator 18.7.1 Overview Each CSIBn interface is equipped with a dedicated baud rate generator. Selector SPCLK1 8-bit timer counter (1, 1/2, 1/4, 1/8) Match detector BRGnOUT BGnCS1, BGnCS0 PRSCMn 18.7.2 Baud Rate Generator registers The Baud Rate Generators BRGn are controlled and operated by means of the following registers: Table 18-8...
Page 600 Chapter 18 Clocked Serial Interface (CSIB) PRSMn - Prescaler mode registers The PRSMn registers control generation of the baud rate signal for CSIB. Access This register can be read/written in 8-bit or 1-bit units. Address <BRG_base> Initial Value . This register is cleared by any reset. BGCEn BGCSn1 BGCSn0 Table 18-10...
Page 601: Baud Rate Calculation
Chapter 18 Clocked Serial Interface (CSIB) 18.7.3 Baud rate calculation The transmission/reception clock is generated by dividing the main clock. The baud rate generated from the main clock is obtained by the following equation. SPCLK1 ------------------------- - BRGn × × Note BRGn count clock BRGn...
Page 602: Cautions
Chapter 18 Clocked Serial Interface (CSIB) 18.8 Cautions 18.8.1 CSIBn behaviour during debugger break The CSIBn continues to operate in debugger break-mode, provided all clocks are continuing. The CSIBn continuous to operate during debugger break-mode • in continuous reception/transmission mode •...
Page 603: Csib Operation Stop
Chapter 18 Clocked Serial Interface (CSIB) 18.8.2 CSIB operation stop Details - Master mode operation When any channel of CSIB is operated with a peripheral clock source different to the clock source of the CPU, the CSIB may stop operating. Depending on the CSIB operating configuration the CSIB behaves as described below.
Page 604 Chapter 18 Clocked Serial Interface (CSIB) SCC. CKC. BRGn clock CSIB clock CPU clock source SPSEL0 PERIC source (SPCLK1) input BRGn PCLK1, BRGn SSCG BRGn Workaround - Slave mode operation In order to avoid the CSIBn stuck condition in slave mode take the following precautions.
Page 605: Features
Chapter 19 I C Bus (IIC) The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the I Bus interface IIC: All devices Instances Names IIC0 to IIC1 Throughout this chapter, the individual instances of I C Bus interface are identified by “n”, for example IICn, or IICCn for the IICn control register. 19.1 Features The I²C provides a synchronous serial interface with the following features: •...
Page 606: Chapter 19 I 2 C Bus (Iic)
Chapter 19 C Bus (IIC) 19.2 I C Pin Configuration The I C function requires to define the pins SCL0 and SDA0 as input and open drain output pins simultaneously. In the following the pin configuration registers are listed to be set up properly for I •...
Page 607: I2C Pin Configuration
Chapter 19 C Bus (IIC) 19.3 I C Pin Configuration The I C function requires to define the pins SCLn and SDAn as input and open drain output pins simultaneously. In the following the pin configuration registers are listed to be set up properly for I •...
Page 608 Chapter 19 C Bus (IIC) Table 19-2 C interface pins set up Cn PFSR0 register Pins and pin group Register settings C0 PFSR0.PFSR04 = 0 SDA0/SCL0 via P16/P17 PMC1.PMC1[7:6] = 11 PICC1.PICC1[7:6] = 00 PILC1.PILC1[7:6] = 00 PDSC1.PDSC1[7:6] = 11 PODC1.PODC1[7:6] = 11 PM1.PM1[7:6] = 11 PFSR0.PFSR04 = 1 SCL0/SDA0 via P64/P65 PLCDC6.PLCDC6[5:4] = 00...
Page 609: I2C Pin Configuration
Chapter 19 C Bus (IIC) 19.4 I C Pin Configuration The I C function requires to define the pins SCLn and SDAn as input and open drain output pins simultaneously. In the following the pin configuration registers are listed to be set up properly for I •...
Page 610 Chapter 19 C Bus (IIC) Table 19-3 C interface pins set up Cn PFSR0 register Pins and pin group Register settings C0 PFSR0.PFSR04 = 0 SDA0/SCL0 via P16/P17 PMC1.PMC1[7:6] = 11 PICC1.PICC1[7:6] = 00 PILC1.PILC1[7:6] = 00 PDSC1.PDSC1[7:6] = 11 PODC1.PODC1[7:6] = 11 PM1.PM1[7:6] = 11 PFSR0.PFSR04 = 1 SCL0/SDA0 via P64/P65 PLCDC6.PLCDC6[5:4] = 00...
Page 611: Configuration
Chapter 19 C Bus (IIC) 19.5 Configuration The block diagram of the I C0n is shown below. Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELnSPIEn WTIMn ACKEn STTn SPTn Slave address Start condition Clear...
Page 612 Chapter 19 C Bus (IIC) A serial bus configuration example is shown below. Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC Address 4 Slave IC Address N Figure 19-2 Serial bus configuration example using I...
Page 613 Chapter 19 C Bus (IIC) Prescaler This selects the sampling clock to be used. Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received.
Page 614: Iic Registers
Chapter 19 C Bus (IIC) 19.6 IIC Registers The I C serial interfaces IICn are controlled and operated by means of the following registers: Table 19-4 IICn registers overview Register name Shortcut Address IICn shift register IICn <base> IICn control register IICCn <base>...
Page 615 Chapter 19 C Bus (IIC) IICCn - IICn control registers The IICCn registers enable/stop I Cn operations, set the wait timing, and set other I Cn operations. Access This register can be read/written in 8-bit or 1-bit units. Address <base> + 2 Initial Value .
Page 616 Chapter 19 C Bus (IIC) SPIEn Enable/disable generation of interrupt request when stop condition is detected Disabled Enabled Condition for clearing (SPIEn = 0) Condition for setting (SPIEn = 1) • Cleared by instruction • Set by instruction • After reset WTIMn Control of wait and interrupt request generation Interrupt request is generated at the eighth clock’s falling edge.
Page 617 Chapter 19 C Bus (IIC) STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDAn line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCLn line is changed to low level.
Page 618 Chapter 19 C Bus (IIC) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until it goes to high level.
Page 619 Chapter 19 C Bus (IIC) IICSn - IICn status registers The IICSn registers indicate the status of the I Cn bus. Access This register can only be read in 8-bit or 1-bit units. Address <base> + 6 Initial Value . This register is cleared by any reset. MSTSn ALDn EXCn...
Page 620 Chapter 19 C Bus (IIC) COIn Matching address detection Addresses do not match. Addresses match. Condition for clearing (COIn = 0) Condition for setting (COIn = 1) • When a start condition is detected • When the received address matches the local address (SVAn register) (set at the rising edge of •...
Page 621 Chapter 19 C Bus (IIC) STDn Start condition detection Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STDn = 0) Condition for setting (STDn = 1) •...
Page 622 Chapter 19 C Bus (IIC) IICFn - IICn flag registers The registers set the I Cn operation mode and indicate the I C bus status. Access This register can be read/written in 8-bit or 1-bit units. STCFn and IICBSYn bits are read-only. Address <base>...
Page 623 Chapter 19 C Bus (IIC) IICRSVn Communication reservation function disable bit Communication reservation enabled Communication reservation disabled Condition for clearing (IICRSVn = 0) Condition for setting (IICRSVn = 1) • Clearing by instruction • Setting by instruction • After reset Note Bits 6 and 7 are read-only bits.
Page 624 Chapter 19 C Bus (IIC) IICCLn - IICn clock select registers The IICCLn registers set the transfer clock for the I Cn bus. The SMCn, CLn1, and CLn0 bits are set by the combination of the IICXn.CLXn bit and the OCKSTHn, OCKSn[1:0] bits of the OCKSn register (see “Transfer rate setting“...
Page 625 Chapter 19 C Bus (IIC) IICXn - IICn function expansion registers The IICXn registers provide additional transfer data rate configuration in fast- speed mode. Setting of the IICXn.CLXn is performed in combination with the IICCLn.SMCn, IICCLn.CLn[1:0], OCKSn.OCKSTHn and OCKSn.OCKSn[1:0] (refer to “Transfer rate setting“ on page 626) Access This register can be read/written in 8-bit or 1-bit units.
Page 626 Chapter 19 C Bus (IIC) Transfer rate setting The nominal transfer rate of the I C interface is determined by the following means: • the root clock source for the I C clock IICLK can be chosen as – main oscillator (4 MHz): ICC.IICSEL1 = 0 –...
Page 627 Chapter 19 C Bus (IIC) Following table lists set-ups for some useful I C transfer clocks. Clock Generator Prescaler C module set-up Transfer clock IICPS IICCLn. IICXn. IICCLn. divisor OCKSn divisor divisor [KHz] [2:0] SMCn CLXn CLn[1:0] 1 0000 380,95 1 0010 95,24 1 0010...
Page 628 Chapter 19 C Bus (IIC) IICn - IICn shift registers The IICn registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. A wait state is released by writing the IICn register during the wait period, and data transfer is started.
Page 629: C Bus Pin Functions
Chapter 19 C Bus (IIC) 19.7 I C Bus Pin Functions The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows. • SCLn This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt Trigger input for fast-speed mode respectively non Schmitt Trigger for standard mode.
Page 630: Start Condition
Chapter 19 C Bus (IIC) condition”, “data”, and “stop condition” output via the I C bus’s serial data bus is shown below. 1 to 7 1 to 7 1 to 7 SCLn SDAn Start Address Data Data Stop condition condition Figure 19-5 C bus serial data transfer timing with stop termination Instead of a stop condition the master may also send a repeated start...
Page 631: Addresses
Chapter 19 C Bus (IIC) SCLn SDAn Figure 19-7 Start condition A start condition is output when the IICCn.STTn bit is set (1) after a stop condition has been detected (IICSn.SPDn bit = 1). When a start condition is detected, the IICSn.STDn bit is set (1). By setting IICCN.STTn=1 the master device will also cancel its own wait status.
Page 632: Transfer Direction Specification
Chapter 19 C Bus (IIC) 19.8.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 633 Chapter 19 C Bus (IIC) Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the ACKEn bit to 0 will prevent the ACK signal from being returned.
Page 634: Stop Condition
Chapter 19 C Bus (IIC) 19.8.5 Stop condition When the SCLn pin is high level, changing the SDAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed.
Page 635: Wait Signal (Wait)
Chapter 19 C Bus (IIC) 19.8.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status.
Page 636 Chapter 19 C Bus (IIC) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master (Tx) after output of ninth clock. IICn data write (cancel wait) IICn SCLn Slave (Rx)
Page 637: I 2 C Interrupt Request Signals (Intiicn)
Chapter 19 C Bus (IIC) 19.9 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing. 19.9.1 Master device operation Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 638 Chapter 19 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1...
Page 639 Chapter 19 C Bus (IIC) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 ▲4 Δ5 ▲1: IICSn register = 1010X110B...
Page 640: Slave Device Operation
Chapter 19 C Bus (IIC) 19.9.2 Slave device operation Start ~ Address ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 Δ4 ▲1: IICSn register = 0001X110B ▲2: IICSn register = 0001X000B ▲3: IICSn register = 0001X000B Δ...
Page 641 Chapter 19 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 642 Chapter 19 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 643 Chapter 19 C Bus (IIC) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2...
Page 644: Slave Device Operation (When Receiving Extension Code)
Chapter 19 C Bus (IIC) 19.9.3 Slave device operation (when receiving extension code) Start ~ Code ~ Data ~ Data ~ Stop <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 Δ4 ▲1: IICSn register = 0010X010B ▲2: IICSn register = 0010X000B...
Page 645 Chapter 19 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 646 Chapter 19 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2 ▲3...
Page 647 Chapter 19 C Bus (IIC) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 ▲1 ▲2...
Page 648: Operation Without Communication
Chapter 19 C Bus (IIC) 19.9.4 Operation without communication Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1 Δ 1: IICSn register = 00000001B Remarks 1. Δ: Generated only when SPIEn bit = 1 2.
Page 649 Chapter 19 C Bus (IIC) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 ▲3 Δ4 ▲1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) ▲2: IICSn register = 0010X000B ▲3: IICSn register = 0010X000B Δ...
Page 650: Operation When Arbitration Loss Occurs
Chapter 19 C Bus (IIC) 19.9.6 Operation when arbitration loss occurs When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 ▲1 Δ2 ▲1: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 651 Chapter 19 C Bus (IIC) When arbitration loss occurs during data transfer <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 ▲1 ▲2 Δ3 ▲1: IICSn register = 10001110B ▲2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 652 Chapter 19 C Bus (IIC) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 ▲1 ▲2 Δ3 ▲1: IICSn register = 1000X110B ▲2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 653 Chapter 19 C Bus (IIC) When arbitration loss occurs due to low level of SDAn pin when attempting to generate a restart condition When WTIMn bit = 1 STTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ▲1 ▲2...
Page 654 Chapter 19 C Bus (IIC) When arbitration loss occurs due to low level of SDAn pin when attempting to generate a stop condition When WTIMn bit = 1 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 ▲1 ▲2...
Page 655: Interrupt Request Signal (Intiicn)
Chapter 19 C Bus (IIC) 19.10 Interrupt Request Signal (INTIICn) The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below. Table 19-6 INTIICn generation timing and wait control WTIMn Bit During Slave Device Operation During Master Device Operation...
Page 656: Address Match Detection Method
Chapter 19 C Bus (IIC) Wait cancellation method The four wait cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • Note By start condition setting (IICCn.STTn bit = 1) •...
Page 657: Extension Code
Chapter 19 C Bus (IIC) 19.13 Extension Code • When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock.
Page 658: Arbitration
Chapter 19 C Bus (IIC) 19.14 Arbitration When several master devices simultaneously output a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs.
Page 659: Wakeup Function
Chapter 19 C Bus (IIC) Table 19-8 Status during arbitration and interrupt request signal generation timing Status During Arbitration Interrupt Request Generation Timing Transmitting address transmission At falling edge of eighth or ninth clock following byte Note 1 transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data...
Page 660: Communication Reservation
Chapter 19 C Bus (IIC) 19.16 Communication Reservation 19.16.1 Communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
Page 661 Chapter 19 C Bus (IIC) Table 19-9 Wait periods with communication reservation function enabled Prescaler C module set-up Waiting module Transfer clock time in Mode IICNn. IICCLn IICCLn IICCLn input IICLKTC IICLK OCKS IICLKPS CLXn .SMCn .CLn1 .CLn0 clock cycles IICLK IICLK/44 IICLK/2...
Page 662 Chapter 19 C Bus (IIC) STTn Write to Program processing IICn Set SPDn Communication Hardware processing reservation and INTIICn STDn SCL0n SDA0n Output by master with bus access Figure 19-15 Communication reservation timing Communication reservations are accepted via the following timing. After the IICSn.STDn bit is set to 1, a communication reservation can be made by setting the IICCn.STTn bit to 1 before a stop condition is detected.
Page 663 Chapter 19 C Bus (IIC) Sets STTn bit (communication reservation). SET1 STTn Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). Secures wait period set by software (see Table 17-16). Wait Note (Communication reservation)
Page 664: Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
Chapter 19 C Bus (IIC) 19.16.2 Communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 665: Cautions
Chapter 19 C Bus (IIC) 19.17 Cautions When IICFn.STCENn bit = 0 Immediately after the I C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication.
Page 666: Communication Operations
Chapter 19 C Bus (IIC) 19.18 Communication Operations 19.18.1 Master operation with communication reservation The following shows the flowchart for master communication when the communication reservation function is enabled (IICFn.IICRSVn bit = 0) and the master operation is started after a stop condition is detected (IICFn.STCENn bit = 0).
Page 667: Master Operation Without Communication Reservation
Chapter 19 C Bus (IIC) 19.18.2 Master operation without communication reservation The following shows the flowchart for master communication when the communication reservation function is disabled (IICRSVn bit = 1) and the master operation is started without detecting a stop condition (STCENn bit = 1).
Page 668: Slave Operation
Chapter 19 C Bus (IIC) 19.18.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 669 Chapter 19 C Bus (IIC) Communication direction flag This flag indicates the direction of communication and is the same as the value of IICSn.TRCn bit. The following shows the operation of the main processing block during slave operation. Start I C0n and wait for the communication enabled status.
Page 670 Chapter 19 C Bus (IIC) START IICCLn ← XXH Selection of transfer flag IICFn ← XXH IICFn register setting IICCn ← XXH IICEn = 1 Communication mode? ACKEn = WTIMn = 1 Communication direction flag = 1? WRELn = 1 WTIMn = 1 Communication mode? Data processing...
Page 671 Chapter 19 C Bus (IIC) During an INTIICn interrupt, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated.
Page 672: Timing Of Data Communication
Chapter 19 C Bus (IIC) 19.19 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 673 Chapter 19 C Bus (IIC) Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device ←...
Page 674 Chapter 19 C Bus (IIC) Processing by master device ← ← IICn data IICn data IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transmit Transfer lines SCL0n SDA0n Processing by slave device ← ← IICn IICn FFH Note IICn FFH Note...
Page 675 Chapter 19 C Bus (IIC) Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transmit Transfer lines SCL0n SDA0n Stop Start condition condition Processing by slave device ←...
Page 676 Chapter 19 C Bus (IIC) Processing by master device IICn ← address IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn Note INTIICn TRCn Transfer lines SCL0n AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDA0n Start condition Processing by slave device IICn ←...
Page 677 Chapter 19 C Bus (IIC) Processing by master device IICn ← FFH Note IICn ← FFH Note IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note Note WRELn INTIICn TRCn Receive Transfer lines SCL0n SDA0n Processing by slave device IICn ←...
Page 678 Chapter 19 C Bus (IIC) Processing by master device IICn ← FFH Note IICn ← address IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn Note WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCL0n SDA0n N-ACK Stop Start condition condition Processing by slave device...
Page 679: Chapter 20 Can Controller (Can)
Chapter 20 CAN Controller (CAN) These microcontrollers feature an on-chip n-channel CAN (Controller Area Network) controller that complies with the CAN protocol as standardized in ISO 11898. The V850E/Dx3 - DJ3/DL3 microcontrollers have following number of channels of the CAN controller: µPD70F3427, µPD70F3425, µPD70F3424, µPD70F3423, µPD70F3426A...
Page 680: Features
Chapter 20 CAN Controller (CAN) 20.1 Features • Compliant with ISO 11898 and tested according to ISO/DIS 16845 (CAN conformance test) • Standard frame and extended frame transmission/reception enabled • Transfer rate: 1 Mbps max. (if CAN clock input ≥ 8 MHz, for 32 channels) •...
Page 681: Overview Of Functions
Chapter 20 CAN Controller (CAN) 20.1.1 Overview of functions Table 20-1 presents an overview of the CAN Controller functions. Table 20-1 Overview of functions Function Details Protocol CAN protocol ISO 11898 (standard and extended frame transmission/reception) Maximum 1 Mbps (CAN clock input ≥ 8 MHz) Baud rate Data storage Storing messages in the CAN RAM...
Page 682: Configuration
Chapter 20 CAN Controller (CAN) 20.1.2 Configuration The CAN Controller is composed of the following four blocks. • NPB interface This functional block provides an NPB (Peripheral I/O Bus) interface and means of transmitting and receiving signals between the CAN module and the host CPU.
Page 683: Can Protocol
Chapter 20 CAN Controller (CAN) 20.2 CAN Protocol CAN (Controller Area Network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class C). CAN is prescribed by ISO 11898. For details, refer to the ISO 11898 specifications. The CAN specification is generally divided into two layers: a physical layer and a data link layer.
Page 684: Frame Types
Chapter 20 CAN Controller (CAN) 20.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 20-2 Frame types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame...
Page 685 Chapter 20 CAN Controller (CAN) Remote frame A remote frame is composed of six fields. Remote frame <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Figure 20-4 Remote frame Note...
Page 686 Chapter 20 CAN Controller (CAN) (b) Arbitration field The arbitration field is used to set the priority, data frame/remote frame, and frame format. Arbitration field (Control field) Identifier (r1) ID28 · · · · · · · · · · · · · · · · · · · ID18 (11 bits) (1 bit) (1 bit)
Page 687 Chapter 20 CAN Controller (CAN) (c) Control field The control field sets “DLC” as the number of data bytes in the data field (DLC = 0 to 8). (Arbitration field) Control field (Data field) DLC3 DLC2 DLC1 DLC0 (IDE) Figure 20-8 Control field Note D: Dominant = 0...
Page 688 Chapter 20 CAN Controller (CAN) (d) Data field The data field contains the amount of data (byte units) set by the control field. Up to 8 units of data can be set. (Control field) Data field (CRC field) Data 0 Data 7 (8 bits) (8 bits)
Page 689 Chapter 20 CAN Controller (CAN) (f) ACK field The ACK field is used to acknowledge normal reception. (CRC field) ACK field (End of frame) ACK slot ACK delimiter (1 bit) (1 bit) Figure 20-11 ACK field Note D: Dominant = 0 R: Recessive = 1 •...
Page 690 Chapter 20 CAN Controller (CAN) Note Bus idle: State in which the bus is not used by any node. D: Dominant = 0 R: Recessive = 1 – Error passive node The interframe space consists of an intermission field, a suspend transmission field, and a bus idle field.
Page 691: Error Frame
Chapter 20 CAN Controller (CAN) 20.2.4 Error frame An error frame is output by a node that has detected an error. Error frame (<4>) <1> <2> <3> (<5>) 6 bits 0 to 6 bits 8 bits Interframe space or overload frame Error delimiter Error flag 2 Error flag 1...
Page 692: Overload Frame
Chapter 20 CAN Controller (CAN) 20.2.5 Overload frame An overload frame is transmitted under the following conditions. • When the receiving node has not completed the reception operation • If a dominant level is detected at the first two bits during intermission •...
Page 693: Functions
Chapter 20 CAN Controller (CAN) 20.3 Functions 20.3.1 Determining bus priority When a node starts transmission: • During bus idle, the node that output data first transmits the data. When more than one node starts transmission: • The node that consecutively outputs the dominant level for the longest from the first bit of the arbitration field has the bus priority (if a dominant level and a recessive level are simultaneously transmitted, the dominant level is taken as the bus value).
Page 694: Multi Masters
Chapter 20 CAN Controller (CAN) 20.3.3 Multi masters As the bus priority (a node acquiring transmit functions) is determined by the identifier, any node can be the bus master. 20.3.4 Multi cast Although there is one transmitting node, two or more nodes can receive the same data at the same time because the same identifier can be set to two or more nodes.
Page 695 Chapter 20 CAN Controller (CAN) Output timing of error frame Table 20-12 Output timing of error frame Type Output timing Bit error, stuff error, Error frame output is started at the timing of the bit following form error, ACK error the detected error.
Page 696 Chapter 20 CAN Controller (CAN) Table 20-13 Types of error states Value of error Indication of Type Operation Operation specific to error state counter CnINFO register Error active Transmission 0 to 95 TECS1, TECS0 = 00 Outputs an active error flag (6 consecutive dominant-level bits) on detection of the error.
Page 697 Chapter 20 CAN Controller (CAN) (b) Error counter The error counter counts up when an error has occurred, and counts down upon successful transmission and reception. The error counter is updated immediately after error detection. Table 20-14 Error counter Transmission error counter Reception error counter State (TEC7 to TEC0 bits)
Page 698 Chapter 20 CAN Controller (CAN) Recovery from bus-off state When the CAN module is in the bus-off state, the CAN module permanently sets its output signals (CTXDn) to recessive level. The CAN module recovers from the bus-off state in the following bus-off recovery sequence.
Page 699 Chapter 20 CAN Controller (CAN) Caution In the bus-off recovery sequence, REC[6:0] counts up (+1) each time 11 consecutive recessive-level bits have been detected. Even during the bus-off period, the CAN module can enter the CAN sleep mode or CAN stop mode. To start the bus-off recovery sequence, it is necessary to transit to the initialization mode once.
Page 700 Chapter 20 CAN Controller (CAN) Caution This function is not defined by the CAN protocol ISO 11898. When using this function, thoroughly evaluate its effect on the network system. Initializing CAN module error counter register (CnERC) in initialization mode If it is necessary to initialize the CAN module error counter register (CnERC) and CAN module information register (CnINFO) for debugging or evaluating a program, they can be initialized to the default value by setting the CCERC bit of the CnCTRL register in the initialization mode.
Page 701: Baud Rate Control Function
Chapter 20 CAN Controller (CAN) 20.3.7 Baud rate control function Prescaler The CAN controller has a prescaler that divides the clock (f ) supplied to CAN. This prescaler generates a CAN protocol layer basic system clock (f derived from the CAN module system clock (f ), and divided by 1 to 256 CANMOD (“CnBRP - CANn module bit rate prescaler register“...
Page 702 Chapter 20 CAN Controller (CAN) Data bit time(DBT) Sync segment Prop segment Phase segment 1 Phase segment 2 Sample point (SPT) Figure 20-19 Configuration of data bit time defined by CAN specification Table 20-16 Configuration of data bit time defined by CAN specification Notes on setting to conform to CAN Segment name Settable range...
Page 703 Chapter 20 CAN Controller (CAN) Synchronizing data bit • The receiving node establishes synchronization by a level change on the bus because it does not have a sync signal. • The transmitting node transmits data in synchronization with the bit timing of the transmitting node.
Page 704: Connection With Target System
Chapter 20 CAN Controller (CAN) If phase error is positive CAN bus Prop Sync Phase Bit timing Phase segment 1 segment segment segment 2 Sample point If phase error is negative CAN bus Prop Phase Sync Bit timing Phase segment 1 segment segment segment 2...
Page 705: Internal Registers Of Can Controller
Chapter 20 CAN Controller (CAN) 20.5 Internal Registers of CAN Controller 20.5.1 CAN module register and message buffer addresses In this chapter all register and message buffer addresses are defined as address offsets to different base addresses. Since all registers are accessed via the programmable peripheral area the bottom address is defined by the BPC register (refer to “Programmable peripheral I/O area“...
Page 706: Can Controller Configuration
Chapter 20 CAN Controller (CAN) 20.5.2 CAN Controller configuration Table 20-18 List of CAN Controller registers Item Register Name CANn global registers CANn global control register (CnGMCTRL) CANn global clock selection register (CnGMCS) CANn global automatic block transmission control register (CnGMABT) CANn global automatic block transmission delay setting register (CnGMABTD) CANn module registers CANn module mask 1 register (CnMASK1L, CnMASK1H)
Page 707: Can Registers Overview
Chapter 20 CAN Controller (CAN) 20.5.3 CAN registers overview CANn global and module registers The following table lists the address offsets to the CANn register base address CnRBaseAddr. Table 20-19 CANn global and module registers Access Address Register name Symbol After reset offset 1-bit...
Page 708 Chapter 20 CAN Controller (CAN) CANn message buffer registers The addresses in the following table denote the address offsets to the CANn message buffer base address: CnMBaseAddr. Example CAN0, message buffer register m = 14 = E , byte 6 C0MDATA614 has the address E x 20 + C0MBaseAddr...
Page 709: Register Bit Configuration
Chapter 20 CAN Controller (CAN) 20.5.4 Register bit configuration Table 20-21 CAN global register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnGMCTRL (W) Clear GOM Set EFSD Set GOM CnGMCTRL (R) EFSD...
Page 710 Chapter 20 CAN Controller (CAN) Table 20-22 CAN module register bit configuration (2/2) Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnLEC (W) CnLEC (R) LEC2 LEC1 LEC0 CnINFO BOFF TECS1 TECS0...
Page 711 Chapter 20 CAN Controller (CAN) Table 20-23 Message buffer register bit configuration Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8 offset CnMDATA01m Message data (byte 0) Message data (byte 1) CnMDATA0m Message data (byte 0) CnMDATA1m...
Page 712: Bit Set/Clear Function
Chapter 20 CAN Controller (CAN) 20.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values.
Page 713 Chapter 20 CAN Controller (CAN) Bit status after bit setting/clearing operations Clear Clear Clear Clear Clear Clear Clear Clear Set 7 Set 6 Set 5 Set 4 Set 3 Set 2 Set 1 Set 0 Set 0 ... 7 Clear 0 ... 7 Status of bit n after bit set/clear operation No change No change...
Page 714: Control Registers
Chapter 20 CAN Controller (CAN) 20.7 Control Registers CnGMCTRL - CANn global control register The CnGMCTRL register is used to control the operation of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 000 Initial Value 0000 .
Page 715 Chapter 20 CAN Controller (CAN) EFSD Bit enabling forced shut down Forced shut down disabled. Forced shut down enabled by subsequent clearing of GOM bit to 0. Caution To request forced shut down, the GOM bit must be cleared to 0 in a subsequent, immediately following access after the EFSD bit has been set to 1.
Page 716 Chapter 20 CAN Controller (CAN) CnGMCS - CANn global clock selection register The CnGMCS register is used to select the CAN module system clock. Access This register can be read/written in 8-bit units. Address <CnRBaseAddr> + 002 Initial Value . The register is initialized by any reset. CCP3 CCP2 CCP1...
Page 717 Chapter 20 CAN Controller (CAN) CnGMABT - CANn global automatic block transmission control register The CnGMABT register is used to control the automatic block transmission (ABT) operation. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 006 Initial Value 0000 .
Page 718 Chapter 20 CAN Controller (CAN) (b) CnGMABT write ABTCLR ABTTRG Clear ABTTRG Caution Before changing the normal operation mode with ABT to the initialization mode, be sure to set the CnGMABT register to the default value (0000 ) and confirm the CnGMABT register is surely initialized to the default value (0000 Set ABTCLR Automatic block transmission engine clear request bit The automatic block transmission engine is in idle status or under...
Page 719 Chapter 20 CAN Controller (CAN) CnGMABTD - CANn global automatic block transmission delay register The CnGMABTD register is used to set the interval at which the data of the message buffer assigned to ABT is to be transmitted in the normal operation mode with ABT.
Page 720 Chapter 20 CAN Controller (CAN) CnMASKaL, CnMASKaH - CANn module mask control register (a = 1 to 4) The CnMASKaL and CnMASKaH registers are used to extend the number of receivable messages into the same message buffer by masking part of the identifier (ID) comparison of a message and invalidating the ID of the masked part.
Page 721 Chapter 20 CAN Controller (CAN) (c) CANn module mask 3 register (CnMASK3L, CnMASK3H) Access These registers can be read/written in 16-bit units. Address CnMASK3L: <CnRBaseAddr> + 048 CnMASK3H: <CnRBaseAddr> + 04A Initial Value Undefined. CnMASK3L CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8...
Page 722 Chapter 20 CAN Controller (CAN) CnCTRL - CANn module control register The CnCTRL register is used to control the operation mode of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 050 Initial Value 0000 .
Page 723 Chapter 20 CAN Controller (CAN) CCERC Error counter clear bit The CnERC and CnINFO registers are not cleared in the initialization mode. The CnERC and CnINFO registers are cleared in the initialization mode. Note The CCERC bit is used to clear the CnERC and CnINFO registers for re- initialization or forced recovery from the bus-off state.
Page 724 Chapter 20 CAN Controller (CAN) PSMODE1 PSMODE0 Power save mode No power save mode is selected. CAN sleep mode Setting prohibited CAN stop mode Caution Transition to and from the CAN stop mode must be made via CAN sleep mode. A request for direct transition to and from the CAN stop mode is ignored.
Page 725 Chapter 20 CAN Controller (CAN) (b) CnCTRL write CCERC PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 Clear Clear Clear Clear Clear Clear Clear VALID PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0 Set CCERC Setting of CCERC bit CCERC bit is set to 1. Other than above CCERC bit is not changed.
Page 726 Chapter 20 CAN Controller (CAN) Clear Setting of OPMODE1 bit OPMODE1 OPMODE1 OPMODE1 bit is cleared to 0. OPMODE1 bit is set to 1. Other than above OPMODE1 bit is not changed. Clear Setting of OPMODE2 bit OPMODE2 OPMODE2 OPMODE2 bit is cleared to 0. OPMODE2 bit is set to 1.
Page 727 Chapter 20 CAN Controller (CAN) CnINFO - CANn module information register The CnINFO register indicates the status of the CAN module. Access This register is read-only in 8-bit units. Address <CnRBaseAddr> + 053 Initial Value . The register is initialized by any reset. BOFF TECS1 TECS0...
Page 728 Chapter 20 CAN Controller (CAN) CnERC - CANn module error counter register The CnERC register indicates the count value of the transmission/reception error counter. Access This register is read-only in 16-bit units. Address <CnRBaseAddr> + 054 Initial Value 0000 . The register is initialized by any reset. REPS REC6 REC5...
Page 729 Chapter 20 CAN Controller (CAN) (10) CnIE - CANn module interrupt enable register The CnIE register is used to enable or disable the interrupts of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 056 Initial Value 0000 .
Page 730 Chapter 20 CAN Controller (CAN) Set CIE2 Clear CIE2 Setting of CIE2 bit CIE2 bit is cleared to 0. CIE2 bit is set to 1. Other than above CIE2 bit is not changed. Set CIE1 Clear CIE1 Setting of CIE1 bit CIE1 bit is cleared to 0.
Page 731 Chapter 20 CAN Controller (CAN) (11) CnINTS - CANn module interrupt status register The CnINTS register indicates the interrupt status of the CAN module. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 058 Initial Value 0000 .
Page 732 Chapter 20 CAN Controller (CAN) (12) CnBRP - CANn module bit rate prescaler register The CnBRP register is used to select the CAN protocol layer basic system clock (f ). The communication baud rate is set to the CnBTR register. Access This register can be read/written in 8-bit units.
Page 733 Chapter 20 CAN Controller (CAN) (13) CnBTR - CANn module bit rate register The CnBTR register is used to control the data bit time of the communication baud rate. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 05C Initial Value 370F .
Page 734 Chapter 20 CAN Controller (CAN) TSEG13 TSEG12 TSEG11 TSEG10 Length of time segment 1 Setting prohibited (default value) This setting must not be made when the CnBRP register = 00 Note = 1/f : CAN protocol layer basic system clock) (14) CnLIPT - CANn module last in-pointer register The CnLIPT register indicates the number of the message buffer in which a...
Page 735 Chapter 20 CAN Controller (CAN) (15) CnRGPT - CANn module receive history list register The CnRGPT register is used to read the receive history list. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 060 Initial Value xx02 .
Page 736 Chapter 20 CAN Controller (CAN) (b) CnRGPT write Clear ROVF Clear ROVF Setting of ROVF bit ROVF bit is not changed. ROVF bit is cleared to 0. (16) CnLOPT - CANn module last out-pointer register The CnLOPT register indicates the number of the message buffer to which a data frame or a remote frame was transmitted last.
Page 737 Chapter 20 CAN Controller (CAN) (17) CnTGPT - CANn module transmit history list register The CnTGPT register is used to read the transmit history list. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 064 Initial Value xx02 .
Page 738 Chapter 20 CAN Controller (CAN) (b) CnTGPT write Clear TOVF Clear Setting of TOVF bit TOVF TOVF bit is not changed. TOVF bit is cleared to 0. R01UH0129ED0701 Rev. 7.01 User Manual...
Page 739 Chapter 20 CAN Controller (CAN) (18) CnTS - CANn module time stamp register The CnTS register is used to control the time stamp function. Access This register can be read/written in 16-bit units. Address <CnRBaseAddr> + 066 Initial Value 0000 .
Page 740 Chapter 20 CAN Controller (CAN) (b) CnTS write TSLOCK TSSEL TSEN Clear Clear Clear TSLOCK TSSEL TSEN Clear Setting of TSLOCK bit TSLOCK TSLOCK TSLOCK bit is cleared to 0. TSLOCK bit is set to 1. Other than above TSLOCK bit is not changed. Clear Setting of TSSEL bit TSSEL...
Page 741 Chapter 20 CAN Controller (CAN) (19) CnMDATAxm, CnMDATAzm - CANn message data byte register (x = 0 to 7, z = 01, 23, 45, 67) The CnMDATAxm, CnMDATAzm registers are used to store the data of a transmit/receive message. Access The CnMDATAzm registers can be read/written in 16-bit units.
Page 742 Chapter 20 CAN Controller (CAN) CnMDATA45m MDATA4515 MDATA4514 MDATA4513 MDATA4512 MDATA4511 MDATA4510 MDATA459 MDATA458 MDATA457 MDATA456 MDATA455 MDATA454 MDATA453 MDATA452 MDATA451 MDATA450 CnMDATA4m MDATA47 MDATA46 MDATA45 MDATA44 MDATA43 MDATA42 MDATA41 MDATA40 CnMDATA5m MDATA57 MDATA56 MDATA55 MDATA54 MDATA53 MDATA52 MDATA51 MDATA50 CnMDATA67m MDATA6715 MDATA6714 MDATA6713 MDATA6712 MDATA6711 MDATA6710 MDATA679 MDATA678...
Page 743 Chapter 20 CAN Controller (CAN) (20) CnMDLCm - CANn message data length register m The CnMDLCm register is used to set the number of bytes of the data field of a message buffer. Access This register can be read/written in 8-bit units. Address Refer to “CAN registers overview“...
Page 744 Chapter 20 CAN Controller (CAN) (21) CnMCONFm - CANn message configuration register m The CnMCONFm register is used to specify the type of the message buffer and to set a mask. Access This register can be read/written in 8-bit units. Address Refer to “CAN registers overview“...
Page 745 Chapter 20 CAN Controller (CAN) Message buffer assignment bit Message buffer not used. Message buffer used. Caution Be sure to write 0 to bits 2 and 1. R01UH0129ED0701 Rev. 7.01 User Manual...
Page 746 Chapter 20 CAN Controller (CAN) (22) CnMIDLm, CnMIDHm - CANn message ID register m The CnMIDLm and CnMIDHm registers are used to set an identifier (ID). Access These registers can be read/written in 16-bit units. Address Refer to “CAN registers overview“ on page 707. Initial Value Undefined.
Page 747 Chapter 20 CAN Controller (CAN) (23) CnMCTRLm - CANn message control register m The CnMCTRLm register is used to control the operation of the message buffer. Access This register can be read/written in 16-bit units. Address Refer to “CAN registers overview“ on page 707. Initial Value 00x0 0000 0000 0000 .
Page 748 Chapter 20 CAN Controller (CAN) Message buffer transmission request bit No message frame transmitting request that is pending or being transmitted is in the message buffer. The message buffer is holding transmission of a message frame pending or is transmitting a message frame. Message buffer ready bit The message buffer can be written by software.
Page 749 Chapter 20 CAN Controller (CAN) Set RDY Clear RDY Setting of RDY bit RDY bit is cleared to 0. RDY bit is set to 1. Other than above RDY bit is not changed. Set IE bit and RDY bit always separately. Caution Do not set the DN bit to 1 by software.
Page 750: Can Controller Initialization
Chapter 20 CAN Controller (CAN) 20.8 CAN Controller Initialization 20.8.1 Initialization of CAN module Before CAN module operation is enabled, the CAN module system clock needs to be determined by setting the CCP[3:0] bits of the CnGMCS register by software. Do not change the setting of the CAN module system clock after CAN module operation is enabled.
Page 751 Chapter 20 CAN Controller (CAN) the transmit message buffer, set a transmission request using the procedure described below. When setting a transmission request to a message buffer that has been redefined without aborting the transmission in progress, however, the 1-bit wait time is not necessary. Redefinition completed Execute transmission?
Page 752: Transition From Initialization Mode To Operation Mode
Chapter 20 CAN Controller (CAN) 20.8.4 Transition from initialization mode to operation mode The CAN module can be switched to the following operation modes. • Normal operation mode • Normal operation mode with ABT • Receive-only mode • Single-shot mode •...
Page 753: Resetting Error Counter Cnerc Of Can Module
Chapter 20 CAN Controller (CAN) 20.8.5 Resetting error counter CnERC of CAN module If it is necessary to reset the CAN module error counter CnERC and CAN module information register CnINFO when re-initialization or forced recovery from the bus-off status is made, set the CCERC bit of the CnCTRL register to 1 in the initialization mode.
Page 754: Message Reception
Chapter 20 CAN Controller (CAN) 20.9 Message Reception 20.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process).
Page 755: Receive Data Read
Chapter 20 CAN Controller (CAN) 20.9.2 Receive data read To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 20-49 on page 805 to Figure 20-52 on page 809. During message reception, the CAN module sets DN of the CnMCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process.
Page 756: Receive History List Function
Chapter 20 CAN Controller (CAN) 20.9.3 Receive history list function The receive history list (RHL) function records in the receive history list the number of the receive message buffer in which each data frame or remote frame was received and stored. The RHL consists of storage elements equivalent to up to 23 messages, the last in-message pointer (LIPT) with the corresponding CnLIPT register and the receive history list get pointer (RGPT) with the corresponding CnRGPT register.
Page 757 Chapter 20 CAN Controller (CAN) As long as the RHL contains 23 or less entries the sequence of occurrence is maintained. If more receptions occur without reading the RHL by the host processor, complete sequence of receptions can not be recovered. Figure 20-29 Receive history list R01UH0129ED0701 Rev.
Page 758: Mask Function
Chapter 20 CAN Controller (CAN) 20.9.4 Mask function For any message buffer, which is used for reception, the assignment to one of four global reception masks (or no mask) can be selected. By using the mask function, the message ID comparison can be reduced by masked bits, herewith allowing the reception of several different IDs into one buffer.
Page 759 Chapter 20 CAN Controller (CAN) The CMID27 to CMID24 and CMID22 bits are cleared to 0, and the CMID28, CMID23, and CMID21 to CMID0 bits are set to 1. R01UH0129ED0701 Rev. 7.01 User Manual...
Page 760: Multi Buffer Receive Block Function
Chapter 20 CAN Controller (CAN) 20.9.5 Multi buffer receive block function The multi buffer receive block (MBRB) function is used to store a block of data in two or more message buffers sequentially with no CPU interaction, by setting the same ID to two or more message buffers with the same message buffer type.
Page 761: Remote Frame Reception
Chapter 20 CAN Controller (CAN) 20.9.6 Remote frame reception In all the operation modes, when a remote frame is received, the message buffer that is to store the remote frame is searched from all the message buffers satisfying the following conditions. •...
Page 762: Message Transmission
Chapter 20 CAN Controller (CAN) 20.10 Message Transmission 20.10.1 Message transmission A message buffer with its TRQ bit set to 1 participates in the search for the most high-prioritized message when the following conditions are fulfilled. This behavior is valid for all operational modes. •...
Page 763 Chapter 20 CAN Controller (CAN) Priority Conditions Description 1 (high) Value of first 11 bits of ID The message frame with the lowest value represented by the first 11 [ID28 to ID18]: bits of the ID is transmitted first. If the value of an 11-bit standard ID is equal to or smaller than the first 11 bits of a 29-bit extended ID, the 11- bit standard ID has a higher priority than a message frame with a 29-bit extended ID.
Page 764: Transmit History List Function
Chapter 20 CAN Controller (CAN) 20.10.2 Transmit history list function The transmit history list (THL) function records in the transmit history list the number of the transmit message buffer from which data or remote frames have been were sent. The THL consists of storage elements equivalent to up to seven messages, the last out-message pointer (LOPT) with the corresponding CnLOPT register, and the transmit history list get pointer (TGPT) with the corresponding CnTGPT register.
Page 765 Chapter 20 CAN Controller (CAN) Caution If the history list is in the overflow condition (TOVF is set), reading the history list contents is still possible, until the history list is empty (indicated by THPM flag set). Nevertheless, the history list remains in the overflow condition, until TOVF is cleared by software.
Page 766: Automatic Block Transmission (Abt)
Chapter 20 CAN Controller (CAN) 20.10.3 Automatic block transmission (ABT) The automatic block transmission (ABT) function is used to transmit two or more data frames successively with no CPU interaction. The maximum number of transmit message buffers assigned to the ABT function is eight (message buffer numbers 0 to 7).
Page 767 Chapter 20 CAN Controller (CAN) held pending and the transmission ID of the message buffers other than those used by the ABT function. Transmission of a data frame from an ABT message buffer is not recorded in the transmit history list (THL). Caution Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT operation at buffer No.0.
Page 768: Transmission Abort Process
Chapter 20 CAN Controller (CAN) 20.10.4 Transmission abort process Transmission abort process except for in normal operation mode with automatic block transmission (ABT) The user can clear the TRQ bit of the CnMCTRLm register to 0 to abort a transmission request. The TRQ bit will be cleared immediately if the abort was successful.
Page 769: Remote Frame Transmission
Chapter 20 CAN Controller (CAN) When the normal operation mode with ABT is resumed after ABT has been aborted and the ABTTRG bit is set to 1, the next ABT message buffer to be transmitted can be determined from the following table. Status of TRQ of Abort after successful transmission Abort after erroneous transmission...
Page 770: Power Saving Modes
Chapter 20 CAN Controller (CAN) 20.11 Power Saving Modes 20.11.1 CAN sleep mode The CAN sleep mode can be used to set the CAN Controller to stand-by mode in order to reduce power consumption. The CAN module can enter the CAN sleep mode from all operation modes.
Page 771 Chapter 20 CAN Controller (CAN) the module has entered the CAN sleep mode, the PSMODE[1:0] bits are set to 01 • If a request for transition to the initialization mode and a request for transition to the CAN sleep mode are made at the same time while the CAN module is in one of the operation modes, the request for the initialization mode is enabled.
Page 772 Chapter 20 CAN Controller (CAN) Releasing CAN sleep mode The CAN sleep mode is released by the following events: • When the CPU writes 00 to the PSMODE[1:0] bits of the CnCTRL register • A falling edge at the CAN reception pin (CRXDn) (i.e. the CAN bus level shifts from recessive to dominant) Caution Even if the falling edge belongs to the SOF of a receive message, this...
Page 773: Can Stop Mode
Chapter 20 CAN Controller (CAN) 20.11.2 CAN stop mode The CAN stop mode can be used to set the CAN Controller to stand-by mode to reduce power consumption. The CAN module can enter the CAN stop mode only from the CAN sleep mode. Release of the CAN stop mode puts the CAN module in the CAN sleep mode.
Page 774: Example Of Using Power Saving Modes
Chapter 20 CAN Controller (CAN) 20.11.3 Example of using power saving modes In some application systems, it may be necessary to place the CPU in a power saving mode to reduce the power consumption. By using the power saving mode specific to the CAN module and the power saving mode specific to the CPU in combination, the CPU can be woken up from the power saving status by the CAN bus.
Page 775: Interrupt Function
Chapter 20 CAN Controller (CAN) 20.12 Interrupt Function The CAN module provides 6 different interrupt sources. The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register.
Page 776: Diagnosis Functions And Special Operational Modes
Chapter 20 CAN Controller (CAN) 20.13 Diagnosis Functions and Special Operational Modes The CAN module provides a receive-only mode, single-shot mode, and self- test mode to support CAN bus diagnosis functions or the operation of special CAN communication methods. 20.13.1 Receive-only mode The receive-only mode is used to monitor receive messages without causing any interference on the CAN bus and can be used for CAN bus analysis nodes.
Page 777: Single-Shot Mode
Chapter 20 CAN Controller (CAN) node recognizes that it has transmitted ACK. An overload frame cannot be transmitted to the CAN bus. Caution If only two CAN nodes are connected to the CAN bus and one of them is operating in the receive-only mode, there is no ACK on the CAN bus. Due to the missing ACK, the transmitting node will transmit an active error flag, and repeat transmitting a message frame.
Page 778: Self-Test Mode
Chapter 20 CAN Controller (CAN) 20.13.3 Self-test mode In the self-test mode, message frame transmission and message frame reception can be tested without connecting the CAN node to the CAN bus or without affecting the CAN bus. In the self-test mode, the CAN module is completely disconnected from the CAN bus, but transmission and reception are internally looped back.
Page 779: Receive/Transmit Operation In Each Operation Mode
Chapter 20 CAN Controller (CAN) 20.13.4 Receive/transmit operation in each operation mode The following table shows outline of the receive/transmit operation in each operation mode. Table 20-26 Outline of the receive/transmit in each operation mode Transmis- Transmis- Automatic sion of Transmis- sion of Store data to...
Page 780: Time Stamp Function
Chapter 20 CAN Controller (CAN) 20.14 Time Stamp Function CAN is an asynchronous, serial protocol. All nodes connected to the CAN bus have a local, autonomous clock. As a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may have different frequencies).
Page 781: Baud Rate Settings
Chapter 20 CAN Controller (CAN) Caution The time stamp function using the TSLOCK bit stops toggle of the TSOUT signal by receiving a data frame in message buffer 0. Therefore, message buffer 0 must be set as a receive message buffer. Since a receive message buffer cannot receive a remote frame, toggle of the TSOUT signal cannot be stopped by reception of a remote frame.
Page 782 Chapter 20 CAN Controller (CAN) Table 20-27 shows the combinations of bit rates that satisfy the above conditions. Table 20-27 Settable bit rate combinations (1/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length...
Page 783 Chapter 20 CAN Controller (CAN) Table 20-27 Settable bit rate combinations (2/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1001 64.7 1010 70.6 1011...
Page 784 Chapter 20 CAN Controller (CAN) Table 20-27 Settable bit rate combinations (3/3) CnBTR register setting Valid bit rate setting Sampling value point SYNC PROP PHASE PHASE TSEG1 TSEG2 (unit %) DBT length SEGMENT SEGMENT SEGMENT1 SEGMENT2 [3:0] [2:0] 1000 83.3 1001 91.7 0101...
Page 785: Representative Examples Of Baud Rate Settings
Chapter 20 CAN Controller (CAN) 20.15.2 Representative examples of baud rate settings Table 20-28 and Table 20-29 show representative examples of baud rate settings. Table 20-28 Representative examples of baud rate settings = 8 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud...
Page 786 Chapter 20 CAN Controller (CAN) Table 20-28 Representative examples of baud rate settings = 8 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 787 Chapter 20 CAN Controller (CAN) Table 20-29 Representative examples of baud rate settings = 16 MHz) (1/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 788 Chapter 20 CAN Controller (CAN) Table 20-29 Representative examples of baud rate settings = 16 MHz) (2/2) CANMOD CnBTR register setting Division Valid bit rate setting (unit: kbps) Set baud CnBRP Sampling value ratio of rate value register set point CnBRP Length SYNC...
Page 789: Operation Of Can Controller
Chapter 20 CAN Controller (CAN) 20.16 Operation of CAN Controller The processing procedure for showing in this chapter is recommended processing procedure to operate CAN controller. Develop the program referring to recommended processing procedure in this chapter. START CnGMCS register. CnGMCTRL register (set GOM bit = 1) CnBRP register,...
Page 790 Chapter 20 CAN Controller (CAN) START START Clear Clear OPMODE OPMODE INIT mode? INIT mode? CnBRP register, CnBRP register, CnBTR register CnBTR register CnIE register CnIE register CnMASK register CnMASK register Initialize message buffers Initialize message buffers CnERC and CnINFO CnERC and CnINFO register clear? register clear?
Page 791 Chapter 20 CAN Controller (CAN) START START RDY = 1? RDY = 1? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? CnMCONFm register CnMCONFm register CnMIDHm register, CnMIDHm register, CnMIDLm register CnMIDLm register Transmit message buffer? Transmit message buffer? CnMDLCm register CnMDLCm register...
Page 792 Chapter 20 CAN Controller (CAN) Figure 20-38 shows the processing for a receive message buffer (MT[2:0] bits of CnMCONFm register = 001 to 101 START Clear VALID bit RDY = 1? Clear RDY bit RDY = 0? RSTAT = 0 or Note1 VALID = 1? Note2...
Page 793 Chapter 20 CAN Controller (CAN) Figure 20-39 shows the processing for a transmit message buffer during transmission (MT[2:0] bits of CnMCONFm register = 000 START START Transmit abort process Transmit abort process Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame...
Page 794 Chapter 20 CAN Controller (CAN) Figure 20-40 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000 START START TRQ = 0? TRQ = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame Remote frame...
Page 795 Chapter 20 CAN Controller (CAN) Figure 20-41 shows the processing for a transmit message buffer (MT[2:0] bits of CnMCONFm register = 000 START START ABTTRG = 0? ABTTRG = 0? Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Set CnMDATAxm register Set CnMDATAxm register Set CnMDLCm register...
Page 796 Chapter 20 CAN Controller (CAN) START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnLOPT register Read CnLOPT register Clear RDY bit Clear RDY bit RDY = 0? RDY = 0? Data frame Data frame Remote frame Remote frame Data frame or remote frame?
Page 797 Chapter 20 CAN Controller (CAN) START START Transmit completion Transmit completion Transmit completion interrupt processing interrupt processing interrupt processing Read CnTGPT register Read CnTGPT register TOVF = 1? TOVF = 1? Clear TOVF bit Clear TOVF bit Clear RDY bit Clear RDY bit RDY = 0? RDY = 0?
Page 798 Chapter 20 CAN Controller (CAN) Note Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as TX history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again.
Page 799 Chapter 20 CAN Controller (CAN) START START CINTS0 = 1? CINTS0 = 1? Clear CINTS0 bit Clear CINTS0 bit Read CnTGPT register Read CnTGPT register TOVF = 1? TOVF = 1? Clear TOVF bit Clear TOVF bit Clear RDY bit Clear RDY bit RDY = 0? RDY = 0?
Page 800 Chapter 20 CAN Controller (CAN) Note Also check the MBON flag at the beginning and at the end of the polling routine, in order to check the access to the message buffers as well as TX history list registers, in case a pending sleep mode had been executed. If MBON is detected to be cleared at any check, the actions and results of the processing have to be discarded and processed again, after MBON is set again.
Page 801 Chapter 20 CAN Controller (CAN) START START Clear TRQ bit Clear TRQ bit Wait for 11 CAN data bits Wait for 11 CAN data bits Note Note TSTAT = 0? TSTAT = 0? Read CnLOPT register Read CnLOPT register Message buffer to Message buffer to be aborted matches CnLOPT be aborted matches CnLOPT...
Page 802 Chapter 20 CAN Controller (CAN) START START Clear ABTTRG bit Clear ABTTRG bit ABTTRG = 0? ABTTRG = 0? Clear TRQ bit Clear TRQ bit Wait for 11 CAN data bits Wait for 11 CAN data bits TSTAT = 0? TSTAT = 0? Read CnLOPT register Read CnLOPT register...
Page 803 Chapter 20 CAN Controller (CAN) Figure 20-47 shows the processing to skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START START TSTAT = 0? TSTAT = 0? Clear ABTTRG bit Clear ABTTRG bit ABTTRG = 0? ABTTRG = 0?
Page 804 Chapter 20 CAN Controller (CAN) Figure 20-48 shows the processing to not skip resumption of transmitting a message that was stopped when transmission of an ABT message buffer was aborted. START START Clear TRQ bit of message buffer Clear TRQ bit of message buffer undergoing transmission undergoing transmission Clear ABTTRG bit...
Page 805 Chapter 20 CAN Controller (CAN) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnLIPT register Read CnLIPT register Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm, Read CnMDATAxm, CnMDLCm, CnMIDLm, and CnMIDHm CnMIDLm, and CnMIDHm registers registers DN = 0...
Page 806 Chapter 20 CAN Controller (CAN) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? RHPM = 1? Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm,...
Page 807 Chapter 20 CAN Controller (CAN) Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to check the access to the message buffers as well as reception history list registers, in case a pending sleep mode had been executed.
Page 808 Chapter 20 CAN Controller (CAN) START START Generation of receive Generation of receive completion interrupt completion interrupt Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? RHPM = 1? Read CnMDATAxm, CnMDLCm, Read CnMDATAxm, CnMDLCm, CnMIDLm, CnMIDHm registers...
Page 809 Chapter 20 CAN Controller (CAN) START START CINTS1 = 1? CINTS1 = 1? Clear CINTS1 bit Clear CINTS1 bit Read CnRGPT register Read CnRGPT register ROVF = 1? ROVF = 1? Clear ROVF bit Clear ROVF bit RHPM = 1? Clear DN bit Clear DN bit Read CnMDATAxm, CnMDLCm,...
Page 810 Chapter 20 CAN Controller (CAN) START (when PSMODE[1:0] = 00B) START (when PSMODE[1:0] = 00B) Set PSMODE0 bit Set PSMODE0 bit PSMODE0 = 1? PSMODE0 = 1? CAN sleep mode CAN sleep mode CAN sleep mode Set PSMODE1 bit Set PSMODE1 bit PSMODE1 = 1? PSMODE1 = 1? Request CAN sleep...
Page 811 Chapter 20 CAN Controller (CAN) START CAN stop mode Clear PSMODE1 bit CAN sleep mode Releasing CAN sleep mode by CAN bus activity Releasing CAN sleep mode by user Dominant edge on CAN detected Clear PSMODE0 bit Clear PSMODE0 bit Clear PSMODE0 bit Clear CINTS5 bit Figure 20-54...
Page 812 Chapter 20 CAN Controller (CAN) START BOFF = 1? Clear all TRQ bits Note Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? Set CnCTRL register Set CCERC bit (Set OPMODE) Set CnCTRL register Wait for recovery (Set OPMODE)
Page 813 Chapter 20 CAN Controller (CAN) START BOFF = 1? Clear ABTTRG bit Clear all TRQ bits Note Set CnCTRL register (Clear OPMODE) Access to registers other than CnCTRL and CnGMCTRL registers Forced recovery from bus off? Set CnCTRL register Set CnCTRL register Set CCERC bit (Set OPMODE) (Set OPMODE)
Page 814 Chapter 20 CAN Controller (CAN) START START INIT mode Clear GOM bit GOM = 0? Shutdown successful GOM = 0, EFSD = 0 Figure 20-57 Normal shutdown process START Set EFSD bit Must be a subsequent write Clear GOM bit Clear GOM bit GOM = 0? GOM = 0?
Page 815 Chapter 20 CAN Controller (CAN) START Error interrupt CINTS2 = 1? Check CAN module state (read CnINFO register) Clear CINTS2 bit CINTS3 = 1? CINTS3 = 1? Check CAN protocol error state (read CnLEC register) Clear CINTS3 bit CINTS4 = 1? Clear CINTS4 bit Figure 20-59 Error handling...
Page 816 Chapter 20 CAN Controller (CAN) START Set PSMODE0 bit Clear CINTS5 bit PSMODE0 bit = 1? Clear PSMODE0 bit = 0 CAN sleep mode CINTS5 bit = 1? MBON bit = 0? Set CPU standby mode. Figure 20-60 Setting CPU stand-by (from CAN sleep mode) Caution Before the CPU is set in the CPU standby mode, please check if the CAN sleep mode has been reached.
Page 817 Chapter 20 CAN Controller (CAN) START Set PSMODE0 bit. Set PSMODE0 bit = 1 Clear PSMODE0 bit = 0 PSMODE0 bit = 1? Clear CINTS5 bit. Clear CINTS5 bit = 1 CAN sleep mode Set PSMODE1 bit. Set PSMODE1 bit = 1 Clear PSMODE1 bit = 0 PSMODE1 bit = 1? CAN stop mode...
Page 818: Chapter 21 A/D Converter (Adc)
Chapter 21 A/D Converter (ADC) These microcontrollers contain an n-channel 10-bit A/D Converter. The V850E/Dx3 - DJ3/DL3 microcontrollers feature the following number of analog input channels: µPD70F3427, µPD70F3426A, µPD70F3423, µPD70F3422, µPD70F3425, µPD70F3424 µPD70F3421 Instances Throughout this chapter, the individual channels of the A/D Converter are identified by “n”, for example ADCR0n for the A/D conversion result register of channel n.
Page 819 Chapter 21 A/D Converter (ADC) The block diagram of the A/D Converter is shown below. ADA0CE bit ADA0CE bit ANI0 Sample & hold circuit ANI1 ANI2 ADA0CE bit Voltage comparator ANIn SPCLK0 (16 MHz) ADCR00 INTTZ5UV Controller ADCR01 INTAD ADCR0n ADA0M0 ADA0M1 ADA0M2 ADA0S Internal bus Figure 21-1...
Page 820: Configuration
Chapter 21 A/D Converter (ADC) 21.2 Configuration The A/D Converter includes the following hardware. Table 21-1 Configuration of A/D Converter Item Configuration Analog inputs ANI0 to ANIn pins Registers Successive approximation register (SAR) A/D conversion result registers ADCR00 to ADCR0n A/D conversion result registers ADCR0H0 to ADCR0Hn: only higher 8 bits can be read Control registers...
Page 821 Chapter 21 A/D Converter (ADC) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register nH (ADCR0Hn). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D conversion result register (ADCR0Hn).
Page 822: Adc Registers
Chapter 21 A/D Converter (ADC) 21.3 ADC Registers The A/D Converter is controlled by the following registers: • ADC mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • ADC channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used: •...
Page 823 Chapter 21 A/D Converter (ADC) ADA0M0 - ADC mode register 0 The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations. Access This register can be read/written in 8-bit or 1-bit units. However, bit 0 is read- only.
Page 824 Chapter 21 A/D Converter (ADC) ADA0M1 - ADC mode register 1 The ADA0M1 register is an 8-bit register that controls the conversion time specification. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F201 Initial Value .
Page 825 Chapter 21 A/D Converter (ADC) ADA0M2 - ADC mode register 2 The ADA0M2 register specifies the hardware trigger mode. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F203 Initial Value . This register is cleared by any reset. ADA0TMD1 ADA0TMD0 Caution Be sure to clear bits 7 to 1.
Page 826 Chapter 21 A/D Converter (ADC) ADA0S - ADC channel specification register 0 The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F202 Initial Value...
Page 827 Chapter 21 A/D Converter (ADC) ADCR0n, ADCR0Hn - ADC conversion result registers The ADCR0n and ADCR0Hn registers store the A/D conversion results. Access These registers are read-only, in 16-bit or 8-bit units. However, specify the ADCR0n register for 16-bit access and the ADCR0Hn register for 8-bit access. The 10 bits of the conversion result are read from the higher 10 bits of the ADCR0n register, and 0 is read from the lower 6 bits.
Page 828 Chapter 21 A/D Converter (ADC) The relationship between the analog voltage input to the analog input pins (ANI0 to ANI11) and the A/D conversion result (of A/D conversion result register n (ADCR0n)) is as follows: • ----------------- - 1024 ADCR0 •...
Page 829 Chapter 21 A/D Converter (ADC) ADA0PFM - ADC power-fail compare mode register The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF F204 Initial Value .
Page 830: Operation
Chapter 21 A/D Converter (ADC) 21.4 Operation 21.4.1 Basic operation 1. Set the operation mode, trigger mode, and conversion time for executing A/ D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D Converter waits for a trigger in the external or timer trigger mode.
Page 831: Trigger Mode
Chapter 21 A/D Converter (ADC) 21.4.2 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
Page 832: Operation Modes
Chapter 21 A/D Converter (ADC) 21.4.3 Operation modes Two operation modes are available as the modes in which to set the ANIn pins: continuous select mode and continuous scan mode. The operation mode is selected by the ADA0MD1 and ADA0MD0 bits of the ADA0M0 register.
Page 833 Chapter 21 A/D Converter (ADC) (a) Timing example ANI0 Data 1 Data 5 ANI1 Data 6 Data 2 Data 7 Data 3 ANI2 ANI3 Data 4 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 conversion (ANI0) (ANI1)
Page 834: Power-Fail Compare Mode
Chapter 21 A/D Converter (ADC) 21.4.4 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • If the power-fail compare mode is disabled (ADA0PFM.ADA0PFE = 0), the INTAD signal is generated each time conversion is completed.
Page 835 Chapter 21 A/D Converter (ADC) Continuous scan mode In this mode, the ADC channels starting from ANI0 to the one specified by the ADA0S register are sequentially converted and the conversion results are stored in the ADCR0n registers. Note In continuous scan mode power-fail comparison is performed only on ANI0. After each conversion of ANI0, the higher 8 bits of conversion result in ADA0CR0H0 is compared with the value of the ADA0PFT register.
Page 836 Chapter 21 A/D Converter (ADC) (a) Timing example ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 conversion ANI3 ANI0 ANI1 ANI2 ANI3 ANI0 ANI1 ADCR0n INTAD ADA0PFT ADA0PFT unmatch match (b) Block diagram Analog input pin ADCR0n registers ADCR00 ANI0 ANI1...
Page 837: Cautions
Chapter 21 A/D Converter (ADC) 21.5 Cautions When A/D Converter is not used When the A/D Converter is not used, the power consumption can be reduced by clearing the ADA0CE bit of the ADA0M0 register to 0. Input range of ANIn pins Input the voltage within the specified range to the ANIn pins.
Page 838 Chapter 21 A/D Converter (ADC) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
Page 839: How To Read A/D Converter Characteristics Table
Chapter 21 A/D Converter (ADC) 21.6 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D Converter. Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 840 Chapter 21 A/D Converter (ADC) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D Converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 841 Chapter 21 A/D Converter (ADC) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 0…111 (full scale - 3/2 LSB). Full-scale error 2 AV REF −...
Page 842 Chapter 21 A/D Converter (ADC) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 843: Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D)
Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) The Stepper Motor Controller/Driver module is comprised of six drivers (k = 1 to 6) for external 360° type meters or for bipolar and unipolar stepper motors. The V850E/Dx3 - DJ3/DL3 microcontrollers have following instances of the Stepper Motor Controller/Driver: Stepper-C/D All devices...
Page 844 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) The following figures show the main components of the Stepper Motor Controller/Driver 0 sub-module (Figure 22-1) and of the Stepper Motor Controller/Driver 1 sub-module (Figure 22-2). The Stepper Motor Controller/Driver 0 sub-module is comprised of 4 drivers (k = 1 to 4), Stepper Motor Controller/Driver 1 sub-module is comprised of 2 drivers (k = 5 to 6).
Page 845 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) SPCLK1 SPCLK1/2 SPCLK1/4 SPCLK1/8 SPCLK1 8-bit free-running counter CNT1 SPCLK1/16 (8MHz) SPCLK1/32 SPCLK1/64 SM51 (sin5+) Output SPCLK1/128 1-bit add. Control SM52 (sin5-) 8-bit compare register MCPMn50 circuit SM53 (cos5+) Output 1-bit add. Control SM54 (cos5-) 8-bit compare register MCPMn51 circuit SM61 (sin6+)
Page 846: Stepper Motor Controller/Driver Registers
Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) 22.2 Stepper Motor Controller/Driver Registers The Stepper Motor Controller/Driver is controlled and operated by means of the following registers: Table 22-2 Stepper Motor Controller/Driver registers overview Register name Shortcut Address Timer mode control registers MCNTCn0 <base>...
Page 847 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) MCNTCn0, MCNTCn1 - Timer mode control registers The 8-bit MCNTCnm registers control the operation of the free running up counters CNTm. Access These registers can be read/written in 8-bit or 1-bit units. Address MCNTCn0: <base> MCNTCn1: <base>...
Page 848 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) Caution In register MCNTCn0, bits 3 and 6 must be 0. In register MCNTCn1, bits 3, 6 and 7 must be 0. Power save mode Before entering any power save mode the Stepper-C/D must be shut down in preparation advance in order to minimize power consumption.
Page 849 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) MCMPnk1 - Compare registers for cosine side (k = 1 to 6) The 8-bit MCMPnk1 registers hold the values that define the PWM pulse width for the cosine side of the connected meters. The contents of the registers are continuously compared to the timer counter value: •...
Page 850 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) MCMPCnk - Compare control registers (k = 1 to 6) The 8-bit MCMPCnk registers control the operation of the corresponding compare registers and the output direction of the PWM pin. Access These registers can be read/written in 8-bit units. Address <base>...
Page 851: Operation
Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) 22.3 Operation In the following, the operation of the Stepper Motor Controller/Driver module as a driver for external meters is described. 22.3.1 Stepper Motor Controller/Driver operation This section describes the generation of PWM signals of the driver k for driving external meters.
Page 852 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) Instruction When writing data to compare registers, proceed as follows: 1. Confirm that MCMPCnk.TEN = 0. 2. Write 8-bit PWM data to MCMPnk0 and MCMPnk1. 3. Set MCMPCnk.ADB0 and MCMPCnk.ADB1 as desired. 4. Set MCMPCnk.TEN = 1 to start the counting operation. The data in MCMPnk0/MCMPnk1 will automatically be copied to the compare slave register when the counter overflows.
Page 853 Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) MCMPnkm value N CNTm OVF (overflow) Match signal PWM output Figure 22-3 Output timing without 1-bit addition MCMPnkm value N CNTm OVF (overflow) Match signal PWM output one bit is added ADB0 / ADB1 Figure 22-4 Output timing with 1-bit addition Sequence...
Page 854: Timing
Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) 22.4 Timing This section starts with the timing of the timer counter and general output timing behaviour. Then, examples of output signal generation with and without 1-bit addition are presented. 22.4.1 Timer counter The free running up counter is clocked by the timer count clock selected in register MCNTCnm.
Page 855: Automatic Pwm Phase Shift
Chapter 22 Stepper Motor Controller/Driver (Stepper-C/D) 22.4.2 Automatic PWM phase shift Simultaneous switching of sine and cosine output could lead to a fluctuation of the power supply and increase the susceptibility to electromagnetic interference. To prevent this for drivers 1 to 4, the output signals are automatically shifted by one timer count clock cycle defined in MCNTCn0.
Page 856: Chapter 23 Lcd Controller/Driver (Lcd-C/D)
Chapter 23 LCD Controller/Driver (LCD-C/D) Only the µPD70F3421, µPD70F3422, and µPD70F3423 microcontrollers are provided with the LCD Controller/Driver. This LCD Controller/Driver is suitable for LC displays with up to 160 segments. The supported addressing method of the LCD is multiplex addressing. 23.1 Overview The LCD Controller/Driver generates the signals that are necessary for driving an LCD panel.
Page 857: Description
Chapter 23 LCD Controller/Driver (LCD-C/D) 23.1.1 Description The following figure shows the main components of the LCD Controller/Driver: LCD Clock Selection LCD Frame Frequency Selection LCDCLK LCD0 Prescaler SPCLK7 (125 KHz) Internal Bus SPCLK9 (31.25 KHz) LCD0 LCD0 LCD0 LCD0 Display Data Memory LCD1...
Page 858: Lcd Panel Addressing
Chapter 23 LCD Controller/Driver (LCD-C/D) 23.1.2 LCD panel addressing Each individual segment of an LCD panel is addressed by a signal pair: a segment signal and a common signal. The segment becomes visible when the potential difference of the corresponding common signal and the segment signal reaches or exceeds the LCD drive voltage V Example Figure 23-2 shows how the eight LCD segments of a digit are allocated to...
Page 859: Lcd-C/D Registers
Chapter 23 LCD Controller/Driver (LCD-C/D) 23.2 LCD-C/D Registers The LCD Controller/Driver is controlled by means of the following registers: Table 23-3 LCD Controller/Driver registers overview Register name Shortcut Address LCD clock control register LCDC0 FFFF FB00 LCD mode control register LCDM0 FFFF FB01 LCD display control registers...
Page 860 Chapter 23 LCD Controller/Driver (LCD-C/D) LCDC0 - LCD clock control register The 8-bit LCDC0 register determines the duty cycle frequency f LCD1 Access This register can be read/written in 8-bit or 1-bit units. Address FFFF FB00 Initial Value . This register is cleared by any reset. LCDC03 LCDC02 LCDC01 LCDC00 Table 23-4 LCDC0 register contents...
Page 861 Chapter 23 LCD Controller/Driver (LCD-C/D) Possible frame Table 23-5 lists the possible frame frequencies. The values in Table 23-5 are frequencies only examples. Check “Clock Generator“ on page 130 for details. Selection of the following LCD clocks is provided: • LCDC0.LCDC0[3:2] = 00 LCD clock = LCDCLK = f / d, with...
Page 862 Chapter 23 LCD Controller/Driver (LCD-C/D) LCDM0 - LCD mode control register The 8-bit LCDM0 register enables/disables the LCD operation, activates edge enhancement and selects the power supply. Access This register can be read/written in 8-bit or 1-bit units. Address FFFF FB01 Initial Value .
Page 863: Operation
Chapter 23 LCD Controller/Driver (LCD-C/D) 23.3 Operation The following describes the timing of common and segment signals, the activation of an LCD segment and how edge enhancement can be applied. 23.3.1 Common signals and segment signals This section describes the timing of common signals and segment signals and at which conditions an individual LCD segment becomes visible.
Page 864 Chapter 23 LCD Controller/Driver (LCD-C/D) Segment Signals Segment signals correspond to the contents of the 40 LCD display control registers SEGREG0k. Bits 0 to 3 of these registers are read in synchronization with the common signals COM0 to COM3, this means bit 0 is read in synchronization with common signal COM0 and so on.
Page 865: Activation Of Lcd Segments
Chapter 23 LCD Controller/Driver (LCD-C/D) 23.3.2 Activation of LCD segments An LCD segment becomes visible when the potential difference of the corresponding common signal and segment signal reaches or exceeds the LCD drive voltage V . This is achieved if common and segment signal are at their selection levels.
Page 866: Display Example
Chapter 23 LCD Controller/Driver (LCD-C/D) 23.4 Display Example As a display example, register contents and output signals for a 20-digit LCD display are presented in this section. LCD panel The display pattern of a single digit is given below. Each digit is addressed by two segment signals and four common signals.
Page 867 Chapter 23 LCD Controller/Driver (LCD-C/D) COM3 COM2 COM1 COM0 SEG0 SEGREG000 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32...
Page 868 Chapter 23 LCD Controller/Driver (LCD-C/D) COM0 COM1 COM2 COM3 SEG28 +1/3V COM0-SEG28 –1/3V –V +1/3V COM1-SEG28 –1/3V –V Figure 23-9 4-time-division LCD drive waveforms – examples R01UH0129ED0701 Rev. 7.01 User Manual...
Page 869: Chapter 24 Lcd Bus Interface (Lcd-I/F)
Chapter 24 LCD Bus Interface (LCD-I/F) The LCD Bus Interface connects the internal peripheral bus to an external LCD controller. It provides an asynchronous 8-bit parallel data bus and two control lines. The LCD Bus Interface supports bidirectional communication. You can send data to and query data from the LCD controller.
Page 870: Description
Chapter 24 LCD Bus Interface (LCD-I/F) 24.1.1 Description Data can be read from and written to the LCD Bus Interface by either involving the DMA Controller or by directly accessing the interface from the CPU. The timing of the LCD bus signals is determined by register settings (WST and CYC).
Page 871: Lcd Bus Interface Access Modes
Chapter 24 LCD Bus Interface (LCD-I/F) The LCD bus interface signals are listed in the following table. Table 24-1 LCD Bus Interface external connections Signal Active Reset Function name level level DBWR mod80: Write strobe (WR) mod68: Read/Write (R/W) DBRD mod80: Read strobe (RD) mod68: E strobe (E) DBD[7:0]...
Page 872: Interrupt Generation
Chapter 24 LCD Bus Interface (LCD-I/F) Read operation When the CPU or the DMA reads the LBDATA0 register, the read operation on the LCD Bus Interface is started. If there is a write transfer in progress while the LBDATA0 register shall be read, the read transfer is stalled and started after the write transfer has completed.
Page 873: Lcd Bus Interface Registers
Chapter 24 LCD Bus Interface (LCD-I/F) 24.2 LCD Bus Interface Registers The LCD Bus Interface is controlled and operated by means of the following registers: Table 24-3 LCD Bus Interface registers overview Register name Shortcut Address LCD Bus Interface control register LBCTL0 FFFF FB60 LCD Bus Interface cycle time register...
Page 874 Chapter 24 LCD Bus Interface (LCD-I/F) Table 24-4 LBCTL0 register contents (2/2) Bit position Bit name Function TCIS0 Select interrupt generation 0: During write access to the bus interface, an interrupt is generated as soon as data is transferred from LBDATA0 to the write buffer. During read access from the bus interface, an interrupt is generated as soon as data is available in the LBDATA0 and LBDATAR0 registers.
Page 875 Chapter 24 LCD Bus Interface (LCD-I/F) LBCYC0 - LCD Bus Interface cycle time register The 8-bit LBCYC0 register determines the cycle time of the LCD Bus Interface. The cycle time is the duration of one bus access for transferring one byte. Access This register can be read/written in 8-bit or 1-bit units.
Page 876 Chapter 24 LCD Bus Interface (LCD-I/F) LBWST0 - LCD Bus Interface wait state register The 8-bit LBWST0 register determines the number of wait states of the LCD Bus Interface. The number of wait states defines the duration of the DBWR and DBRD signals.
Page 877 Chapter 24 LCD Bus Interface (LCD-I/F) LBDATA0 - LCD Bus Interface data register The 32-bit LBDATA0 register contains the data that is transferred via the LCD Bus Interface. Access This register can be read/written in 3 different units under following names: •...
Page 878 Chapter 24 LCD Bus Interface (LCD-I/F) Write to this register A write operation to this register sets the busy flag LBCTL0.BYF0 immediately. If there is no LCD bus transfer in progress (LBCTL0.TPF0 = 0), the data is copied to the write buffer and LBCTL0.BYF0 is cleared. If there is a transfer going on (LBCTL0.TPF0 = 1), the data is not copied to the write buffer until the transfer has completed.
Page 879 Chapter 24 LCD Bus Interface (LCD-I/F) LBDATAR0 - LCD Bus Interface data register The LBDATAR0 register is read-only. It contains the data of the last previous read transfer via the LCD Bus Interface. Reading this register does not start a new read transfer on the LCD Bus Interface.
Page 880: Timing
Chapter 24 LCD Bus Interface (LCD-I/F) 24.3 Timing This section starts with the general timing and then presents examples of consecutive write and read operations. 24.3.1 Timing dependencies The following figure shows the general timing when the mod80 mode is used. It illustrates the effect of the LBCYC0 and LBWST0 register settings.
Page 881: Lcd Bus I/F States During And After Accesses
Chapter 24 LCD Bus Interface (LCD-I/F) 24.3.2 LCD Bus I/F states during and after accesses Changing between input and output mode of the LCD bus pins DB[7:0] is done automatically after they are configured as LCD Bus Interface pins via the port configuration registers.
Page 882 Chapter 24 LCD Bus Interface (LCD-I/F) 3. All four bytes of the word are transferred back-to-back via the LCD bus interface. 4. After the transfer on the LCD bus interface has been completed, the LBCTL0.TPF0 is cleared. Writing halfwords Writing a halfword transmits two bytes to the external LCD Controller/Driver. Write 2nd halfword to LBDATA0 register Write 1st halfword to LBDATA0 register SPCLK...
Page 883 Chapter 24 LCD Bus Interface (LCD-I/F) Writing bytes Writing consecutive bytes transmits these bytes to the external LCD controller/ driver. write 3rd byte to LBDATA0 register write 2nd byte to LBDATA0 register write 1st byte to LBDATA0 register SPCLK LBDATA0 1st byte 2nd byte 3rd byte...
Page 884: Reading From The Lcd Bus
Chapter 24 LCD Bus Interface (LCD-I/F) 24.3.4 Reading from the LCD bus You can read from the LCD bus in word, halfword, or byte format. The following shows typical sequences of reading words and bytes. Reading words Reading a word requires the transmission of four bytes. Dummy read word from LBDATA0 register Read word from LBDATA0 register SPCLK...
Page 885 Chapter 24 LCD Bus Interface (LCD-I/F) Reading bytes The following figure shows a byte read operation in mod68 mode. Read 3rd byte from LBDATAR0 register without initiating a new transfer Read 2nd byte from LBDATA0 register Read 1st byte from LBDATA0 register Dummy read byte from LBDATA0 register SPCLK 1st Byte...
Page 886: Write-Read-Write Sequence On The Lcd Bus
Chapter 24 LCD Bus Interface (LCD-I/F) 24.3.5 Write-Read-Write sequence on the LCD bus Figure 24-8 shows an example when a write access to the LCD bus is immediately followed by a read access and vice versa. The example is given in mod80 mode (LBCTL0.IMD0 = 0) with byte transfers.
Page 887: Cautions
Chapter 24 LCD Bus Interface (LCD-I/F) 24.4 Cautions 24.4.1 Polling of LBCTL0.TPF0 flag may indicate wrong status Though the LBCTL0.TPF0 flag is intented to determine the current status of the LCD bus data transfer, reading of this flag may indicate a wrong status by accident.
Page 888 Chapter 24 LCD Bus Interface (LCD-I/F) µPD70F3425 PCC.CKS[1:0] = 11B µPD70F3426A (CPU system clock (VBCLK) = PLLCLK/2 = 16 MHz) LBCTL0.LBC0[1:0] = 00B or 01B (LCD bus clock = SPCLK0 = 16 MHz, or LCD bus clock = SPCLK1 = 8 MHz) µPD70F3427 Avoidance of critical clock settig is not possible.
Page 889 Chapter 24 LCD Bus Interface (LCD-I/F) Table 24-14 Clock combinations of µPD70F3425 LCD bus clock CPU system clock LBCTL0.LBC0[1:0] SCPS.SPSPS[2:0] SCPS.VBSPS[2:0] 00B or 010B 001B, 011B, 101B, 111B (SSCCLK or SSCCLK/3 (SSCCLK/2, SSCCLK/4, SSCCKL/6, SSCCLK/8) valid when SSCCLK ≤ 010B not permitted (SPCLK0 = SSCG (SSCG...
Page 890 Chapter 24 LCD Bus Interface (LCD-I/F) Table 24-15 Clock combinations of µPD70F3426A LCD bus clock CPU system clock LBCTL0.LBC0[1:0] SCPS.SPSPS[2:0] SCPS.VBSPS[2:0] 00B or 010B 001B, 011B, 101B, 111B (SSCCLK or SSCCLK/3 (SSCCLK/2, SSCCLK/4, SSCCKL/6, SSCCLK/8) valid when SSCCLK ≤ 010B not permitted (SPCLK0 = SSCG (SSCG...
Page 891: Chapter 25 Sound Generator (Sg)
Chapter 25 Sound Generator (SG) The Sound Generator (SG0) generates an audio-frequency tone signal and a high-frequency pulse-width modulated (PWM) signal. The duty cycle of the PWM signal defines the volume. By default, the two signal components are routed to separate pins. But both signals can also be combined to generate a composite signal that can be used to drive a loudspeaker circuit.
Page 892: Description
Chapter 25 Sound Generator (SG) 25.1.1 Description The following figure provides a functional block diagram of the Sound Generator. SG0CLK = Clear Clear PCLK0 9-bit S0GFH 9-bit SG0FH 9-bit S0GFL (16MHz) tone counter Tone frequency counter (32 to 64 kHz) Match Match SG0CTL.PWR...
Page 893: Principle Of Operation
Chapter 25 Sound Generator (SG) If bit SG0CTL.OS is set, pin SGO provides the composite signal SG0O that can directly control a speaker circuit. 25.1.2 Principle of operation The software-controlled registers SG0FL, SG0FH, and SG0PWM are equipped with hardware buffers. The Sound Generator operates on these buffers.
Page 894 Chapter 25 Sound Generator (SG) After low-pass filtering, the analog signal amplitude corresponds to the duty cycle of the PWM signal. Low-pass filtering (averaging) is an inherent characteristic of a loudspeaker system. The duty cycle can vary between 0 % and 100 %. Its generation is controlled by the counter register SG0FL and the volume register SG0PWM.
Page 895: Sound Generator Registers
Chapter 25 Sound Generator (SG) 25.2 Sound Generator Registers The Sound Generator is controlled by means of the following registers: Table 25-1 Sound Generator registers overview Register name Shortcut Address SG0 frequency low register SG0FL <base> SG0 frequency high register SG0FH <base>...
Page 896 Chapter 25 Sound Generator (SG) SG0FL - SG0 frequency low register The 16-bit SG0FL register is used to specify the target value for the PWM frequency. It holds the target value for the 9-bit counter SG0FL. Access This register is can be read/written in 16-bit units. It cannot be written if bit SG0CTL.PWR = 0.
Page 897 Chapter 25 Sound Generator (SG) SG0FH - SG0 frequency high register The 16-bit SG0FH register is used to specify the final tone frequency. It holds the target value for the 9-bit counter SG0FH. Access This register is can be read/written in 16-bit units. It cannot be written if bit SG0CTL.PWR = 0.
Page 898 Chapter 25 Sound Generator (SG) SG0PWM - SG0 volume register The 16-bit register SG0PWM is used to specify the sound volume. It holds the target value for the sound amplitude that is given by the duty cycle of the PWM signal.
Page 899 Chapter 25 Sound Generator (SG) SG0SDF - SG0 sound duration factor register The 8-bit register SG0SDF is used to specify the duration of the sound when the ALD is switched on. It defines the number of tone signal edges between two successive volume reductions.
Page 900 Chapter 25 Sound Generator (SG) SG0ITH - SG0 interrupt threshold register The 16-bit register SG0ITH is used to specify the volume level for the interrupt request INTSG0. When the ALD is switched on, the sound volume is stepwise reduced. This is done by reducing the value of the volume buffer.
Page 901: Sound Generator Operation
Chapter 25 Sound Generator (SG) 25.3 Sound Generator Operation This section explains the details of the Sound Generator. 25.3.1 Generating the tone The tone signal is generated by the compare match signal of the SG0FH counter value with the value of the SG0FH buffer, followed by a by-two-divider. At each compare match, the counter is reset to zero.
Page 902: Generating The Volume Information
Chapter 25 Sound Generator (SG) Tone frequency calculation The tone frequency can be calculated as: / (([SG0FL buffer] + 1) × ([SG0FH buffer] + 1) × 2) tone SG0CLK where: = frequency of the SG0 input clock SG0CLK [SG0FL buffer] = contents of the SG0FL buffer [SG0FH buffer] = contents of the SG0FH buffer Example –...
Page 903 Chapter 25 Sound Generator (SG) Note To achieve 100 % duty cycle for all PWM frequencies, SGOFL must not be set to a value above 1FE The PWM signal is continually low when the value of the volume buffer is zero —...
Page 904 Chapter 25 Sound Generator (SG) PWM calculations PWM frequency The PWM frequency is generated by the counter SG0FL. It can be calculated / (([SG0FL buffer] + 1) SG0CLK where: = frequency of the SG0 input clock SG0CLK [SG0FL buffer] = contents of the SG0FL buffer Duty cycle The duty cycle of the PWM signal is calculated as follows: •...
Page 905 Chapter 25 Sound Generator (SG) Automatic fading The built-in automatic logarithmic decrement function (ALD) can be used to reduce the volume gradually to zero without CPU intervention. The logarithmic decrease matches the sensitivity of the human ear and creates the impression of a linearly decaying sound.
Page 906 Chapter 25 Sound Generator (SG) The following settings are assumed: – f = 16 MHz SG0CLK – [SG0FL] = 332 (this yields a PWM frequency of 48.048 KHz) – [SG0PWM] = 333 (100 % volume) – a) [SG0FH] = 3 (this yields a tone frequency of 6.006 KHz) –...
Page 907: Sound Generator Application Hints
Chapter 25 Sound Generator (SG) 25.4 Sound Generator Application Hints This section provides supplementary programming information. 25.4.1 Initialization To enable the Sound Generator, set SG0CTL.PWR to 1. This connects the SG0 to the clock SG0CLK. Check bit SG0CTL.OS. When SG0CTL.OS is 0, the signal at pin SGO is a symmetrical square waveform with the frequency f .
Page 908: Constant Sound Volume
Chapter 25 Sound Generator (SG) 25.4.5 Constant sound volume A sound started with SG0CTL.ALDS = 0 is output with the volume value written to SG0PWM. The sound is output continually and does not stop automatically. It has to be stopped by writing 0000 to the SG0PWM register.
Page 909: Chapter 26 Power Supply Scheme
Chapter 26 Power Supply Scheme The microcontroller has general power supply pins for its core, internal memory and peripherals. These pins are connected to internal voltage regulators. The microcontroller also has dedicated power supply pins for certain I/O modules. These pins provide the power for the I/O operations. 26.1 Overview The following table gives the naming convention of the pins: Dedicated function...
Page 910 Chapter 26 Power Supply Scheme The following pins belong to the Power Supply Scheme: Table 26-1 Power supply pins Connected to µPD70F3421, µPD70F3422, µPD70F3424, µPD70F3425, µPD70F3427 µPD70F3423 µPD70F3426A VDD50 / CPU core VSS50 Pin pair is connected to voltage regulator 0. REGC0 Capacitor for voltage regulator 0 for pin pair VDD50 / VSS50.
Page 911: Description
Chapter 26 Power Supply Scheme 26.2 Description 26.2.1 Devices µPD70F3421, µPD70F3422, µPD70F3423 Figure 26-1 gives an overview of the allocation of power supply pins of the µPD70F3421, µPD70F3422, µPD70F3423 devices. Their functional assignment is depicted in more detail in Figure 26-2. Note The diagrams do not show the exact pin location.
Page 912: Devices Μpd70F3424, Μpd70F3425, Μpd70F3426A
Chapter 26 Power Supply Scheme 26.2.2 Devices µPD70F3424, µPD70F3425, µPD70F3426A Figure 26-3 gives an overview of the allocation of power supply pins of the µPD70F3424, µPD70F3425, µPD70F3426A devices. Their functional assignment is depicted in more detail in Figure 26-4. Note The diagrams do not show the exact pin location.
Page 913: Device Μpd70F3427
Chapter 26 Power Supply Scheme 26.2.3 Device µPD70F3427 Figure 26-5 gives an overview of the allocation of power supply pins of the µPD70F3427 devices. Their functional assignment is depicted in more detail in Figure 26-6. Note The diagrams do not show the exact pin location. LCD Bus I/F I/O Ext.
Page 914: Voltage Regulators
Chapter 26 Power Supply Scheme 26.3 Voltage regulators The on-chip voltage regulators generate the voltages for the internal circuitry (CPU core, clock generation circuit and peripherals), refer to Figure 26-2, Figure 26-4 and Figure 26-6. The regulators operate per default in all operation modes (normal operation, HALT, IDLE, STOP, WATCH, Sub-WATCH, and during RESET).
Page 915: Chapter 27 Reset
Chapter 27 Reset Several system reset functions are provided in order to initialize hardware and registers. 27.1 Overview Features summary A reset can be caused by the following events: • External reset signal RESET Noise in the external reset signal is eliminated by an analog filter. •...
Page 916: General Reset Performance
Chapter 27 Reset 27.1.1 General reset performance The following figure shows the signals involved in the reset function: Internal bus RESPOC: RESSTAT = 01 RESSTAT RESEXT: RESSTAT = 02 RESPOC RESET RESCMM SYSRES SYSRESWDT RESCMS RESWDT RESSW Figure 27-1 Reset function signal diagram All resets are applied asynchronously.
Page 917 Chapter 27 Reset Hardware status With each reset function the hardware is initialized (including the watchdog). When the reset status is released, program execution is started. The following table describes the status of the clocks during reset and after reset release. Note that the clock status "operates" does not inevitably mean that any function using this clock source operates as well.
Page 918 Chapter 27 Reset Register status With each reset function the registers of the CPU, internal RAM, and on-chip peripheral I/Os are initialized. Since after reset the internal firmware is processed, some resources hold a different value as after reset, when the user’s program is started. After a reset, make sure to set the registers to the values needed within your program.
Page 919: Reset At Power-On
Chapter 27 Reset Note In the table above, “Undefined” means either undefined at the time of a power-on reset, or undefined due to data destruction when the falling edge of the external RESET signal corrupts an ongoing RAM write access. The internal RAM of the microcontroller comprises several separate RAM blocks.
Page 920: External Reset
Chapter 27 Reset 27.1.3 External RESET Reset is performed when a low level signal is applied to the RESET pin. The reset status is released when the signal applied to the RESET pin changes from low to high. After the external RESET is released, the RESSTAT register is cleared and the RESSTAT.RESEXT bit is set (RESSTAT = 02 , refer also to “RESSTAT - Reset source flag register“...
Page 921: Reset By Watchdog Timer
Chapter 27 Reset 27.1.4 Reset by Watchdog Timer The Watchdog Timer can be configured to generate a reset if the watchdog time expires. After watchdog reset, the RESSTAT.RESWDT bit is set. The system reset signal SYSRES is generated. After Watchdog Timer overflow, the reset status lasts for a specific time. Then the reset status is automatically released.
Page 922: Reset Registers
Chapter 27 Reset 27.2 Reset Registers The reset functions are controlled and operated by means of the following registers: Table 27-3 Reset function registers overview Register name Shortcut Address Reset source flag register RESSTAT FFFF FF20 Software reset register RESSWT FFFF FF22 Software reset enable register RESCMD...
Page 923 Chapter 27 Reset Table 27-4 RESSTAT register contents (2/2) Bit position Bit name Function RESCM1 Reset by Clock Monitor of main oscillator 0: Not generated. 1: Generated. RESEXT External RESET 0: Not generated. 1: Generated. RESPOC Reset at Power-On-Clear 0: Not generated. 1: Generated.
Page 924 Chapter 27 Reset RESCMD - Software reset enable register Immediately after writing data to the 8-bit RESCMD register, write access to the RESSWT register is enabled. The content of data written to RESCMD register is not relevant. The register is always read as 00 Access This register can only be written in 8-bit units.
Page 925: Chapter 28 Voltage Comparator
Chapter 28 Voltage Comparator The microcontroller has two instances of a Voltage Comparator. Note Throughout this chapter, the individual instances of the Voltage Comparator are identified by “n”, for example INTVCn for the generated interrupt signal. 28.1 Overview The Voltage Comparator compares an external voltage V at pin VCMPn CMPn and the internal reference voltage V...
Page 926: Description
Chapter 28 Voltage Comparator 28.1.1 Description Each Voltage Comparator consists of an operation amplifier and a logic block. The operation amplifier is connected to the external voltage (V ) with one CMPn input and to an internal reference voltage (V ) with the other.
Page 927: Voltage Comparator Registers
Chapter 28 Voltage Comparator 28.2 Voltage Comparator Registers The Voltage Comparator is controlled by means of the following registers: Table 28-1 Voltage Comparator registers overview Register name Shortcut Address Voltage Comparator n control register VCCTLn <base> Voltage Comparator n status register VCSTRn <base>...
Page 928 Chapter 28 Voltage Comparator Caution If the voltage comparator input level V is below the reference voltage V CMPn an INTVCn interrupt is generated under both following conditions: → • The comparator is enabled (VCCTLn.VCEn = 0 1) and falling or both edges are specified (VCCTLn.VCEn = 00 or 11 →...
Page 929: Timing
Chapter 28 Voltage Comparator 28.3 Timing The following figure shows the timing of the Voltage Comparator. In this example, the interrupt INTVCn is generated at the falling edge (VCCTLn.ESTn[1:0] = 00 ) of the comparator’s output signal. External voltage Internal reference voltage Time Delay...
Page 930: Chapter 29 On-Chip Debug Unit
Chapter 29 On-Chip Debug Unit The microcontroller includes an on-chip debug unit. By connecting an N-Wire emulator, on-chip debugging can be executed. 29.1 Functional Outline 29.1.1 Debug functions Debug interface Communication with the host machine is established by using the DRST, DCK, DMS, DDI, and DDO signals via an N-Wire emulator.
Page 931 Chapter 29 On-Chip Debug Unit Debug monitor function A memory space for debugging that is different from the user memory space is used during debugging (background monitor mode). The user program can be executed starting from any address. While execution of the user program is aborted, the user resources (such as memory and I/O) can be read and written, and the user program can be downloaded.
Page 932: Security Function
Chapter 29 On-Chip Debug Unit 29.1.2 Security function This microcontroller has a N-Wire security function, that demands the user to input an ID code upon start of the debugger. The ID code is compared to a predefined ID code, written in advance to the internal flash memory by an external flash programmer.
Page 933 Chapter 29 On-Chip Debug Unit Security disable The entire ID code, i.e. also the security bit 7 of address 0000 0079 , can be made temporarily ineffective by software. This is achieved by setting the control bit RSUDISC.DIS = 1. Setting RSUDISC.DIS = 1 does not change the security bit.
Page 934 Chapter 29 On-Chip Debug Unit RSUDISCP - RSUDISC write protection register The 8-bit RSUDISCP register protects the register RSUDISC from inadvertent write access. After data has been written to the RSUDISCP register, the first write access to register RSUDISC is valid. All subsequent write accesses are ignored. Thus, the value of RSUDISC can only be rewritten in a specified sequence, and illegal write access is inhibited.
Page 935: Controlling The N-Wire Interface
Chapter 29 On-Chip Debug Unit 29.2 Controlling the N-Wire Interface The N-Wire interface pins DRST, DDI, DDO, DCK, DMS are shared with port functions, see Table 29-2. During debugging the respective device pins are forced into the N-Wire interface mode and port functions are not available. Note that N-Wire debugging must be generally permitted by the security bit in the ID code region (*0x0000 0079[bit7] = 1) of the flash memory.
Page 936 Chapter 29 On-Chip Debug Unit External RESET External reset by the RESET pin sets OCDM.OCDM0 = 1, i.e. the pins are defined as N-Wire interface pins. If connected the debugger can communicate with the on-chip debug unit and take over CPU control. During and after RESET the pins P05, P52…P55 are configured as follows: •...
Page 937: N-Wire Enabling Methods
Chapter 29 On-Chip Debug Unit 29.3 N-Wire Enabling Methods 29.3.1 Starting normal operation after RESET and RESPOC For “normal operation” it has to be assured that the pins P05, P52…P55 are available as port pins after either reset event. Therefore the software has to perform OCDM.OCDM0 = 0 to make the pins available as port pins after RESET.
Page 938: N-Wire Activation By Reset Pin
Chapter 29 On-Chip Debug Unit RESET Application software “1” RESPOC sets OCDM.OCDM0 = 1 “0 ” OCDM0 Debugger starts PC = 0 P05/DRST XXXXXXXXXXXXXXX reset normal operation debug Figure 29-2 Start with N-Wire activation 29.3.3 N-Wire activation by RESET pin The N-Wire interface can also be activated after power up by keeping RESET active for at least 2 sec after RESPOC release.
Page 939: Connection To N-Wire Emulator
Chapter 29 On-Chip Debug Unit 29.4 Connection to N-Wire Emulator To connect the N-Wire emulator, a connector for emulator connection and a connection circuit must be mounted on the target system. As a connector example the KEL connector is described in more detail. Other connectors, like for instance MICTOR connector (product name: 2-767004-2, Tyco Electronics AMP K.K.), are available as well.
Page 940 Chapter 29 On-Chip Debug Unit Pin configuration Figure 29-5 shows the pin configuration of the connector for emulator connection (target system side), and Table 29-3 on page 941 shows the pin functions. Figure 29-5 Pin configuration of connector for emulator connection (target system side) Caution Evaluate the dimensions of the connector when actually mounting the...
Page 941 Chapter 29 On-Chip Debug Unit Pin functions The following table shows the pin functions of the connector for emulator connection (target system side). “I/O” indicates the direction viewed from the device. Table 29-3 Pin functions of connector for emulator connection (target system side) Pin no.
Page 942 Chapter 29 On-Chip Debug Unit Example of recommended circuit An example of the recommended circuit of the connector for emulator connection (target system side) is shown below. V850E/Dx3 KEL connector 8830E-026-170S Note 3 (Reserved 1) (Reserved 2) (Reserved 3) (Reserved 4) (Reserved 5) (Reserved 6) Note 1...
Page 943: Restrictions And Cautions On On-Chip Debug Function
Chapter 29 On-Chip Debug Unit 29.5 Restrictions and Cautions on On-Chip Debug Function • Do not mount a device that was used for debugging on a mass-produced product (this is because the flash memory was rewritten during debugging and the number of rewrites of the flash memory cannot be guaranteed). •...
Page 944 2B23 for constant data placement. In case using Renesas’ directive files, which are part of the device file package, this is the default assignment. If the program requires less constant data than that address space offers, modify the linker directive file in a way, that program code does not start before the address 2B24 R01UH0129ED0701 Rev.
Page 945: Appendix A Registers Access Times
Appendix A Registers Access Times This chapter provides formulas to calculate the access time to registers, which are accessed via the peripheral I/O areas. All accesses to the peripheral I/O areas are passed over to the NPB bus via the VSB - NPB bus bridge BBR. Read and write access times to registers via the NPB depend on the register, the system clock VBCLK and the setting of the VSWC register.
Page 946: Timer P
Appendix A Registers Access Times A.1 Timer P Register TPnCCR0, TPnCCR1 Access ⎧ ⎫ VBCLK ⋅ ⋅ SUWL VSWL ------------------------------------------------------ - VSWL ------------------ ⎨ ⎬ Formula ⋅ VSWL ⎩ ⎭ PCLK0 VBCLK Access ⋅ ⎧ ⎫ VBCLK ⋅ ⋅ ------------------------------------------------------ - ------------------ SUWL VSWL...
Page 947 Appendix A Registers Access Times Register TZnR Access ⋅ SUWL VSWL ------------------ Formula VBCLK Access ⋅ ⋅ ------------------ ----------------- - SUWL 3 VSWL Formula VBCLK PCLK2 Register TZnCTL Access ⋅ ------------------ SUWL VSWL Formula VBCLK A.3 Timer Y Register TYnCNT0 Access ⋅...
Page 948 Appendix A Registers Access Times Access ⎧ ⎫ VBCLK ⋅ ⋅ ---------------------------------------------------------- ------------------ SUWL VSWL VSWL ⎨ ⎬ Formula ⋅ VSWL ⎩ ⎭ SPCLK0 VBCLK Access W (no write access during timer operation) ⋅ SUWL VSWL ------------------ Formula VBCLK Register GCCn[5:0] Access ⎧...
Page 949 Appendix A Registers Access Times ⋅ ⋅ ------------------ SUWL 3 VSWL Formula VBCLK Register all other Access ⋅ ------------------ SUWL VSWL Formula VBCLK A.6 Watch Calibration Timer Register CR01 Access ⋅ SUWL VSWL ------------------ Formula VBCLK Access Read-Modify-Write ⋅ ⋅ ------------------ SUWL 3 VSWL...
Page 950 Appendix A Registers Access Times A.9 Clocked Serial Interface (CSIB) Register Access ⋅ SUWL VSWL ------------------ Formula VBCLK A.10 I C Bus Register IICSn Access ⋅ ⋅ SUWL 3 VSWL ------------------ Formula VBCLK Register all other Access ⋅ SUWL VSWL ------------------ Formula VBCLK...
Page 951 Appendix A Registers Access Times Formula VBCLK ⎧ ⎫ ----------------------- - ⎪ ⎪ CANMOD ⋅ ⋅ ⋅ SUWL VSWL ru 4 --------------------------------- - VSWL ------------------ ⎨ ⎬ VSWL ⎪ ⎪ VBCLK ⎩ ⎭ Register all other Access Formula VBCLK ⎧ ⎫...
Page 952 Appendix A Registers Access Times A.14 LCD Controller/Driver Register Access ⋅ ------------------ SUWL VSWL Formula VBCLK A.15 LCD Bus Interface Register Access ⋅ ------------------ SUWL VSWL Formula VBCLK A.16 Sound Generator Register SG0FL, SG0FH, SG0PWM Access ⋅ SUWL VSWL ------------------ Formula VBCLK Access...
Page 953 Appendix A Registers Access Times Access ⋅ ------------------ SUWL VSWL Formula VBCLK Register all other Access ⋅ ------------------ SUWL VSWL Formula VBCLK A.18 All other Registers Register Access ⋅ ------------------ SUWL VSWL Formula VBCLK R01UH0129ED0701 Rev. 7.01 User Manual...
Page 954 Appendix B Special Function Registers The following tables list all registers that are accessed via the NPB (Peripheral bus). The registers are called “special function registers” (SFR). Table B-1 lists all CAN special function registers. The addresses are given as offsets to programmable peripheral base address (refer to “CAN module register and message buffer addresses“...
Page 955 Appendix B Special Function Registers Table B-1 CAN special function registers (2/4) Address Initial Register name Shortcut offset value 0x056 CAN0 Module Interrupt Enable register low byte C0IEL R/W R/W 0x00 0x057 CAN0 Module Interrupt Enable register high byte C0IEH R/W R/W 0x00 0x058...
Page 956 Appendix B Special Function Registers Table B-1 CAN special function registers (3/4) Address Initial Register name Shortcut offset value 0x654 CAN1 Module Error Counter C1ERC 0x0000 0x656 CAN1 Module Interrupt Enable register C1IE 0x0000 0x656 CAN1 Module Interrupt Enable register low byte C1IEL R/W R/W 0x00...
Page 957 Appendix B Special Function Registers Table B-1 CAN special function registers (4/4) Address Initial Register name Shortcut offset value 0xC52 CAN2 Module Last Error Code register C2LEC R/W R/W 0x00 0xC53 CAN2 Module Information register C2INFO 0x00 0xC54 CAN2 Module Error Counter C2ERC 0x0000 0xC56...
Page 958 Appendix B Special Function Registers B.2 Other Special Function Registers Table B-2 Other special function registers (1/20) Initial Address Register name Shortcut value 0xFFFFF060 CPU: Chip Area Select Control register 0 CSC0 0x2C11 0xFFFFF062 CPU: Chip Area Select Control register 1 CSC1 0x2C11 0xFFFFF064...
Page 959 Appendix B Special Function Registers Table B-2 Other special function registers (2/20) Initial Address Register name Shortcut value 0xFFFFF103 Interrupt Mask register 1H IMR1H R/W R/W 0xFF 0xFFFFF104 Interrupt Mask register 2 IMR2 0xFFFF 0xFFFFF104 Interrupt Mask register 2L IMR2L R/W R/W 0xFF 0xFFFFF105...
Page 960 Appendix B Special Function Registers Table B-2 Other special function registers (3/20) Initial Address Register name Shortcut value 0xFFFFF144 Interrupt control register of INTTP2CC0 TP2CC0IC R/W R/W 0x47 0xFFFFF146 Interrupt control register of INTTP2CC1 TP2CC1IC R/W R/W 0x47 0xFFFFF148 Interrupt control register of INTTP3OV TP3OVIC R/W R/W 0x47...
Page 961 Appendix B Special Function Registers Table B-2 Other special function registers (4/20) Initial Address Register name Shortcut value 0xFFFFF196 Interrupt control register of INTDMA1 DMA1IC R/W R/W 0x47 0xFFFFF198 Interrupt control register of INTDMA2 DMA2IC R/W R/W 0x47 0xFFFFF19A Interrupt control register of INTDMA3 DMA3IC R/W R/W 0x47...
Page 962 Appendix B Special Function Registers Table B-2 Other special function registers (5/20) Initial Address Register name Shortcut value 0xFFFFF205 ADC power fail threshold register ADA0PFT R/W R/W 0x00 0xFFFFF210 ADC result register channel 0 ADCR00 undefined 0xFFFFF211 ADC result register high byte channel 0 ADCR0H0 undefined 0xFFFFF212...
Page 963 Appendix B Special Function Registers Table B-2 Other special function registers (6/20) Initial Address Register name Shortcut value 0xFFFFF312 Port Drive strength control register P9 PDSC9 R/W R/W 0x00 0xFFFFF314 Port Drive strength control register P10 PDSC10 R/W R/W 0x00 0xFFFFF344 Port LCD control register P2 PLCDC2...
Page 964 Appendix B Special Function Registers Table B-2 Other special function registers (7/20) Initial Address Register name Shortcut value 0xFFFFF3AC Port input level control register P6 PILC6 R/W R/W 0x00 0xFFFFF3AE Port input level control register P7 PILC7 0x0000 0xFFFFF3AE Port input level control register P7 low byte PILC7L R/W R/W 0x00...
Page 965 Appendix B Special Function Registers Table B-2 Other special function registers (8/20) Initial Address Register name Shortcut value 0xFFFFF406 Port register port 3 R/W R/W 0x00 0xFFFFF408 Port register port 4 R/W R/W 0x00 0xFFFFF40A Port register port 5 R/W R/W 0x00 0xFFFFF40C Port register port 6 R/W R/W...
Page 966 Appendix B Special Function Registers Table B-2 Other special function registers (9/20) Initial Address Register name Shortcut value 0xFFFFF456 Port mode control register port 11 PMC11 R/W R/W 0x00 0xFFFFF458 Port mode control register port 12 PMC12 R/W R/W 0x00 0xFFFFF45A Port mode control register port 13 PMC13 R/W R/W...
Page 967 Appendix B Special Function Registers Table B-2 Other special function registers (10/20) Initial Address Register name Shortcut value 0xFFFFF592 Watchdog timer security register WCMD R/W R/W undefined 0xFFFFF594 Watchdog timer mode register WDTM R/W R/W 0x00 0xFFFFF596 Watchdog timer error register WPHS R/W R/W 0x00...
Page 968 Appendix B Special Function Registers Table B-2 Other special function registers (11/20) Initial Address Register name Shortcut value 0xFFFFF602 TMZ0 non-synchronized counter read register TZ0CNT1 0x0000 0xFFFFF604 TMZ0 counter reload register TZ0R 0x0000 0xFFFFF606 TMZ0 control register TZ0CTL R/W R/W 0x00 0xFFFFF608 TMZ1 Synchronized counter read register...
Page 969 Appendix B Special Function Registers Table B-2 Other special function registers (12/20) Initial Address Register name Shortcut value 0xFFFFF662 TMP0 timer-specific I/O control register 0 TP0IOC0 R/W R/W 0x00 0xFFFFF663 TMP0 timer-specific I/O control register 1 TP0IOC1 R/W R/W 0x00 0xFFFFF664 TMP0 timer-specific I/O control register 2 TP0IOC2...
Page 970 Appendix B Special Function Registers Table B-2 Other special function registers (13/20) Initial Address Register name Shortcut value 0xFFFFF6A4 Output control register TMG 0 low byte OCTLG0L R/W R/W 0x44 0xFFFFF6A5 Output control register TMG 0 high byte OCTLG0H R/W R/W 0x44 0xFFFFF6A6 Time base status register TMG 0 TMGST0...
Page 971 Appendix B Special Function Registers Table B-2 Other special function registers (14/20) Initial Address Register name Shortcut value 0xFFFFF6EC Capture / Compare register 0 TMG 2 GCC20 0x0000 0xFFFFF6EE Capture / Compare register 1 TMG 2 GCC21 0x0000 0xFFFFF6F0 Capture / Compare register 2 TMG 2 GCC22 0x0000 0xFFFFF6F2...
Page 972 Appendix B Special Function Registers Table B-2 Other special function registers (15/20) Initial Address Register name Shortcut value 0xFFFFF848 VFB flash/ROM correction address register 2 CORAD2 R/W 0x00000000 0xFFFFF848 VFB flash/ROM correction address register 2L CORAD2L 0x0000 0xFFFFF84A VFB flash/ROM correction address register 2H CORAD2H 0x0000 0xFFFFF84C VFB flash/ROM correction address register 3...
Page 973 Appendix B Special Function Registers Table B-2 Other special function registers (16/20) Initial Address Register name Shortcut value 0xFFFFF8BA VSB flash correction address register 6H COR2AD6H 0x0000 0xFFFFF8BC VSB flash correction address register 7 COR2AD7 R/W 0x00000000 0xFFFFF8BC VSB flash correction address register 7L COR2AD7L 0x0000 0xFFFFF8BE VSB flash correction address register 7L...
Page 974 Appendix B Special Function Registers Table B-2 Other special function registers (17/20) Initial Address Register name Shortcut value 0xFFFFF927 VFB flash/ROM correction address register 5HH CORADR5HH 0x00 0xFFFFF930 VFB flash/ROM correction value register 0L CORVAL0L 0x0000 0xFFFFF932 VFB flash/ROM correction value register 0H CORVAL0H 0x0000 0xFFFFF934...
Page 975 Appendix B Special Function Registers Table B-2 Other special function registers (18/20) Initial Address Register name Shortcut value 0xFFFFFB25 LCD RAM data SEGREG005 R/W R/W 0x00 0xFFFFFB25 LCD RAM data SEGREG025 R/W R/W 0x00 0xFFFFFB26 LCD RAM data SEGREG006 R/W R/W 0x00 0xFFFFFB26 LCD RAM data SEGREG026...
Page 976 Appendix B Special Function Registers Table B-2 Other special function registers (19/20) Initial Address Register name Shortcut value 0xFFFFFCA8 Self-programming enable protection register SELFENP undefined 0xFFFFFCAA Stand-by control protection register STBCTLP undefined 0xFFFFFCB0 CLMM write protection register PRCMDCMM undefined 0xFFFFFCB2 CLMS write protection register PRCMDCMS undefined 0xFFFFFD00 CSIB0 control register 0...
Page 977 Appendix B Special Function Registers Table B-2 Other special function registers (20/20) Initial Address Register name Shortcut value 0xFFFFFD94 IIC1 clock selection register IICCL1 R/W R/W 0x00 0xFFFFFD95 IIC1 function expansion register IICX1 R/W R/W 0x00 0xFFFFFD96 IIC1 state register IICS1 0x00 0xFFFFFD97 IIC1 state register (for emulation only)
Page 978 Revision History The following revision list shows all functional changes of this document R01UH0129ED0701 compared to the previous manual version R01UH0129ED0601 (date published Oct 21, 2010). Chapter Page Description internal RAM size of µPD70F3422 corrected new note for meaning of identifier "n" inserted limitation of LCD bus I/F read/write strobe pins (DBRD, DBWR) to µPD70F3424, µPD70F3425, µPD70F3426A and µPD70F3427 removed missing table of write protected register inserted...
Page 979 Index Baud rate generator Numerics CSIB 599 16-bit data busses UARTA 560 Access to 310 BCC 283 8-bit data busses BCTn 279 Access to 304 BCU (Bus Control Unit) 258 BCU registers 270 BEC 277 A/D conversion result register Hn BMC 284 (ADCR0Hn) 820, 827 Boundary operation conditions 267...
Page 980 Index CANn message configuration register m CLMS 168 (CnMCONFm) 744 CLMS write protection register CANn message control register m (PRCMDCMS) 169 (CnMCTRLm) 747 Clock Generator 130, 178 CANn message data byte register Default setup 190 (CnMDATAxm) 741 Operation 189 CANn message data length register m Registers 137 (CnMDLCm) 743 Start conditions 135...
Page 981 Index CnTRXIC 215 CTPSW 113 CnTS 739 CnWUPIC 215 DADCn 325 Combined compare control registers Data access order 304 (MCMPnkHW) 849 Data address space Command protection register (PHCMD) 141 Recommended use 125 Command register (PRCMD) 164, 236 Data busses Common signals (LCD Controller/Driver) 863 Access order 304 Compare control registers (MCMPCnk) 850 Data space 119...
Page 982 Index DMA source address registers Ln (DSALn) 321 via N-Wire 246 DMA Transfer Count Registers n (DBCn) 324 with flash programmer 247 DMA Trigger Source Select Register n FOUTCLK control register (FCC) 157 (DTFRn) 329 DMAnIC 215 GCCn0 468 DRST 328 GCCn5 468 DSAHn 320 GCCnm 469...
Page 983 Index IICFn 622 Activation of segments 865 IICn 628 Panel addressing 858 IICnIC 215 LCD Bus Interface 869 IICSn 619 Access modes 871 IICX0n 625 Interrupt generation 872 Illegal opcode Registers 873 Definition 229 Timing 880 Images in address space 117 LCD Bus Interface control register (LBCTL) 873 IMRn 219 LCD Bus Interface cycle time register...
Page 984 Index Normal operation mode 116 PFSR2 49 N-Wire PFSR3 50 Code protection 362 PHCMD 141 Connection to emulator 939 PHS 142 Controlling the interface 935 Physical address space 117 emulator 930 PICCn 43 Enabling methods 937 PILCn 44 Flash programming 246 Pin functions 29 ID code 932 After reset/in stand-by modes 101...
Page 985 Index PRCMD 164, 236 CORADRnL 352 PRCMDCMM 167 ROM correction control registers PRCMDCMS 169 COR2CN 359 PRCn 42 CORCN 358 Prescaler compare registers (PRSCMn) 600 CORCTL0 351 Prescaler mode registers (PRSMn) 600 CORCTL1 351 PRM0 521 ROM Correction Function 344 Processor clock control register (PCC) 143 DBTRAP operation and program flow 357 Program counter (PC) 111...
Page 986 Index Software reset register (RESSWT) 923 Basic Operation 471 Sound Generator 891 Control registers 462 Application hints 907 Edge Noise Elimination 493 Operation 901 Match and Clear Mode 483 Registers 895 Operation in Free-Run Mode 473 SPCLK control register (SCC) 156 Output Delay Operation 470 Special clocks 133 Precautions 494...
Page 987 Index TMGn0 467 TZnUVIC 215 TMGn1 467 TMGSTn 467 UAnCTL0 540 TMP (Timer/event counter P) 366 UAnCTL1 561 TMPn capture/compare register 0 UAnCTL2 562 (TPnCCR0) 376 UAnOPT0 542 TMPn capture/compare register 1 (TPnCCR1) 378 UAnREIC 215 TMPn control register 0 (TPnCTL0) 370 UAnRIC 215 TMPn control register 1 (TPnCTL1) 371 UAnRX 545...
Page 988 Index Registers 512 Watch Timer clock control register (TCC) 154 Watch Timer operation 516 Start-Up 517 Steady operation 516 Watchdog Timer 527 Clock 528 Registers 530 Watchdog Timer clock control register (WCC) 152 Watchdog Timer clock selection register (WDCS) 531 Watchdog Timer command protection register (WCMD) 534 Watchdog Timer command status register...
Page 989 SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
Page 990 V850E/Dx3 - DJ3/DL3 R01UH0129ED0701, Rev. 7.01...

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