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7542 Group
b 7
b 0
S e r i a l I / O 2 s t a t u s r e g i s t e r
( S I O 2 S T S : a d d r e s s 0 0 2 F
T r a n s m i t b u f f e r e m p t y f l a g ( T B E )
0 : B u f f e r f u l l
1 : B u f f e r e m p t y
R e c e i v e b u f f e r f u l l f l a g ( R B F )
0 : B u f f e r e m p t y
1 : B u f f e r f u l l
T r a n s m i t s h i f t c o m p l e t i o n f l a g ( T S C )
0 : T r a n s m i t s h i f t i n p r o g r e s s
1 : T r a n s m i t s h i f t c o m p l e t e d
O v e r r u n e r r o r f l a g ( O E )
0 : N o e r r o r
1 : O v e r r u n e r r o r
P a r i t y e r r o r f l a g ( P E )
0 : N o e r r o r
1 : P a r i t y e r r o r
F r a m i n g e r r o r f l a g ( F E )
0 : N o e r r o r
1 : F r a m i n g e r r o r
S u m m i n g e r r o r f l a g ( S E )
0 : ( O E ) U ( P E ) U ( F E ) = 0
1 : ( O E ) U ( P E ) U ( F E ) = 1
N o t u s e d ( r e t u r n s " 1 " w h e n r e a d )
b 7
b0
U A R T 2 c o n t r o l r e g i s t e r
(UART2CON : address 0031
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
Not used (return "0" when read)
(Do not write "1" to this bit.)
Not used (return "1" when read)
Fig. 64 Structure of serial I/O2-related registers
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
, i n i t i a l v a l u e : 8 0
)
1 6
1 6
, initial value: E0
16
Page 54 of 134
b 7
b 0
S e r i a l I / O 2 c o n t r o l r e g i s t e r
( S I O 2 C O N : a d d r e s s 0 0 3 0
BRG count source selection bit (CSS)
0: f(X
1: f(X
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
S
RDY2
0: P0
1: P0
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O2 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P0
1: Serial I/O2 enabled
(pins P0
)
16
, i n i t i a l v a l u e : 0 0
1 6
)
IN
)/4
IN
output enable bit (SRDY)
pin operates as ordinary I/O pin
7
pin operates as S
output pin
7
RDY2
to P0
operate as ordinary I/O pins)
4
7
to P0
operate as serial I/O pins)
4
7
)
1 6
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