Renesas 78K0/FB2-L User Manual
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Renesas 78K0/FB2-L User Manual

Renesas 78K0/FB2-L User Manual

78k0/fx2-l 8-bit single-chip microcontrollers
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78K0/Fx2-L
8
8-Bit Single-Chip Microcontrollers
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
www.renesas.com
User's Manual: Hardware
Rev.2.03 Jun 2012

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Summary of Contents for Renesas 78K0/FB2-L

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
  • Page 4 • 78K0/FY2-L: PD78F0854, 78F0855, 78F0856 μ • 78K0/FA2-L: PD78F0857, 78F0858, 78F0859 μ • 78K0/FB2-L: PD78F0864, 78F0865 Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The manual for the 78K0/Fx2-L microcontrollers is separated into two parts: this manual and the instructions edition (common to the 78K0 microcontrollers).
  • Page 5 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/Fx2-L User’s Manual U19856E 78K/0 Series Instructions User’s Manual U12326E 78K0 Microcontrollers User’s Manual Self Programming Library Type 01 U18274E 78K0 Microcontrollers Self Programming Library Type 01 Ver.
  • Page 6 Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual” website (http://www2.renesas.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.

  • Page 7: Table Of Contents

    1.2 Ordering Information........................17 1.3 Pin Configuration (Top View) ...................... 19 1.3.1 78K0/FY2-L (16 pins)......................... 19 1.3.2 78K0/FA2-L (20 pins)......................... 20 1.3.3 78K0/FB2-L (30 pins)......................... 21 1.4 Block Diagram ..........................22 1.4.1 78K0/FY2-L (16 pins)......................... 22 1.4.2 78K0/FA2-L (20 pins)......................... 23 1.4.3 78K0/FB2-L (30 pins).........................
  • Page 8 3.3.4 Register addressing........................... 71 3.4 Operand Address Addressing ....................71 3.4.1 Implied addressing..........................71 3.4.2 Register addressing........................... 72 3.4.3 Direct addressing..........................73 3.4.4 Short direct addressing........................74 3.4.5 Special function register (SFR) addressing ..................75 3.4.6 Register indirect addressing ......................76 3.4.7 Based addressing ..........................
  • Page 9 CHAPTER 6 16-BIT TIMERS X0 AND X1 ..................159 6.1 Functions of 16-bit Timers X0 and X1 ..................159 6.2 Configuration of 16-bit Timers X0 and X1................161 6.3 Registers Controlling 16-bit Timers X0 and X1 ............... 166 6.4 Operation of 16-Bit Timer/Event Counter 00................182 6.5 Operation of PWM output operation of 16-Bit Timers X0 and X1 ..........
  • Page 10 CHAPTER 10 WATCHDOG TIMER ..................... 329 10.1 Functions of Watchdog Timer....................329 10.2 Configuration of Watchdog Timer ..................330 10.3 Register Controlling Watchdog Timer..................331 10.4 Operation of Watchdog Timer....................332 10.4.1 Controlling operation of watchdog timer ..................332 10.4.2 Setting overflow time of watchdog timer ..................333 10.4.3 Setting window open period of watchdog timer................
  • Page 11 14.4 I C Bus Mode Functions ......................450 14.4.1 Pin configuration ..........................450 14.4.2 Setting transfer clock by using IICWL and IICWH registers............451 14.5 I C Bus Definitions and Control Methods ................452 14.5.1 Start conditions ..........................452 14.5.2 Addresses............................453 14.5.3 Transfer direction specification ......................
  • Page 12 18.1.1 Standby function ..........................558 18.1.2 Registers controlling standby function ................... 559 18.2 Standby Function Operation ....................561 18.2.1 HALT mode............................ 561 18.2.2 STOP mode ........................... 565 CHAPTER 19 RESET FUNCTION......................573 19.1 Register for Confirming Reset Source ................... 582 CHAPTER 20 POWER-ON-CLEAR CIRCUIT..................
  • Page 13 CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) ........ 673 CHAPTER 29 PACKAGE DRAWINGS ....................699 29.1 78K0/FY2-L ..........................699 29.2 78K0/FA2-L..........................700 29.3 78K0/FB2-L..........................701 CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS............702 CHAPTER 31 CAUTIONS FOR WAIT....................703 31.1 Cautions for Wait........................703 31.2 Peripheral Hardware That Generates Wait ................
  • Page 14 A.4.1 When using in-circuit emulator ......................710 A.4.2 When using on-chip debug emulator with programming function QB-MINI2 ........710 A.5 Debugging Tools (Software)..................... 710 APPENDIX B REVISION HISTORY ..................... 711 B.1 Major Revisions in This Edition ....................711 B.2 Revision History of Preceding Editions .................. 712 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 15: Chapter 1 Outline

     Timer • 16-bit timer X … PWM output, operation in conjunction with an external signal, synchronous output of up to four channels (available only in 78K0/FB2-L), A/D conversion trigger generation • 16-bit timer/event counter … PPG output, capture input, external event counter input •...
  • Page 16  Multiplier (8 bits × 8 bits = 16 bits, 16 bits × 16 bits = 32 bits, 1-clock operation)  10-bit resolution A/D conversion • 78K0/FY2-L: 4 ch • 78K0/FA2-L: 6 ch • 78K0/FB2-L: 9 ch  Comparator • 78K0/FY2-L: 1 ch • 78K0/FA2-L: 3 ch •...

  • Page 17: Ordering Information

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.2 Ordering Information [Part Number] μ PD78F08xy ΔΔ × - ××× -× Semiconductor Lead- Product contains no lead in any area (Terminal free finish is Ni/Pd/Au plating) Quality Grade = −40 to +85°C) Special (T = −40 to +125°C) Special (T ΔΔ...
  • Page 18 PD78F0854MAA-FAA-G, 78F0855MAA-FAA-G, 78F0856MAA-FAA-G, (5.72 mm (225)) 78F0854MAA2-FAA-G, 78F0855MAA2-FAA-G, 78F0856MAA2-FAA-G μ 78K0/FA2-L 20-pin plastic SSOP PD78F0857MCA-CAA-G, 78F0858MCA-CAA-G, 78F0859MCA-CAA-G, (7.62 mm (300)) 78F0857MCA2-CAA-G, 78F0858MCA2-CAA-G, 78F0859MCA2-CAA-G μ 78K0/FB2-L 30-pin plastic SSOP PD78F0864MCA-CAB-G, 78F0865MCA-CAB-G, (7.62 mm (300)) 78F0864MCA2-CAB-G, 78F0865MCA2-CAB-G R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 19: Pin Configuration (Top View)

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 78K0/FY2-L (16 pins) • 16-pin plastic SSOP (5.72 mm (225)) P60/SCLA0/TxD6 P61/SDAA0/RxD6 ANI0/P20 RESET ANI1/P21 P122/X2/EXCLK/TOOLD0 ANI2/P22 P121/X1/TOOLC0 ANI3/P23/CMP2+ REGC P00/TI000/INTP0 P01/TO00/TI010 P30/TOH1/TI51/INTP1 ANI0 to ANI3: Analog Input RESET: Reset Analog Reference RxD6: Receive Data...

  • Page 20: K0/Fa2-L (20 Pins)

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.3.2 78K0/FA2-L (20 pins) • 20-pin plastic SSOP (7.62 mm (300)) ANI5/P25/CMP1+ ANI0/P20 ANI4/P24/CMP0+ ANI1/P21 P60/SCLA0/TxD6 ANI2/P22 P61/SDAA0/RxD6 ANI3/P23/CMP2+ RESET P122/X2/EXCLK/TOOLD0 P00/TI000/INTP0 P121/X1/TOOLC0 P01/TI010/TO00 REGC P30/TOH1/TI51/INTP1 P31/TOX00/INTP2/TOOLC1 P32/TOX01/INTP3/TOOLD1 ANI0 to ANI5: Analog Input RESET: Reset Analog Reference RxD6: Receive Data Voltage...

  • Page 21: K0/Fb2-L (30 Pins)

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.3.3 78K0/FB2-L (30 pins) • 30-pin plastic SSOP (7.62 mm (300)) ANI8/P70 ANI6/P26/CMPCOM ANI5/P25/CMP1+ ANI7/P27 ANI4/P24/CMP0+ P60/SCLA0/TxD6 P61/SDAA0/RxD6 ANI0/P20 P02/SSI11/INTP5 ANI1/P21 RESET ANI2/P22 P122/X2/EXCLK/TOOLD0 ANI3/P23/CMP2+ P00/TI000/INTP0 P121/X1/TOOLC0/<TI000>/<INTP0> REGC P01/TO00/TI010 P30/TOH1/TI51/INTP1 P31/TOX00/INTP2/TOOLC1 P37/SO11 P32/TOX01/INTP3/TOOLD1 P36/SI11 P33/TOX10 P35/SCK11...

  • Page 22: Block Diagram

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.4 Block Diagram 1.4.1 78K0/FY2-L (16 pins) PORT 0 P00, P01 16-bit TIMER X0 PORT 2 P20-P23 TO00/TI010/P01 16-bit TIMER/ EVENT COUNTER 00 TI000/P00 RxD6/P61<LINSEL> PORT 3 TI51/P30 8-bit TIMER 51 PORT 6 P60, P61 PORT 12 P121, P122 TOH1/P30 8-bit TIMER H1...

  • Page 23: K0/Fa2-L (20 Pins)

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.4.2 78K0/FA2-L (20 pins) TOX00/P31 16-bit TIMER X0 PORT 0 P00, P01 TOX01/P32 PORT 2 P20-P25 TO00/TI010/P01 16-bit TIMER/ EVENT COUNTER 00 TI000/P00 PORT 3 RxD6/P61<LINSEL> P30-P32 TI51/P30 8-bit TIMER 51 PORT 6 P60, P61 PORT 12 P121, P122 TOH1/P30 8-bit TIMER H1...

  • Page 24: K0/Fb2-L (30 Pins)

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.4.3 78K0/FB2-L (30 pins) TOX00/P31 PORT 0 P00 to P02 16-bit TIMER X0 TOX01/P32 PORT 2 P20 to P27 TOX10/P33 16-bit TIMER X1 TOX11/P34 PORT 3 P30 to P37 TO00/TI010/P01 16-bit TIMER/ <TI000>/P121 EVENT COUNTER 00...

  • Page 25: Outline Of Functions

    78K0/Fx2-L CHAPTER 1 OUTLINE 1.5 Outline of Functions (1/2) Item 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L 16 pins 20 pins 30 pins Internal Flash memory 4 KB to 16 KB 8 KB and 16 KB memory (self-programming supported) High-Speed RAM 384 bytes to 768 bytes...
  • Page 26 78K0/Fx2-L CHAPTER 1 OUTLINE (2/2) Item 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L 16 pins 20 pins 30 pins Serial UART6 1 ch interface IICA 1 ch CSI11 – 1 ch 10-bit A/D converter 4 ch 6 ch 9 ch Comparator 1 ch 3 ch 8 bits ×...

  • Page 27: Chapter 2 Pin Functions

    Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins Note P20 to P27, P70 Note Pins other than P20 to P27, P70 Note 78K0/FY2-L: P20 to P23 78K0/FA2-L: P20 to P25 78K0/FB2-L: P20 to P27, P70 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 28: K0/Fy2-L

    78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS 2.1.1 78K0/FY2-L (1) Port functions: 78K0/FY2-L Function Name Function After Reset Alternate Function Port 0. Input port TI000/INTP0 2-bit I/O port. TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
  • Page 29 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 78K0/FY2-L Function Name Function After Reset Alternate Function ANI0 Input A/D converter analog input Analog input ANI1 ANI2 ANI3 CMP2+ Input Comparator input Analog input P23/ANI31 INTP0 Input External interrupt request input for which the valid edge Input port P00/TI000 (rising edge, falling edge, or both rising and falling...

  • Page 30: K0/Fa2-L

    78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS 2.1.2 78K0/FA2-L (1) Port functions: 78K0/FA2-L Function Name Function After Reset Alternate Function Port 0. Input port TI000/INTP0 2-bit I/O port. TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
  • Page 31 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/FA2-L (2/2) Function Name Function After Reset Alternate Function CMP0+ Input Comparator input Analog input P24/ANI4 CMP1+ P25/ANI5 CMP2+ P21/ANI1 INTP0 Input External interrupt request input for which the valid edge Input port P00/TI000 (rising edge, falling edge, or both rising and falling...

  • Page 32: K0/Fb2-L

    78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS 2.1.3 78K0/FB2-L (1) Port functions: 78K0/FB2-L Function Name Function After Reset Alternate Function Port 0. Input port TI000/INTP0 3-bit I/O port. TO00/TI010 Input/output can be specified in 1-bit units. SSI11/INTP5 Use of an on-chip pull-up resistor can be specified by a software setting.
  • Page 33 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/FB2-L (1/2) Function Name Function After Reset Alternate Function ANI0 Input A/D converter analog input Analog input ANI1 ANI2 ANI3 P23/CMP2+ ANI4 P24/CMP0+ ANI5 P25/CMP1+ ANI6 P26/CMPCOM ANI7 ANI8 CMP0+ Input...
  • Page 34 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/FB2-L (2/2) Function Name Function After Reset Alternate Function SCK11 Clock input/output for CSI11 Input port SI11 Input Serial data input to CSI11 SO11 Output Serial data output from CSI11 SSI11...

  • Page 35: Description Of Pin Functions

    2.2.1 P00 to P02 (port 0) P00 to P02 function as an I/O port. These pins also function as timer I/O, external interrupt request input, and chip select input. 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) P00/TI000/INTP0 P00/TI000/INTP0 P00/TI000 P01/TO00/TI010 P01/TO00/TI010 P01/TO00/TI010 −...

  • Page 36: P20 To P27 (Port 2)

    CHAPTER 2 PIN FUNCTIONS 2.2.2 P20 to P27 (port 2) P20 to P27 function as an I/O port. These pins also function as pins for A/D converter analog input and comparator input. 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) P20/ANI0 P20/ANI0 P20/ANI0 P21/ANI1 P21/ANI1...

  • Page 37: P30 To P37 (Port 3)

    P30 to P37 function as an I/O port. These pins also function as pins for external interrupt request input, timer I/O, clock input and data I/O for flash memory programmer/on-chip debugger, and clock input and data I/O for serial interface. 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) P30/TOH1/TI51/INTP1 P30/TOH1/TI51/INTP1 P30/TOH1/TI51/INTP1 −...
  • Page 38 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS SCK11 This is a serial clock I/O pin of serial interface CSI11. SI11 This is a serial data input pin of serial interface CSI11. (k) SO11 This is a serial data output pin of serial interface CSI11. Remark For how to connect a flash memory programmer using TOOLC1/P31, TOOLD1/P32, refer to CHAPTER 24 FLASH MEMORY.

  • Page 39: P60 And P61 (Port 6)

    Output from the P60 and P61 pins can be specified as normal CMOS output or N-ch open-drain output (V tolerance) in 1-bit units, using port output mode register 6 (POM6). 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) P60/SCLA0/TxD6 P60/SCLA0/TxD6 P60/SCLA0/TxD6 P61/SDAA0/RxD6...

  • Page 40: P70 (Port 7)

    2.2.5 P70 (port 7) P70 functions as an I/O port. This pin also functions as the pin for A/D converter analog input. 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) − − P70/ANI8 The following operation modes can be specified in 1-bit units.
  • Page 41 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS (1) Port mode P121 and P122 function as an input port. (2) Control mode P121 and P122 function as pins for external interrupt request input, connecting resonator for main system clock, external clock input for main system clock, timer input, and clock input and data I/O for flash memory programmer/on- chip debugger.

  • Page 42: Reset

    78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS 2.2.7 AV , AV 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) − − (a) AV This is the A/D converter reference voltage input pin and the positive power supply pin of port 2 and A/D converter.

  • Page 43: Pin I/O Circuits And Recommended Connection Of Unused Pins

    78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Tables 2-2 to 2-4 show the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
  • Page 44 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types (78K0/FA2-L) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P00/TI000/INTP0 5-AQ Input: Independently connect to V or V via a resistor. Output: Leave open. P01/TO00/TI010 ANI0/P20 11-G <Digital input setting>...
  • Page 45 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS Table 2-4. Pin I/O Circuit Types (78K0/FB2-L) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P00/TI000/INTP0 5-AQ Input: Independently connect to V or V via a resistor. Output: Leave open. P01/TO00/TI010 P02/SSI11/INTP5 ANI0/P20 11-G <Digital input setting>...
  • Page 46 78K0/Fx2-L CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List Type 2 Type 5-AG pullup P-ch enable data P-ch IN/OUT output N-ch Schmitt-triggered input with hysteresis characteristics disable input enable Type 5-AQ Type 5-AS pullup P-ch enable pullup P-ch enable CMOS/N-ch OD data...

  • Page 47: Chapter 3 Cpu Architecture

    Table 3-1. Set Values of Internal Memory Size Switching Register (IMS) Products ROM Capacity Internal High-Speed RAM Capacity 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L μ μ − PD78F0854 PD78F0857 4 KB 384 bytes μ...
  • Page 48 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE μ Figure 3-1. Memory Map ( PD78F0854, 78F0857) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H FEFFH General-purpose registers 32 × 8 bits FEE0H FEDFH Internal high-speed RAM 384 ×...
  • Page 49 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE μ Figure 3-2. Memory Map ( PD78F0855, 78F0858, 78F0864) F F F F H Special function registers 1FFFH (SFR) 1FFFH 256 × 8 bits Program area F F 0 0 H FEFFH General-purpose 108FH registers 108EH On-chip debug security 32 ×...
  • Page 50 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE μ Figure 3-3. Memory Map ( PD78F0856, 78F0859, 78F0865) F F F F H 3FFFH Special function registers (SFR) 1FFFH 256 × 8 bits Program area F F 0 0 H FEFFH General-purpose 108FH registers 108EH On-chip debug security 32 ×...

  • Page 51: Internal Program Memory Space

    The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/Fx2-L microcontrollers incorporate internal ROM (flash memory), as shown below. Table 3-3. Internal ROM Capacity Product Internal ROM 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L Structure Capacity μ μ − 4096 × 8 bits PD78F0854...
  • Page 52 Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-4. Vector Table Vector Table Interrupt Source 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L Address 16 Pins 20 Pins 30 Pins √...

  • Page 53: Internal Data Memory Space

    3.1.2 Internal data memory space 78K0/Fx2-L microcontrollers incorporate the following RAMs. (1) Internal high-speed RAM Table 3-5. Internal High-Speed RAM Capacity Internal High-Speed Product 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L μ μ 384 × 8 bits − PD78F0854 PD78F0857 (FD80H to FEFFH) μ...

  • Page 54: Data Memory Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/Fx2-L microcontrollers, based on operability and other considerations.
  • Page 55 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Correspondence Between Data Memory and Addressing μ PD78F0855, 78F0858, 78F0864) F F F F H Special function registers SFR addressing (SFR) 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H FEFFH General-purpose...
  • Page 56 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing μ PD78F0856, 78F0859, 78F0865) F F F F H Special function registers SFR addressing (SFR) 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H FEFFH General-purpose...

  • Page 57: Processor Registers

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/Fx2-L microcontrollers incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
  • Page 58 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts.
  • Page 59 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H Register pair higher FEDFH FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
  • Page 60 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH...

  • Page 61: General-Purpose Registers

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).

  • Page 62: Special Function Registers (Sfrs)

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
  • Page 63 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (1/5) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − √ √ √ FF00H Port register 0 √...
  • Page 64 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (2/5) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − √ √ √ FF2EH A/D port configuration register 0 ADPC0 √...
  • Page 65 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (3/5) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits − √ √ √ √ √ FF70H Multiplication input data register A MULA MULAL −...
  • Page 66 78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (4/5) Address Special Function Register (SFR) Symbol Manipulatable Bit Unit After Name Reset 1 Bit 8 Bits 16 Bits − √ − √ √ √ FF99H Watchdog timer enable register WDTE 1AH/ Note...
  • Page 67 2. Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding to each product as indicated below after release of reset. Products Internal High-Speed RAM Capacity Capacity 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L μ μ − PD78F0854 PD78F0857 4 KB 384 bytes μ...

  • Page 68: Instruction Address Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.

  • Page 69: Immediate Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.

  • Page 70: Table Indirect Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.

  • Page 71: Register Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during...

  • Page 72: Register Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

  • Page 73: Direct Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. [Operand format] Identifier Description...

  • Page 74: Short Direct Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

  • Page 75: Special Function Register (Sfr) Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.

  • Page 76: Register Indirect Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces.

  • Page 77: Based Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.

  • Page 78: Based Indexed Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.

  • Page 79: Stack Addressing

    78K0/Fx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.

  • Page 80: Chapter 4 Port Functions

    Pins other than P20 to P27, P70 Note 78K0/FY2-L: P20 to P23 78K0/FA2-L: P20 to P25 78K0/FB2-L: P20 to P27, P70 78K0/Fx2-L microcontrollers are provided with digital I/O ports, which enable variety of control operations. functions of each port are shown in Tables 4-2 to 4-4.
  • Page 81 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (78K0/FY2-L) Function Name Function After Reset Alternate Function Port 0. Input port TI000/INTP0 2-bit I/O port. TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
  • Page 82 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Functions (78K0/FA2-L) Function Name Function After Reset Alternate Function Port 0. Input port TI000/INTP0 2-bit I/O port. TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
  • Page 83 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-4. Port Functions (78K0/FB2-L) Function Name Function After Reset Alternate Function Port 0. Input port TI000/INTP0 3-bit I/O port. TO00/TI010 Input/output can be specified in 1-bit units. SSI11/INTP5 Use of an on-chip pull-up resistor can be specified by a software setting.

  • Page 84: Port Configuration

    • 78K0/FY2-L: Total: 11 (CMOS I/O: 9, CMOS input: 2) Port • 78K0/FA2-L: Total: 15 (CMOS I/O: 13, CMOS input: 2) • 78K0/FB2-L: Total: 24 (CMOS I/O: 22, CMOS input: 2) • 78K0/FY2-L: Total: 5 Pull-up resistor • 78K0/FA2-L: Total: 7 •...

  • Page 85: Port 0

    78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) P00/TI000/INTP0 P00/TI000/INTP0 P00/TI000/INTP0 P01/TO00/TI010 P01/TO00/TI010 P01/TO00/TI010 − − P02/SSI11/INTP5 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0).
  • Page 86 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 87 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 PU02 P-ch Alternate function PORT Output latch P02/SSI11/INTP5 (P02) PM02 Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 88: Port 2

    To use P20/ANI0 to P27/ANI7 as a digital input or a digital output, it is recommended to select a pin to use starting with the furthest pin from AV (for example, the P24/CMP0+/ANI4 pin in the 78K0/FB2-L). To use P20/ANI0 to P27/ANI7 as an analog input, it is recommended to select a pin to use starting with the closest pin to AV (for example, the P27/ANI7 pin in the 78K0/FB2-L).
  • Page 89 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-7. Setting Functions of P21/ANI1 Pin ADPC0 PM2 Register ADS Register P21/ANI1 Pin Register Digital I/O Input mode Selects ANI1. Setting prohibited selection Does not select ANI1. Digital input Output mode Selects ANI1. Setting prohibited Does not select ANI1.
  • Page 90 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-9. Setting Functions of P26/ANI6/CMPCOM Pin ADPC0 PM2 Register CmMODSEL1 CmMODSEL0 ADS Register P26/ANI6/CMPCOM Pin Register bit (m = 0 to 2) bit (m = 0 to 2) − Digital I/O Input mode Selects ANI6. Setting prohibited selection Does not select ANI6.
  • Page 91 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P20 to P22 and P27 PORT Output latch P20/ANI0 to (P20 to P22, P27) P22/ANI2 and P27/ANI7 PM20-PM22, PM27 A/D converter Figure 4-5. Block Diagram of P23 PORT Output latch P23/ANI3/CMP2+ (P23) PM23...
  • Page 92 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P24 PORT Output latch P24/ANI4/CMP0+ (P24) PM24 A/D converter Comparator 0 (+) input Figure 4-7. Block Diagram of P25 PORT Output latch P25/ANI5/CMP1+ (P25) PM25 A/D converter Comparator 1 (+) input Port register 2 PM2: Port mode register 2...
  • Page 93 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P26 PORT Output latch P26/ANI6/CMPCOM (P26) PM26 A/D converter Comparator common (-) input R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 94: Port 3

    Figures 4-9 to 4-16 show block diagrams of port 3. Caution To use P35/SCK11 and P37/SO11 of 78K0/FB2-L as general-purpose ports, set serial operation mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to the default status (00H).
  • Page 95 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P30 PU30 P-ch Alternate function PORT Output latch P30/TOH1/TI51/INTP1 (P30) PM30 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 96 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P31 PU31 P-ch Alternate function PORT Output latch P31/TOX00/INTP2/TOOLC1 (P31) PM31 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 97 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P32 PU32 P-ch Alternate function PORT Output latch P32/TOX01/INTP3/TOOLD1 (P32) PM32 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 98 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P33 PU33 P-ch PORT Output latch P33/TOX10 (P33) PM33 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 99 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P34 PU34 P-ch Alternate function PORT Output latch P34/TOX11/INTP4 (P34) PM34 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 100 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P35 PU35 P-ch Alternate function PORT Output latch P35/SCK11 (P35) PM35 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 101 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P36 PU36 P-ch Alternate function PORT Output latch P36/SI11 (P36) PM36 Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 102 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P37 PU37 P-ch PORT Output latch P37/SO11 (P37) PM37 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 103: Port 6

    This port can also be used for serial interface data I/O and clock I/O. Reset signal generation sets port 6 to input mode. Caution To use P60/SCLA0/TxD6 of 78K0/FY2-L, 78K0/FA2-L, and 78K0/FB2-L as general-purpose port, clear bit 0 (TXDLV6) of asynchronous serial interface control register 6 (ASICL6) to 0 (normal output of TxD6).
  • Page 104 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P60 PU60 P-ch PIM6 Alternate function PIM60 POM6 POM60 PORT Output latch P60/SCLA0/TxD6 (P60) PM60 Alternate function Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PIM6: Port input mode register 6 POM6: Port output mode register 6...
  • Page 105 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P61 PU61 P-ch PIM6 Alternate function PIM61 POM6 POM61 PORT Output latch P61/SDAA0/RxD6 (P61) PM61 Alternate function Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 PIM6: Port input mode register 6 POM6: Port output mode register 6...

  • Page 106: Port 7

    CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 7 78K0/FY2-L (16-pin) 78K0/FA2-L (20-pin) 78K0/FB2-L (30-pin) − − P70/ANI8 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7).
  • Page 107 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P70 PORT Output latch P70/ANI8 (P70) PM70 A/D converter Port register 7 PM7: Port mode register 7 Read signal WR××: Write signal R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 108: Port 12

    78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 12 78K0/FY2-L (16 Pins) 78K0/FA2-L (20 Pins) 78K0/FB2-L (30 Pins) P121/X1/TOOLC0 P121/X1/TOOLC0 P121/X1/TOOLC0/<TI000>/<INTP0> P122/X2/EXCLK/TOOLD0 P122/X2/EXCLK/TOOLD0 P122/X2/EXCLK/TOOLD0 Remark Functions in angle brackets < > can be assigned by setting the input switch control register (MUXSEL).
  • Page 109 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P121 and P122 OSCCTL OSCSEL P122/X2/EXCLK/TOOLD0 OSCCTL EXCLK, OSCSEL P121/X1/TOOLC0 (78K0/FY2-L, 78K0/FA2-L) P121/X1/TOOLC0/<TI000>/<INTP0> (78K0/FB2-L) Note MUXSEL INTP0SEL0 TM00SEL0 Alternate function MUXSEL: Port alternate switch control register OSCCTL: Clock operation mode select register Read signal WR××:...

  • Page 110: Registers Controlling Port Function

    • Port alternate switch control register (MUXSEL) Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 111 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-21. Format of Port Mode Register (78K0/FY2-L) Symbol Address After reset PM01 PM00 FF20H Note Note Note Note PM23 PM22 PM21 PM20 FF22H PM30 FF23H FF26H PM61 PM60 PMmn Pmn pin I/O mode selection (m = 0, 2, 3, 6;...
  • Page 112 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-23. Format of Port Mode Register (78K0/FB2-L) Symbol Address After reset PM02 PM01 PM00 FF20H Note Note Note Note Note Note Note Note PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM37 PM36...
  • Page 113 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-24. Format of Port Register (78K0/FY2-L) Symbol Address After reset FF00H 00H (output latch) Note 1 Note 1 Note 1 Note 1 FF02H 00H (output latch) FF03H 00H (output latch) FF06H 00H (output latch) Note 2 Note 2 P122...
  • Page 114 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-26. Format of Port Register (78K0/FB2-L) Symbol Address After reset FF00H 00H (output latch) Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 FF02H 00H (output latch)
  • Page 115 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
  • Page 116 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-29. Format of Pull-up Resistor Option Register (78K0/FB2-L) Symbol Address After reset PU02 PU01 PU00 FF30H PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 FF33H FF36H PU61 PU60 Pmn pin on-chip pull-up resistor selection PUmn (m = 0, 3, 6;...
  • Page 117 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS (4) Port input mode register 6 (PIM6) This register sets the input buffer of P60 or P61 in 1-bit units. When using an input compliant with the SMBus specifications in I C communication, set PIM60 and PIM61 to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 118 ADPCn can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ADPCn to 00H. Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 4-32. Format of A/D Port Configuration Register 0 (ADPC0) (a) 78K0/FY2-L Address: FF2EH...
  • Page 119 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-33. Format of A/D Port Configuration Register 1 (ADPC1) (78K0/FB2-L Only) Address: FF2FH After reset: 00H Symbol ADPC1 ADPCS8 ADPCS8 Digital I/O or analog input selection Analog input Digital I/O Cautions 1. Set the pin set to analog input to the input mode by using port mode register 7 (PM7).

  • Page 120: Port Function Operations

    78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.

  • Page 121: Settings Of Port Mode Register And Output Latch When Using Alternate Function

    78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Tables 4-12 to 4-14. Table 4-12.
  • Page 122 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-12. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/FY2-L) (2/2) Pin Name Alternate Function PM×× P×× Function Name Note − × × P121 × × TOOLC0 Input Note − ×...
  • Page 123 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-13. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/FA2-L) (1/2) Pin Name Alternate Function PM×× P×× Function Name × TI000 Input × INTP0 Input × TI010 Input TO00 Output Note 1 ×...
  • Page 124 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-13. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/FA2-L) (2/2) Pin Name Alternate Function PM×× P×× Function Name Note − × × P121 × × TOOLC0 Input Note − ×...
  • Page 125 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-14. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/FB2-L) (1/2) Pin Name Alternate Function PM×× P×× Function Name × TI000 Input × INTP0 Input × TI010 Input TO00 Output ×...
  • Page 126 78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS Table 4-14. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/FB2-L) (2/2) Pin Name Alternate Function PM×× P×× Function Name TOX00 Output × INTP2 Input × × TOOLC1 Input TOX01 Output ×...

  • Page 127: Cautions On 1-Bit Memory Manipulation Instruction For Port Register N (Pn)

    78K0/Fx2-L CHAPTER 4 PORT FUNCTIONS 4.6 Cautions on 1-bit Memory Manipulation Instruction for Port Register n (Pn) When a 1-bit memory manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.

  • Page 128: Chapter 5 Clock Generator

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock As the main system clock, a high-speed system clock (X1 clock or external main system clock) or internal high- speed oscillation clock can be selected by using the main clock mode register (MCM).

  • Page 129: Configuration Of Clock Generator

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode/PLL control register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC)
  • Page 130 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Remark f X1 clock oscillation frequency R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 131: Registers Controlling Clock Generator

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock frequency Main system clock frequency Internal low-speed oscillation clock frequency CPU clock frequency Peripheral hardware clock frequency 5.3 Registers Controlling Clock Generator The following seven registers are used to control the clock generator.
  • Page 132 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Select Register (OSCCTL) Address: FF9FH After reset: 00H Symbol <7> <6> <0> OSCCTL EXCLK OSCSEL AMPH EXCLK OSCSEL High-speed system clock P121/X1 pin P122/X2/EXCLK pin pin operation mode Input port mode Input port X1 oscillation mode...
  • Page 133 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR (2) Processor clock control register (PCC) This register is used to set the division ratio of the CPU clock,. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 5-3.
  • Page 134 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/Fx2-L microcontrollers. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-3. Table 5-3.
  • Page 135 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR (3) Internal oscillation mode/PLL control register (RCM) This register sets the operation mode of internal oscillator and controls the PLL function. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H Figure 5-4.
  • Page 136 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Cautions 1. When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock other (MCS = 1) than the internal high-speed oscillation clock. Specifically, set under either of the following conditions. In addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting RSTOP to 1.
  • Page 137 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR (5) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 138 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR (6) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
  • Page 139 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.

  • Page 140: System Clock Oscillator

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (clock-through mode: 2 to 20 MHz, PLL mode: 4 MHz) connected to the X1 and X2 pins. An external clock can also be input.

  • Page 141: Internal High-Speed Oscillator

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched 5.4.2 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/Fx2-L microcontrollers.

  • Page 142: Internal Low-Speed Oscillator

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.4.3 Internal low-speed oscillator The internal low-speed oscillator is incorporated in the 78K0/Fx2-L microcontrollers. The internal low-speed oscillation clock is only used as the watchdog timer and the clock of 8-bit timer H1. The internal low-speed oscillation clock cannot be used as the CPU clock.
  • Page 143 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Here is an example when using PLL (flow chart). Figure 5-11. Setting Example When Using PLL (Flow Chart) (When Multiplying Internal High-Speed Oscillation Clock) Reset release Waits for the accuracy of the internal RSTS = 1? high-speed oscillation to stabilize.

  • Page 144: Clock Generator Operation

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (refer to Figure 5-1). • Main system clock f • High-speed system clock f X1 clock f External main system clock f EXCLK...
  • Page 145 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-12. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART = 0)) Power supply 1.8 V voltage (V 1.61 V (TYP.) 0.5 V/ms (MIN.) Internal reset signal <1>...
  • Page 146 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (refer to (4) in 5.6.1 Example of controlling high-speed system clock, and (3) in 5.6.2 Example of controlling internal high-speed oscillation clock).

  • Page 147: Controlling Clock

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Cautions 1. A voltage oscillation stabilization time (0.93 to 3.7 ms) is required after the supply voltage reaches 1.61 V (TYP.). If the supply voltage rises from 1.61 V (TYP.) to 1.91 V (TYP.) within the power supply oscillation stabilization time, the power supply oscillation stabilization time is automatically generated before reset processing.
  • Page 148 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using the external main system clock <1> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register) When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input mode. EXCLK OSCSEL Operation Mode of High-...
  • Page 149 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR (4) Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. • Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is used) •...

  • Page 150: Example Of Controlling Internal High-Speed Oscillation Clock

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of controlling internal high-speed oscillation clock The following describes examples of clock setting procedures for the following cases. (1) When restarting oscillation of the internal high-speed oscillation clock (2) When using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high- speed system clock as peripheral hardware clock (3) When stopping the internal high-speed oscillation clock Remark See 5.4.5 PLL (phase locked loop) when using the PLL.
  • Page 151 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR <3> Selecting the CPU clock division ratio (PCC register) To select the CPU clock division ratio, use PCC0, PCC1, and PCC2. PCC2 PCC1 PCC0 CPU Clock (f ) Selection /2 (default) Other than above Setting prohibited (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways.

  • Page 152: Example Of Controlling Internal Low-Speed Oscillation Clock

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. • Watchdog timer • 8-bit timer H1 (if f is selected as the count clock) In addition, the following operation modes can be selected by the option byte.

  • Page 153: Cpu Clock Status Transition Diagram

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set (Option Byte: LVISTART = 0)) Internal low-speed oscillation: Woken up Power ON Internal high-speed oscillation: Woken up...
  • Page 154 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/3) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) →...
  • Page 155 78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (2/3) (4) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0...

  • Page 156: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR Table 5-4. CPU Clock Transition and SFR Register Setting Examples (3/3) (7) • HALT mode (H) set while CPU is operating with internal high-speed oscillation clock (B) • HALT mode (I) set while CPU is operating with high-speed system clock (C) •...

  • Page 157: Time Required For Switchover Of Cpu Clock And Main System Clock

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC), the division ratio of the main system clock can be changed. The actual switchover operation is not performed immediately after rewriting to PCC;...

  • Page 158: Conditions Before Clock Oscillation Is Stopped

    78K0/Fx2-L CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-8. Conditions Before Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR...

  • Page 159: Chapter 6 16-Bit Timers X0 And X1

    The A/D conversion start timing signal can be output by using a compare register (TXnCCR0 register). Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L (3) Capture function This function captures the count value to the capture register by detecting a comparator output or an external interrupt input (INPT0).
  • Page 160 (7) Timer output gating function (by interlocking with 8-bit timer H1) Timer output can be gate-controlled by using the output of 8-bit timer H1 (the TOH1 output). Note 78K0/FA2-L and 78K0/FB2-L only. Note (8) Timer reset mode (comparator, INTP0 interlocking mode 1) Timer output can be reset and the timer counter cleared while the comparator 0 to 2 outputs or the INTP0 input is high level.

  • Page 161: Configuration Of 16-Bit Timers X0 And X1

    16-bit timer X0 operation control register 4 (TX0CTL4) Note 16-bit timer X0 output control register 0 (TX0IOC0) Port mode register 3 (PM3) Port register 3 (P3) Note 78K0/FA2-L and 78K0/FB2-L only (2) 16-bit timer X1 (78K0/FB2-L only) Item Configuration Timer/counter 16-bit timer counter X1 Register...
  • Page 162 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-1. Block Diagram of 16-bit Timer X0 Internal bus 16-bit timer X0 capture/ Note Capture trigger compare register 0 CMP0+ (TX0CCR0) CMP1+ CMP2+ 16-bit timer X0 capture/ INTP0 compare buffer register TOH1 (from TMH1) A/D trigger signal...
  • Page 163 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-3. Block Diagram of 16-bit Timers X0 and X1 (TMX0 and TMX1 Synchronous Start/Clear Mode, TMX0 and TMX1 Synchronous Start Mode) Internal bus 16-bit timer X0 capture/ Capture trigger Note compare register 0 (TX0CCR0) CMP2+ INTP0...
  • Page 164 Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L (i) Using TXnCCR0 as a compare register TXnCCR0 can be refreshed (writing the same value) and its value can be rewritten while the timer is counting (TXnTMC = 1). When the value of TXnCCR0 is rewritten while the timer is operating, that value is latched, transferred to TXnCCR0 at the following timing, and the value of TXnCCR0 is changed.
  • Page 165 Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 6-5. Format of 16-bit Timer Xn Compare Register m (TXnCRm) Address: FF84H, FF85H (TX0CR0), FF86H, FF87H (TX0CR1), FF8AH, FF8BH (TX0CR2), FF90H, FF91H (TX0CR3), FF9CH, FF9DH (TX1CR0), FFB0H, FFB1H (TX1CR1), FFB2H, FFB3H (TX1CR2), FFB4H, FFB5H (TX1CR3)

  • Page 166: Registers Controlling 16-Bit Timers X0 And X1

    • Port register 3 (P3) Note 78K0/FA2-L and 78K0/FB2-L only ● 16-bit timer X1 (78K0/FB2-L only) • 16-bit timer X1 operation control registers 0 to 2, 4 (TX1CTL0 to TX1CTL2, TX1CTL4) • 16-bit timer X1 output control register 0 (TX1IOC0) •...
  • Page 167 TXnCTL0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TXnCTL0 to 00H. Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 6-6. Format of 16-bit Timer X0 Operation Control Register 0 (TX0CTL0) Address: FF7EH After reset: 00H Symbol <7>...
  • Page 168 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-7. Format of 16-bit Timer X1 Operation Control Register 0 (TX1CTL0) (78K0/FB2-L Only) Address: FF94H After reset: 00H Symbol <7> <2> <1> <0> TX1CTL0 TX1TMC TX1CKS2 TX1CKS1 TX1CKS0 TX1TMC TMX1 count operation control...
  • Page 169 • INTTMX0 is generated upon match of counter and TX0CR3 register Notes 1. In TMX0 or TMX1 synchronous start mode (available only in 78K0/FB2-L), a timer start operation via detection of INTP0 rising edge cannot be performed, so set TX0INTPST to 0.
  • Page 170 3. When using the output gate function, set bit 0 (TOEN1) of the TMHMD1 register to 1 (enable the TOH1 output). Figure 6-9. Format of 16-bit Timer X1 Operation Control Register 1 (TX1CTL1) (78K0/FB2-L Only) Address: FF95H After reset: 00H Symbol <5>...
  • Page 171 Remarks 1. The capture trigger source differs as follows, according to the operation mode. Operation mode Capture trigger sources TMX0-only start mode INTCMP2, INTP0 TMX1-only start mode (78K0/FB2-L only) INTCMP1 TMX0 and TMX1 synchronous start TMX0 INTCMP2, INTP0 mode (78K0/FB2-L only)
  • Page 172 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-11. Format of 16-bit Timer X1 Operation Control Register 2 (TX1CTL2) (78K0/FB2-L only) Address: FF96H After reset: 00H Symbol <1> <0> TX1CTL2 TX1ADEN TX1CCS TX1ADEN Control of generating A/D conversion synchronization trigger from TMX1...
  • Page 173 Do not set to interlocking mode 3 when in TMX0 and TMX1 synchronous start/clear mode (available only in 78K0/FB2-L). 78K0/FA2-L and 78K0/FB2-L only. Caution During the timer operation, setting the other bits of TX0CTL3 is prohibited. However, TX0CTL3 can be refreshed (the same value is written).
  • Page 174 TX0CMP1RP Selection of timer interlocking with comparator 1 output Comparator 1 output interlocks with TMX0 timer. Comparator 1 output interlocks with TMX1 timer (available only in 78K0/FB2-L). TX0CMP1R TX0CMP1R Operation mode of interlocking function via comparator 1 output (interlocking with TMX0 timer) Disables operation of interlocking function via comparator 1 output.
  • Page 175 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-14. Format of 16-bit Timer X1 Operation Control Register 4 (TX1CTL4) (78K0/FB2-L Only) Address: FF9AH After reset: 00H Symbol <4> <3> <1> <0> TX1CTL4 TX1CMP1R TX1CMP1R TX1CMP0R TX1CMP0R TX1CMP1R TX1CMP1R Operation mode of interlocking function via comparator 1 output (interlocking with TMX1 timer) Disables operation of interlocking function via comparator 1 output.
  • Page 176 Reset signal generation clears TXnIOC0 to 00H. Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 6-15. Format of 16-bit Timer X0 Output Control Register 0 (TX0IOC0) (78K0/FA2-L and 78K0/FB2-L only) Address: FF83H After reset: 00H Symbol <3>...
  • Page 177 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-16. Format of 16-bit Timer X1 Output Control Register 0 (TX1IOC0) (78K0/FB2-L Only) Address: FF9BH After reset: 00H Symbol <3> <2> <1> <0> TX1IOC0 TX1TOC1 TX1TOC0 TX1TOL1 TX1TOL0 TX1TOC1 TOX11 output control Disables timer output (Fixes to low-level output when TX1TOL1 = 0, and fixes to high-level output when TX1TOL1 = 1.)
  • Page 178 Output mode (output buffer on) Input mode (output buffer off) Remark The figure shown above presents the format of port mode register 3 of the 78K0/FB2-L products. For the format of port mode register 3 of other products, refer to (1) Port mode registers (PMxx) in 4.3 Registers Controlling Port Function.
  • Page 179 TX0INTP0RM1, Setting Setting Setting (setting TX0INTP0RM0 TX0INTP0RM1 = 1 and TX0INTP0RM0 = 1 is prohibited) − − TX0CMP2RM1, Setting Setting Setting (setting TX0CMP2RM0 TX0CMP2RM1 = 1 and TX0CMP2RM0 = 1 is prohibited) Note 78K0/FB2-L only R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 180 Setting Setting Setting − − − TX1IOC0 TX1TOC1 Setting Setting Setting − − − TX1TOC0 Setting Setting Setting − − − TX1TOL1 Setting Setting Setting − − − TX1TOL0 Setting Setting Setting Note 78K0/FB2-L only R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 181 (n = 0, 1) Mode Mode Note TMX0 TMX1 Master Slave Master Slave (TMX0) (TMX1) (TMX0) (TMX1) INTP0 Usable Usable Usable usable usable INTCMP0 Usable Usable Not usable INTCMP1 INTCMP2 Usable usable usable Note Available only in 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 182: Operation Of 16-Bit Timer/Event Counter 00

    (INTTMXn) is generated. This INTTMXn signal enables TMXn to operate as an interval timer. Remarks 1. For how to enable the INTTMXn interrupt, refer to CHAPTER 17 INTERRUPT FUNCTIONS. 2. m = 1, 3 : 78K0/FY2-L, 78K0/FA2-L, 78K0/FB2-L n = 0...
  • Page 183 Select target compare register of INTTMX0 0 : INTTMX0 is generated upon match of counter and TX0CR1 register 1 : INTTMX0 is generated upon match of counter and TX0CR3 register (c) 16-bit timer X1 operation control register 1 (TX1CTL1) (78K0/FB2-L only) TX1PWMCE TX1PWM...
  • Page 184 The counter is initialized and counting is stopped TXnTMC bit = 0 by clearing the TXnTMC bit bit to 0. STOP Remark m = 1, 3 : 78K0/FY2-L, 78K0/FA2-L, 78K0/FB2-L n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03...
  • Page 185 A/D converter (timer trigger mode). 2. m = 1, 3 n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 6-21. Basic Timing Example of A/D Conversion Start Timing Signal Output 16-bit timer counter Xn 0000H A/D conversion synchronization...
  • Page 186 Select target compare register of INTTMX0 0: INTTMX0 is generated upon match of counter and TX0CR1 register 1: INTTMX0 is generated upon match of counter and TX0CR3 register (d) 16-bit timer X1 operation control register 1 (TX1CTL1) (78K0/FB2-L only) TX1PWMCE TX1PWM...
  • Page 187 = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L 2. For details of A/D conversion in combination with 16 bit timer X0 or X1, refer to 11.4.2 Basic operation of A/D converter (timer trigger mode). R01UH0068EJ0203 Rev.2.03...
  • Page 188 Xn (TMXn) is captured to a 16-bit timer Xn capture/compare register 0 (TXnCCR0) . When the value of TMXn later matches the value of TXnCRk, TMXn is cleared to 0000H. Remarks 1. m = 1, 2 : 78K0/FB2-L m = 2...
  • Page 189 Select target compare register of INTTMX0 0: INTTMX0 is generated upon match of counter and TX0CR1 register 1: INTTMX0 is generated upon match of counter and TX0CR3 register (c) 16-bit timer X1 operation control register 1 (TX1CTL1) (78K0/FB2-L only) TX1PWMCE TX1PWM...
  • Page 190 The counter is initialized and counting is stopped TXnTMC bit = 0 by clearing the TXnTMC bit bit to 0. STOP Remarks 1. m = 1, 2 : 78K0/FB2-L m = 2 : 78K0/FY2-L, 78K0/FA2-L n = 0 : 78K0/FY2-L, 78K0/FA2-...

  • Page 191: Operation Of Pwm Output Operation Of 16-Bit Timers X0 And X1

    Note Count clock of 16-bit timer Xn Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 6-27. Example of Register Settings for PWM Output Operation (Single Mode) (1/2) (a) 16-bit timer Xn operation control register 0 TXnTMC...
  • Page 192 (c) 16-bit timer Xn output control register 0 TXnTOC1 TXnTOC0 TXnTOL1 TXnTOL0 TXnIOC0 0: Normal output (low level) 1: Inverted output (high level) Enables timer output Disables timer output Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 193 = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L (2) PWM output operation (TMXn-only mode, dual output) PWM outputs are started when the count value of the inverted output of TOXn0 is set to TXnCR0 and TXnCR1, the count value of the inverted output of TOXn1 and the count value of the cycle are set to TXnCR2 and TXnCR3, and 1 is set to bit 7 (TXnTMC) of TXnCTL0.
  • Page 194 • PWM output: TOX10 and TOX11 pins TX1PWMCE TX1PWM TX1MD1 TX1MD0 TX1CTL1 TMX1-only start mode Dual output Using the TOX1n output gate function by TOH1 output is prohibited. Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 195 1: Inverted output (high level) Enables timer output Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 6-30. PWM Output Timing (TMXn-only Operation, PWM output: TOXn0 and TOXn1 pins) FFFFH 16-bit timer counter Xn 0000H 16-bit timer Xn compare...
  • Page 196 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (3) PWM output operation (TMX0 and TMX1 synchronous start mode) (78K0/FB2-L only) Output from the two timer outputs of TMX0 and TMX1 (up to 4 outputs) is simultaneously started. Setting bit 7 (TX0TMC) of TX0CTL1 to 1 starts PWM output.
  • Page 197 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-31. Example of Register Settings for PWM Output Operation (TMX0 and TMX1 Synchronous Start Mode) (2/2) (c) 16-bit timer Xn output control register 0 TXnTOC1 TXnTOC0 TXnTOL1 TXnTOL0 TXnIOC0 0: Normal output (low level) 1: Inverted output (high level) Disables timer output Enables timer output...
  • Page 198 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-32. PWM Output Timing (Synchronous Start mode, TMX0 dual output, TMX1 dual output) Synchronous Start FFFFH 16-bit timer counter X0 0000H FFFFH 16-bit timer counter X1 0000H 16-bit timer X0 compare buffer register 0 16-bit timer X0 compare buffer register 1...
  • Page 199 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (4) PWM output operation (TMX0 and TMX1 synchronous start/clear mode) (78K0/FB2-L only) Output cycles from the two timer outputs of TMX0 and TMX1 (up to 4 outputs) are synchronized. Setting bit 7 (TX0TMC) of TX0CTL1 to 1 starts PWM output.
  • Page 200 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (b) TMX0 dual output, TMX1 single output or dual output ● Pulse cycle and duty of TOX00 • Pulse cycle = (Set value of TX0CR3 + 1) × Count clock cycle • Duty = (Set value of TX0CR1 − Set value of TX0CR0) / (Set value of TX0CR3 + 1) ●...
  • Page 201 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-33. Example of Register Settings for PWM Output Operation (TMX0 and TMX1 synchronous start/clear mode) (a) 16-bit timer X0 operation control register 0 TX0TMC TX0CKS2 TX0CKS1 TX0CKS0 TX0CTL0 Selects count clock Starts timer count operation (b) 16-bit timer Xn operation control register 1 TX0INTPST...
  • Page 202 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-34. PWM Output Timing (Synchronous start/clear mode, TMX0 dual output, TMX1 dual output) FFFFH 16-bit timer counter X0 0000H FFFFH 16-bit timer counter X1 0000H 16-bit timer X0 compare buffer register 0 16-bit timer X0 compare buffer register 1 16-bit timer X0 compare...
  • Page 203 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (5) PWM output operation (PWM output from TOX0n when TOH1 output is at high level) A square wave is output from the TOX0n pin by combining 8-bit timer H1 and 16-bit timer X0, only when the TOH1 output is at high level.
  • Page 204 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-36. PWM Output Timing (TMX0-Only Operation (Dual Output), PWM Output from TOX00 and TOX01 When TOH1 Output Is at High Level) TOH1 output (intarnal output) TOX00 output (intarnal output) TOX00 pin output (TX0TOL0 = 0) TOX00 pin output (TX0TOL0 = 1)
  • Page 205 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-37. Example of Register Settings for PWM Output Operation (TMX0-Only Operation (Dual Output), PWM Output from TOX00 and TOX01 When TOH1 Output Is at Low Level) (2/2) (b) 16-bit timer X0 operation control register 1 TX0INTPST TX0PWMCE TX0PWMCINV TX0PWM TX0CTL1...
  • Page 206 CHAPTER 6 16-BIT TIMERS X0 AND X1 (7) PWM output operation (PWM output from TOX1n when TOH1 output is at high level) (78K0/FB2-L only) A square wave is output from the TOX1n pin by combining 8-bit timer H1 and 16-bit timer X1, only when the TOH1 output is at high level.
  • Page 207 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-39. Example of Register Settings for PWM Output Operation (TMX1-Only Operation (Dual Output), PWM Output from TOX10 and TOX11 When TOH1 Output Is at High Level) (2/2) (c) 16-bit timer X1 output control register 0 TX1TOC1 TX1TOC0 TX1TOL1...
  • Page 208 (8) PWM output operation (PWM output from TOX00, TOX01, TOX10, and TOX11 when TOH1 output is at high level) (78K0/FB2-L only) A square wave is output from the TOX00, TOX01, TOX10, and TOX11 pins by combining 8-bit timer H1 and 16-bit timers X0 and X1, only when the TOH1 output is at high level.
  • Page 209 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-41. Example of Register Settings for PWM Output Operation (TMX0 and TMX1 Synchronous Start/Clear Mode, PWM Output from TOX00, TOX01, TOX10, and TOX11 When TOH1 Output Is at High Level) (2/2) (c) 16-bit timer Xn output control register 0 TXnTOC1 TXnTOC0...

  • Page 210: Interlocking Function With Comparator Or Intp0

    • 16-bit timer X1 (TMX1-only operation mode, synchronous start mode) Note CMP0, CMP1 Note • 16-bit timers X0 and X1 (synchronous start/clear mode) CMP2, INTP0 Note Available only in 78K0/FB2-L Figure 6-43. Block Diagram of 16-bit Timer X0 Output Configuration TOH1 Output latch (from TMH1) PM31...
  • Page 211 Note2 Timer counter clear signal controller Mode Comparator 1 output selector Capture trigger signal INTTMX1 Figure 6-45. Block Diagram of 16-Bit Timers X0 and X1 Output Configuration (78K0/FB2-L only) TOH1 (from TMH1) Output latch (P31) PM31 Note1 TOTX0C0 Level Output gate...
  • Page 212 16-bit timer X0 compare buffer register 3 TOXn0 pin output Reset (TXnTOL0 = 0) TOXn1 pin output Reset (TXnTOL1 = 0) Comparator output or INTP0 input Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 213 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (2) Interlocking mode 2 (timer restart mode) This mode restarts the corresponding timer when the rising edge of the comparators 0 to 2 outputs or the INTP0 input is detected. Figure 6-48 Example of Register Settings for Interlocking Mode 2 (Timer Restart Mode) •...
  • Page 214 16-bit timer X0 compare buffer register 3 TOXn0 pin output (TXnTOL0 = 0) TOXn1 pin output (TXnTOL1 = 0) Reset Comparator output or INTP0 input Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 215 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (3) Interlocking mode 3 (timer output reset mode) This mode sets the output of the corresponding timer to the reset state from when the rising edge of the comparators 0 to 2 outputs or the INTP0 input is detected until the next interrupt is generated. Caution Do not set to interlocking mode 3 when in TMX0 and TMX1 synchronous start/clear mode.
  • Page 216 16-bit timer X0 compare buffer register 3 Reset TOXn0 pin output (TXnTOL0 = 0) Reset TOXn1 pin output (TXnTOL1 = 0) Comparator output or INTP0 input Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 217 INTTMXn signal Comparator output or INTP0 input (Interlocking mode 1) Comparator output or INTP0 input (Interlocking mode 2) Interlocking mode 1 has priority Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 218 If interlocking mode 2 is triggered by the detection of an edge while the timer is being reset in interlocking mode 3, interlocking mode 2 is valid. Remark n = 0 : 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 219: High-Impedance Output Control Function

    78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 6.7 High-Impedance Output Control Function The high-impedance output control function changes the outputs of 16-bit timers X0 and X1 to a high-impedance state at the generation of an external interrupt input (INTP0) or comparator output (INTCMP0 to INTCMP2) and executes functions such as the PWM output emergency stop function.

  • Page 220: Registers Controlling High-Impedance Output Controller

    78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 6.7.2 Registers controlling high-impedance output controller Registers used to control the high-impedance output controller are shown below. • High-impedance output function enable register (HIZTREN) • High-impedance output mode select register (HIZTRS) • High-impedance output function control register 0 (HZA0CTL0) (1) High-impedance output function enable register (HIZTREN) HIZTREN is a register that enables/disables the input of the trigger signal used for controlling high-impedance output.
  • Page 221 Normal output Can be used as high-impedance output HIZPTS1 P32/TOX01 pin control Normal output Can be used as high-impedance output HIZPTS0 P31/TOX00 pin control Normal output Can be used as high-impedance output Note 78K0/FB2-L only. R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 222 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (3) High-impedance output function control register 0 (HZA0CTL0) HZA0CTL0 is a register that controls the high-impedance state of the output buffers. HZA0CTL0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears HZA0CTL0 to 00H.
  • Page 223 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 Figure 6-58 Format of High-Impedance Output Function Control Register 0 (HZA0CTL0) (2/2) HZA0DCT0 High-impedance output trigger bit Notes 1 to 4 Does not operate. Sets target pin to high-impedance output state and sets (1) HZA0DCF0 bit. HZA0DCC0 High-impedance output control clear bit Notes 2 to 6...

  • Page 224: High-Impedance Output Control Circuit Setting Procedure

    78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 6.7.3 High-impedance output control circuit setting procedure (1) Transitioning to the high-impedance output state by detecting the valid edge of the INPT0 input or the output of comparators 0 to 2 <1> Set the HIZTRS1, HSTRS0, and HIZPTS3 to HIZPTS0 bits (select the trigger source and the high-impedance target pin).
  • Page 225 78K0/Fx2-L CHAPTER 6 16-BIT TIMERS X0 AND X1 (4) Transitioning to the high-impedance output state by using the HZA0DCT0 bit To set the pin to the high-impedance output state by using the HZA0DCT0 bit, the HZA0DCT0 bit must be set (1) while the trigger signal is in the inactive-level state.

  • Page 226: Chapter 7 16-Bit Timer/Event Counter 00

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.1 Functions of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 is mounted onto all 78K0/Fx2-L microcontroller products. 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval.

  • Page 227: Configuration Of 16-Bit Timer/Event Counter 00

    Prescaler mode register 00 (PRM00) Note Port alternate switch control register (MUXSEL) Port mode register 0 (PM0) Port register 0 (P0) Note 78K0/FB2-L only. Figure 7-1 shows a block diagram. Figure 7-1. Block Diagram of 16-bit Timer/Event Counter 00 Internal bus Capture/compare control...
  • Page 228 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time. Select either of the functions. 2. If clearing of bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) to 00 and input of the capture trigger conflict, then the captured data is undefined.
  • Page 229 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) 16-bit timer capture/compare register 000 (CR000), 16-bit timer capture/compare register 010 (CR010) CR000 and CR010 are 16-bit registers that are used with a capture function or comparison function selected by using CRC00. Change the value of CR000 while the timer is stopped (TMC003 and TMC002 = 00).
  • Page 230 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-4. Format of 16-bit Timer Capture/Compare Register 010 (CR010) Address: FF14H, FF15H After reset: 0000H FF15H FF14H CR010 (i) When CR010 is used as a compare register The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal (INTTM010) is generated if they match.
  • Page 231 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Timer counter clear TM00 register Compare register set value (0000H) Operation Operation enabled Timer operation enable bit disabled (00) (other than 00) (TMC003, TMC002) Interrupt request signal Interrupt signal Interrupt signal is not generated is generated Remarks 1.
  • Page 232 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Table 7-2. Capture Operation of CR000 and CR010 External Input Signal TI000 Pin Input TI010 Pin Input Capture Operation Capture operation of CRC001 = 1 Set values of ES010 and CRC001 bit = 0 Set values of ES110 and CR000 TI000 pin input...

  • Page 233: Registers Controlling 16-Bit Timer/Event Counter 00

    • Port mode register 0 (PM0) • Port register 0 (P0) Note 78K0/FB2-L only. (1) 16-bit timer mode control register 00 (TMC00) TMC00 is an 8-bit register that sets the 16-bit timer/event counter 00 operation mode, TM00 clear mode, and output timing, and detects an overflow.
  • Page 234 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-5. Format of 16-bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock. Clears 16-bit timer counter 00 (TM00).
  • Page 235 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-6. Format of Capture/Compare Control Register 00 (CRC00) Address: FFBCH After reset: 00H Symbol CRC00 CRC002 CRC001 CRC000 CRC002 CR010 operating mode selection Operates as compare register Operates as capture register CRC001 CR000 capture trigger selection Captures on valid edge of TI010 pin Note...
  • Page 236 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) TOC00 is an 8-bit register that controls the TO00 output. TOC00 can be rewritten while only OSPT00 is operating (when TMC003 and TMC002 = other than 00). Rewriting the other bits is prohibited during operation.
  • Page 237 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-8. Format of 16-bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software −...
  • Page 238 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00). PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 239 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-9. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H Symbol PRM00 ES110 ES100 ES010 ES000 PRM001 PRM000 ES110 ES100 TI010 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES010...
  • Page 240 Input mode (output buffer off) Remark The figure shown above presents the format of port mode register 0 of the 78K0/FB2-L. For the format of port mode register 0 of other products, refer to (1) Port mode registers (PMxx) in 4.3 Registers Controlling Port Function.

  • Page 241: Operation Of 16-Bit Timer/Event Counter 00

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4 Operation of 16-bit Timer/Event Counter 00 7.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the count clock.
  • Page 242 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-14. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
  • Page 243 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-15. Example of Software Processing for Interval Timer Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register INTTM000 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before PRM00 register, setting the TMC003 and TMC002 bits to 11.

  • Page 244: Square-Wave Output Operation

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.2 Square-wave output operation When 16-bit timer/event counter 00 operates as an interval timer (refer to 7.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H. When TMC003 and TMC002 are set to 11 (count clear &...
  • Page 245 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-18. Example of Register Settings for Square-Wave Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
  • Page 246 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-19. Example of Software Processing for Square-Wave Output Function TM00 register 0000H Operable bits (TMC003, TMC002) CR000 register TO00 output INTTM000 signal TO0n output control bit (TOC001, TOE00) <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before...

  • Page 247: External Event Counter Operation

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM00 and CR000 (INTTM000) is generated.
  • Page 248 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-21. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as...
  • Page 249 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-21. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If M is set to CR000, the interrupt signal (INTTM000) is generated when the number of external events reaches (M + 1).
  • Page 250 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-22. Example of Software Processing in External Event Counter Mode TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) TO00 output Compare match interrupt (INTTM000) TO00 output control bits (TOC004, TOC001, TOE00) <1>...

  • Page 251: Operation In Clear & Start Mode Entered By Ti000 Pin Valid Edge Input

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear & start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the timer/event counter, TM00 starts counting up.
  • Page 252 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-24. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Compare Register) (a) TOC00 = 13H, PRM00 = 10H, CRC00 = 00H, TMC00 = 08H TM00 register 0000H Operable bits...
  • Page 253 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 7-25. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) Edge TI000 pin...
  • Page 254 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-26. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 0AH, CR000 = 0003H TM00 register 0003H 0000H...
  • Page 255 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) Edge TI000 pin...
  • Page 256 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (1/2) (a) TOC00 = 13H, PRM00 = 10H, CRC00 = 03H, TMC00 = 08H, CR010 = 0001H TM00 register 0000H Operable bits...
  • Page 257 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00 = 03H, TMC00 = 0AH, CR010 = 0003H TM00 register 0003H 0000H...
  • Page 258 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002...
  • Page 259 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (2/3) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 0AH FFFFH TM00 register 0000H...
  • Page 260 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (3/3) (c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 = 0AH TM00 register 0000H Operable bits...
  • Page 261 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 output on match between TM00 and CR000/CR010.
  • Page 262 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (2/2) (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 Count clock selection (setting TI000 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection...
  • Page 263 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-32. Example of Software Processing in Clear & Start Mode Entered by TI000 Pin Valid Edge Input TM00 register 0000H Operable bits (TMC003, TMC002) Count clear input (TI000 pin input) Compare register (CR000) Compare match interrupt (INTTM000)

  • Page 264: Free-Running Timer Operation

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free-running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and continues counting.
  • Page 265 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-34. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Compare Register) • TOC00 = 13H, PRM00 = 00H, CRC00 = 00H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000)
  • Page 266 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-36. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Capture Register) • TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000)
  • Page 267 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 7-37. Block Diagram of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002 Timer counter Count clock (TM00) Capture register Interrupt signal...
  • Page 268 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-38. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (1/2) (a) TOC00 = 13H, PRM00 = 50H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000)
  • Page 269 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-38. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI010)
  • Page 270 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-39. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 0: Inverts TO00 output on match between TM00 and CR000/CR010. 1: Inverts TO00 output on match between TM00 and CR000/CR010 valid edge of TI000 pin.
  • Page 271 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-39. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM001 PRM000 Count clock selection (setting TI000 valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited 11: Both edges detection...
  • Page 272 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-40. Example of Software Processing in Free-Running Timer Mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) Timer output control bits (TOE00, TOC004, TOC001) TO00 output <1>...

  • Page 273: Ppg Output Operation

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.6 PPG output operation A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11 (clear &...
  • Page 274 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-42. Example of Register Settings for PPG Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 Clears and starts on match between TM00 and CR000. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 CR000 used as compare register...
  • Page 275 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-42. Example of Register Settings for PPG Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00. The count value of TM00 is cleared.
  • Page 276 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-43. Example of Software Processing for PPG Output Operation TM00 register 0000H Operable bits (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) Timer output control bits (TOE00, TOC004, TOC001) TO00 output N + 1...

  • Page 277: One-Shot Pulse Output Operation

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge) and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
  • Page 278 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-45. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode by valid edge of TI000 pin.
  • Page 279 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-45. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a compare register when a one-shot pulse is output.
  • Page 280 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-46. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM00 register 0000H Operable bits 01 or 10 (TMC003, TMC002) One-shot pulse enable bit (OSPE0) One-shot pulse trigger bit (OSPT0) One-shot pulse trigger input (TI000 pin) Overflow plug...
  • Page 281 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-46. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits. CRC00 register, Note TOC00 register...

  • Page 282: Pulse Width Measurement Operation

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI000 pin.
  • Page 283 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 A pulse width can be measured in the following three ways. • Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode) • Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) •...
  • Page 284 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge detected on the TI000 pin.
  • Page 285 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00 is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected.
  • Page 286 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-52. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 OVF00 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI000 pin.
  • Page 287 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-52. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a capture register. Either the TI000 or TI010 pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
  • Page 288 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-53. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) Capture trigger input (TI000) Capture register 0000H (CR010) Capture interrupt (INTTM010) Capture trigger input...
  • Page 289 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 Figure 7-53. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM00 register, before setting the TMC003 and TMC002 bits. CRC00 register, port setting TMC003, TMC002 bits =...

  • Page 290: Special Use Of Tm00

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.5 Special Use of TM00 7.5.1 Rewriting CR010 during TM00 operation In principle, rewriting CR000 and CR010 of the 78K0/Fx2-L microcontrollers when they are used as compare registers is prohibited while TM00 is operating (TMC003 and TMC002 = other than 00). However, the value of CR010 can be changed, even while TM00 is operating, using the following procedure if CR010 is used for PPG output and the duty factor is changed.
  • Page 291 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (2) Setting LVS00 and LVR00 Set LVS00 and LVR00 using the following procedure. Figure 7-54. Example of Flow for Setting LVS00 and LVR00 Bits Setting TOC00.OSPE00, TOC004, TOC001 bits <1> Setting of timer output operation Setting TOC00.TOE00 bit Setting TOC00.LVS00, LVR00 bits <2>...

  • Page 292: Cautions For 16-Bit Timer/Event Counter 00

    78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 7.6 Cautions for 16-bit Timer/Event Counter 00 (1) Restrictions for each channel of 16-bit timer/event counter 00 Table 7-3 shows the restrictions for each channel. Table 7-3. Restrictions for Each Channel of 16-bit Timer/Event Counter 00 Operation Restriction −...
  • Page 293 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not guaranteed.
  • Page 294 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag (a) Setting OVF00 flag (1) The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows. Select the clear & start mode entered upon a match between TM00 and CR000. ↓...
  • Page 295 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly.
  • Page 296 78K0/Fx2-L CHAPTER 7 16-BIT TIMER/EVENT COUNTER 00 (12) Reading of 16-bit timer counter 00 (TM00) TM00 can be read without stopping the actual counter, because the count values captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up.

  • Page 297: Chapter 8 8-Bit Timer/Event Counter 51

    78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.1 Functions of 8-bit Timer/Event Counter 51 8-bit timer/event counter 51 is mounted onto all 78K0/Fx2-L microcontroller products. 8-bit timer/event counter 51 has the following functions. • Interval timer •...
  • Page 298 78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 Figure 8-1. Block Diagram of 8-bit Timer/Event Counter 51 Internal bus 8-bit timer compare INTTM51 register 51 (CR51) TI51/P30/ Match TOH1/INTP1 8-bit timer counter 51 (TM51) 8-bit timer H1 output Clear TCE51 TCL512 TCL511 TCL510 Timer clock selection 8-bit timer mode control register 51 (TCL51)

  • Page 299: Registers Controlling 8-Bit Timer/Event Counter 51

    78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 (2) 8-bit timer compare register 51 (CR51) CR51 can be read and written by an 8-bit memory manipulation instruction. The value set in CR51 is constantly compared with the 8-bit timer counter 51 (TM51) count value, and an interrupt request (INTTM51) is generated if they match.
  • Page 300 78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 (1) Timer clock selection register 51 (TCL51) This register sets the count clock of 8-bit timer/event counter 51 and the valid edge of the TI51 pin input. TCL51 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears TCL51 to 00H.
  • Page 301 Input mode (output buffer off) Remark The figure shown above presents the format of port mode register 3 of the 78K0/FB2-L. For the format of port mode register 3 of other products, refer to (1) Port mode registers (PMxx) in 4.3 Registers Controlling Port Function.

  • Page 302: Operations Of 8-Bit Timer/Event Counter 51

    78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.4 Operations of 8-bit Timer/Event Counter 51 8.4.1 Operation as interval timer 8-bit timer/event counter 51 operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 51 (CR51). When the count value of 8-bit timer counter 51 (TM51) matches the value set to CR51, counting continues with the TM51 value cleared to 0 and an interrupt request signal (INTTM51) is generated.
  • Page 303 78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 Figure 8-7. Interval Timer Operation Timing (a) Basic operation Count clock TM51 count value Count start Clear Clear CR51 TCE51 INTTM51 Interrupt acknowledged Interrupt acknowledged Interval time Interval time Remark Interval time = (N + 1) × t, N = 01H to FFH (b) When CR51 = 00H Count clock TM51...

  • Page 304: Operation As External Event Counter

    78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI51 pin by 8-bit timer counter 51 (TM51). TM51 is incremented each time the valid edge specified by timer clock selection register 51 (TCL51) is input. Either the rising or falling edge can be selected.

  • Page 305: Cautions For 8-Bit Timer/Event Counter 51

    78K0/Fx2-L CHAPTER 8 8-BIT TIMER/EVENT COUNTER 51 8.5 Cautions for 8-bit Timer/Event Counter 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counter 51 (TM51) are started asynchronously to the count clock.

  • Page 306: Chapter 9 8-Bit Timer H1

    78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 CHAPTER 9 8-BIT TIMER H1 9.1 Functions of 8-bit Timer H1 8-bit timer H1 is mounted onto all 78K0/Fx2-L microcontroller products. 8-bit timer H1 has the following functions. • Interval timer • Square-wave output •...
  • Page 307 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 308 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 (1) 8-bit timer H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP01 with the count value of the 8-bit timer counter H1 and, when the two values match, generates an interrupt request signal (INTTMH1) and inverts the output level of TOH1.

  • Page 309: Registers Controlling 8-Bit Timer H1

    78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 9.3 Registers Controlling 8-bit Timer H1 The following four registers are used to control 8-bit timer H1. • 8-bit timer H mode register 1 (TMHMD1) • 8-bit timer H carrier control register 1 (TMCYC1) •...
  • Page 310 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-4. Format of 8-bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) Count clock selection CKS12...
  • Page 311 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Remarks 1. f : Peripheral hardware clock frequency 2. f Internal low-speed oscillation clock frequency (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 312 Input mode (output buffer off) Remark The figure shown above presents the format of port mode register 3 of the 78K0/FB2-L. For the format of port mode register 3 of other products, refer to (1) Port mode registers (PMxx) in 4.3 Registers Controlling Port Function.

  • Page 313: Operation Of 8-Bit Timer H1

    78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 9.4 Operation of 8-bit Timer H1 9.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and the 8-bit timer counter H1 is cleared to 00H. Compare register 11 (CMP11) is not used in interval timer mode.
  • Page 314 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-8. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H ≤ CMP01 ≤ FEH) Count clock Count start 01H 00H 8-bit timer counter H1 Clear Clear CMP01 TMHE1 INTTMH1 Interval time TOH1 <1>...
  • Page 315 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-8. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP01 = FFH Count clock Count start 8-bit timer counter H1 Clear Clear CMP01 TMHE1 INTTMH1 TOH1 Interval time (c) Operation when CMP01 = 00H Count clock Count start 8-bit timer counter H1...

  • Page 316: Operation As Pwm Output

    78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 9.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during timer operation is prohibited.
  • Page 317 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHE1 = 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the PWM pulse output cycle and duty are as follows.
  • Page 318 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-10. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter H1 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <4>...
  • Page 319 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-10. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP01 CMP11...
  • Page 320 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-10. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1...
  • Page 321 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-10. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) Count clock 8-bit timer 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H counter Hn...

  • Page 322: Carrier Generator Operation

    78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 9.4.3 Carrier generator operation In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
  • Page 323 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
  • Page 324 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Setting <1> Set each register. Figure 9-12. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHMD1 Timer output enabled Default setting of timer output level Carrier generator mode selection Count clock (f ) selection...
  • Page 325 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is f , the carrier clock output cycle and duty are as follows.
  • Page 326 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-13. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N 8-bit timer H1 count clock 8-bit timer counter N 00H N 00H N 00H N 00H N 00H H1 count value CMP01 CMP11...
  • Page 327 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-13. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H H1 count value CMP01 CMP11...
  • Page 328 78K0/Fx2-L CHAPTER 9 8-BIT TIMER H1 Figure 9-13. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1 <4>...

  • Page 329: Chapter 10 Watchdog Timer

    78K0/Fx2-L CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer is mounted onto all 78K0/Fx2-L microcontroller products. The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.

  • Page 330: Configuration Of Watchdog Timer

    78K0/Fx2-L CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 10-2.

  • Page 331: Register Controlling Watchdog Timer

    78K0/Fx2-L CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.

  • Page 332: Operation Of Watchdog Timer

    78K0/Fx2-L CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, refer to CHAPTER 23).

  • Page 333: Setting Overflow Time Of Watchdog Timer

    78K0/Fx2-L CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped)

  • Page 334: Setting Window Open Period Of Watchdog Timer

    78K0/Fx2-L CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. •...
  • Page 335 78K0/Fx2-L CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 3.64 s 0 to 2.43 s 0 to 1.21 s None Window open time...

  • Page 336: Chapter 11 A/D Converter

    Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated. Remark A/D converter analog input pins differ depending on products. • 78K0/FY2-L: ANI0 to ANI3 • 78K0/FA2-L: ANI0 to ANI5 • 78K0/FB2-L: ANI0 to ANI8 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 337 Be sure to connect V to a stabilized GND (= 0 V). Remark A/D converter analog input pins differ depending on products. • 78K0/FY2-L: ANI0 to ANI3 • 78K0/FA2-L: ANI0 to ANI5 • 78K0/FB2-L: ANI0 to ANI8 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 338: Configuration Of A/D Converter

    Remark A/D converter analog input pins differ depending on products. • 78K0/FY2-L: ANI0 to ANI3 • 78K0/FA2-L: ANI0 to ANI5 • 78K0/FB2-L: ANI0 to ANI8 (2) Sample & hold circuit The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and sends them to the A/D voltage comparator.
  • Page 339 A/D converter. Be sure to connect V to a stabilized GND (= 0 V). Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 340: Registers Used In A/D Converter

    • 8-bit A/D conversion result register L for TMXn synchronization (ADCRXnL) Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L (1) A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
  • Page 341 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Table 11-1. Settings of ADCS and ADCE ADCS ADCE A/D Conversion Operation Stop status (DC power consumption path does not exist) Conversion waiting mode (only A/D voltage comparator consumes power) Setting prohibited Conversion mode (A/D voltage comparator operation) Figure 11-3.
  • Page 342 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Table 11-2. A/D Conversion Time Selection (1/3) (1) 4.0 V ≤ AV ≤ 5.5 V A/D Converter Mode Register 0 Mode Conversion Time Selection Conversion (ADM0) Clock = 4 MHz = 8 MHz f = 10 MHz f = 20 MHz (when using PLL)
  • Page 343 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Table 11-2. A/D Conversion Time Selection (2/3) (2) 2.7 V ≤ AV < 4.0 V A/D Converter Mode Register 0 Mode Conversion Time Selection Conversion (ADM0) Clock = 4 MHz = 8 MHz f = 10 MHz f = 20 MHz (when using PLL)
  • Page 344 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Table 11-2. A/D Conversion Time Selection (3/3) (3) 1.8 V ≤ AV < 2.7 V A/D Converter Mode Register 0 Mode Conversion Time Selection Conversion (ADM0) Clock = 4 MHz = 8 MHz f = 10 MHz f = 20 MHz (when using PLL)
  • Page 345 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Figure 11-4. A/D Converter Sampling and A/D Conversion Timing ADCS ← 1 or ADS rewrite ADCS Sampling timing INTAD Wait Sampling Sampling Successive conversion Transfer Note period clear to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, refer to CHAPTER 31 CAUTIONS FOR WAIT.
  • Page 346 78K0/Fx2-L CHAPTER 11 A/D CONVERTER (3) 8-bit A/D conversion result register L (ADCRL) This register is an 8-bit register that stores the A/D conversion result. The lower 8 bits of 10-bit resolution are stored. ADCRL can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
  • Page 347 Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L (6) 8-bit A/D conversion result register L for TMXn synchronization (ADCRXnL) ADCRXnL is an 8-bit register that holds the A/D conversion result when A/D conversion is started with the output of 16-bit timer Xn as the trigger.
  • Page 348 Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L (7) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted and sets the A/D conversion start method.
  • Page 349 (timer trigger mode set by A/D conversion trigger signal of TMX1) Setting prohibited Notes 1. Setting permitted in 78K0/FA2-L and 78K0/FB2-L. 2. Setting permitted in 78K0/FB2-L. 3. Switching the A/D conversion start method should be done after stopping the A/D conversion operation (clearing (0) ADCS).
  • Page 350 Reset signal generation clears ADPC0 and ADPC1 to 00H. Remark A/D converter analog input pins differ depending on products. • 78K0/FY2-L: ANI0 to ANI3 • 78K0/FA2-L: ANI0 to ANI5 • 78K0/FB2-L: ANI0 to ANI8 Figure 11-11. Format of A/D Port Configuration Register 0 (ADPC0) (1) 78K0/FY2-L Address: FF2EH...
  • Page 351 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Figure 11-12. Format of A/D Port Configuration Register 1 (ADPC1) (78K0/FB2-L Only) Address: FF2FH After reset: 00H Symbol ADPC1 ADPC8 ADPCS8 Digital I/O or analog input selection Analog input Digital I/O Cautions 1. Set the pin set to analog input to the input mode by using port mode register 7 (PM7).
  • Page 352 PM20 PM2n P2n pin I/O mode selection (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) Figure 11-14. Format of Port Mode Register 7 (PM7) (78K0/FB2-L Only) Address: FF27H After reset: FFH Symbol PM70...
  • Page 353 78K0/Fx2-L CHAPTER 11 A/D CONVERTER When using P20/ANI0 to P27/ANI7 and P70/ANI8, set the registers according to the pin function to be used (refer to Tables 11-3 to 11-6). Table 11-3. Setting Functions of P2n/ANIn Pin ADPC0 Register PM2 Register ADS Register P2n/ANIn Pin Digital I/O selection...
  • Page 354 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Table 11-5. Setting Functions of P26/ANI6/CMPCOM Pin ADPC0 PM2 Register CmMODSEL1 CmMODSEL0 ADS Register P26/ANI6/CMPCOM Pin Register bit (m = 0 to 2) bit (m = 0 to 2) − Digital I/O Input mode Selects ANI6. Setting prohibited selection Does not select ANI6.

  • Page 355: A/D Converter Operations

    78K0/Fx2-L CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Operations 11.4.1 Basic operations of A/D converter (software trigger mode) <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0).
  • Page 356 78K0/Fx2-L CHAPTER 11 A/D CONVERTER Remark Three types of A/D conversion result registers are available. • ADCR (16 bits): Store 10-bit A/D conversion value • ADCRH (8 bits): Store higher 8-bit of A/D conversion value • ADCRL (8 bits): Store lower 8-bit of A/D conversion value Figure 11-15.

  • Page 357: Basic Operation Of A/D Converter (Timer Trigger Mode)

    78K0/Fx2-L CHAPTER 11 A/D CONVERTER 11.4.2 Basic operation of A/D converter (timer trigger mode) <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0). <2>...
  • Page 358 • ADCRXn (16 bits) : Store 10-bit A/D conversion value • ADCRXnL (8 bits) : Store lower 8-bit of A/D conversion value n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Figure 11-16. Basic Operation of A/D Converter (Timer Trigger Mode) Conversion time Sampling time...

  • Page 359: Input Voltage And Conversion Results

    • 78K0/FY2-L: ANI0 to ANI3 • 78K0/FA2-L: ANI0 to ANI5 • 78K0/FB2-L: ANI0 to ANI8 Figure 11-14 shows the relationship between the analog input voltage and the A/D conversion result. Figure 11-17. Relationship between Analog Input Voltage and A/D Conversion Result...

  • Page 360: A/D Converter Trigger Mode Selection

    ADCS = 0 is set. Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L Caution Switching the trigger mode should be done after stopping the A/D conversion operation (clearing (0) ADCS). 11.4.5 A/D converter operation mode One channel of analog input is selected by the analog input channel specification register (ADS) and A/D conversion is executed.
  • Page 361 Notes 1. Software trigger mode: A/D conversion is started by setting (1) ADCS. Timer trigger mode: A/D conversion is started when a timer trigger signal (TMX0 or TMX1 output (78K0/FB2-L only)) is detected after ADCS is set (1). 2. Software trigger mode: ADCR, ADCRH, ADCRL registers Timer trigger mode:...
  • Page 362 78K0/Fx2-L CHAPTER 11 A/D CONVERTER The setting methods are described below. (2) Setting of Software trigger mode <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0).
  • Page 363 5. When switching from timer trigger mode to software trigger mode, switch the operation mode and input channel after stopping the A/D conversion operation (clearing (0) ADCS). Remark n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 364: How To Read A/D Converter Characteristics Table

    78K0/Fx2-L CHAPTER 11 A/D CONVERTER 11.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
  • Page 365 78K0/Fx2-L CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.

  • Page 366: Cautions For A/D Converter

    2. A/D conversion result registers differ depending on the trigger mode. • Software trigger mode: ADCR, ADCRH, ADCRL registers • Timer trigger mode: ADCRXn, ADCRXnL registers (TMXn synchronization) 3. n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 367 10 kΩ, and to connect a capacitor of about 100 pF to the ANI0 to ANI8 pins (refer to Figure 11- 22). Remark A/D converter analog input pins differ depending on products. • 78K0/FY2-L: ANI0 to ANI3 • 78K0/FA2-L: ANI0 to ANI5 • 78K0/FB2-L: ANI0 to ANI8 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 368 78K0/Fx2-L CHAPTER 11 A/D CONVERTER (7) AV pin input impedance A series resistor string of several tens of kΩ is connected between the AV and AV pins. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AV and AV pins, resulting in a large reference voltage error.
  • Page 369 3. A/D conversion result registers differ depending on the trigger mode. • Software trigger mode: ADCR, ADCRH, ADCRL registers • Timer trigger mode: ADCRXm, ADCRXmL registers (TMXm synchronization) 4. m = 0 : 78K0/FY2-L, 78K0/FA2-L m = 0, 1 : 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 370: Chapter 12 Comparators

    <1> Internal reference voltage: 3 (reference voltage level: 1.58 V (TYP.) divided by 32) <2> Input voltage from comparator common pin (CMPCOM) (78K0/FB2-L only) • An interrupt signal can be generated by detecting the valid edge of the comparator output. The valid edge can be set by using the EGPn and EGNn bits (n = 6 to 8) (refer to CHAPTER 17 INTERRUPT FUNCTIONS).
  • Page 371 (C1RVM) Note 1 Comparator output flag CMP2F CMP1F CMP0F register (CMPFLG) C2VRS4 C2VRS3 C2VRS2 C2VRS1 C2VRS0 DA2 internal reference voltage selection register (C2RVM) Note 1 Notes 1. 78K0/FA2-L and 78K0/FB2-L only 2. 78K0/FB2-L only R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 372: Configurations Of Comparator

    CnCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark 78K0/FY2-L: n = 2 78K0/FA2-L, 78K0/FB2-L: n = 0 to 2 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 373 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-2. Format of Comparator 0 Control Register (C0CTL) (78K0/FA2-L, 78K0/FB2-L) Address: FF62H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <1> <0> C0CTL CMP0EN C0DFS1 C0DFS0 C0MODSEL1 C0MODSEL0 C0OE C0INV CMP0EN Comparator 0 operation control...
  • Page 374 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-3. Format of Comparator 1 Control Register (C1CTL) (78K0/FA2-L, 78K0/FB2-L) Address: FF64H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <1> <0> C1CTL CMP1EN C1DFS1 C1DFS0 C1MODSEL1 C1MODSEL0 C1OE C1INV CMP1EN Comparator 1 operation control...
  • Page 375 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-4. Format of Comparator 2 Control Register (C2CTL) Address: FF66H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <1> <0> C2CTL CMP2EN C2DFS1 C2DFS0 C2MODSEL1 C2MODSEL0 C2OE C2INV CMP2EN Comparator 2 operation control Stops operation Enables operation Enables input to the external pins (CMP2+) on the positive and negative sides of comparator 2...
  • Page 376 78K0/Fx2-L CHAPTER 12 COMPARATORS (2) DAn internal reference voltage selection register (CnRVM) This register is used to set the internal reference voltage level of comparator. This register also controls the internal reference voltage generation operation by using bit 7 (CVRE) of C0RVM. CnRVM can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 377 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-5. Format of DA0 Internal Reference Voltage Selection Register (C0RVM) Address: FF63H After reset: 00H R/W Symbol <7> <4> <3> <2> <1> <0> C0RVM CVRE C0VRS4 C0VRS3 C0VRS2 C0VRS1 C0VRS0 CVRE Internal reference voltage generation operation control Stops operation Enables operation C0VRS4...
  • Page 378 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-6. Format of DA1 Internal Reference Voltage Selection Register (C1RVM) Address: FF65H After reset: 00H R/W Symbol <4> <3> <2> <1> <0> C1RVM C1VRS4 C1VRS3 C1VRS2 C1VRS1 C1VRS0 C1VRS4 C1VRS3 C1VRS2 C1VRS1 C1VRS0 Reference voltage level (DA1) setting 0.05 V (TYP.) 0.1 V (TYP.) 0.15 V (TYP.)
  • Page 379 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-7. Format of DA2 Internal Reference Voltage Selection Register (C2RVM) Address: FF67H After reset: 00H R/W Symbol <4> <3> <2> <1> <0> C2RVM C2VRS4 C2VRS3 C2VRS2 C2VRS1 C2VRS0 C2VRS4 C2VRS3 C2VRS2 C2VRS1 C2VRS0 Reference voltage level (DA2) setting 0.05 V (TYP.) 0.1 V (TYP.) 0.15 V (TYP.)
  • Page 380 Reset signal generation clears this register to 00H. Figure 12-8. Format of Comparator Output Flag Register (CMPFLG) (a) 78K0/FY2-L Address: FF69H After reset: 00H R Symbol <2> CMPFLG CMP2F (b) 78K0/FA2-L, 78K0/FB2-L Address: FF69H After reset: 00H R Symbol <2> <1> <0> CMPFLG CMP2F...
  • Page 381 ADPC0. ADPC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ADPC0 to 00H. Note 78K0/FB2-L only Figure 12-9. Format of A/D Port Configuration Register 0 (ADPC0) (a) 78K0/FY2-L...
  • Page 382 78K0/Fx2-L CHAPTER 12 COMPARATORS (5) External interrupt rising edge enable registers (EGPCTL0, EGPCTL1), external interrupt falling edge enable registers (EGNCTL0, EGNCTL1) EGPCTL0, EGPCTL1, EGNCTL0, and EGNCTL1 are the registers that set the INTCMP0 to INTCMP2 valid edges. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
  • Page 383 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-10. Format of External Interrupt Rising Edge Enable Registers (EGPCTL0, EGPCTL1) and External Interrupt Falling Edge Enable Registers (EGNCTL0, EGNCTL1) (2/3) (b) 78K0/FA2-L Address: FF48H After reset: 00H Symbol EGPCTL0 EGP7 EGP6 EGP3 EGP2 EGP1 EGP0 Address: FF49H After reset: 00H...
  • Page 384 Edge detection disabled Falling edge Rising edge Both rising and falling edges Caution Be sure to clear bits 1 to 7 of EGPCTL1 and EGNCTL1 to 0 in the 78K0/FB2-L. Remark n = 0 to 8 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 385 Detection Enable Bit Edge Detection Interrupt Request Signal Signal EGP6 EGN6 CMP0 output INTCMP0 EGP7 EGN7 CMP1 output INTCMP1 EGP8 EGN8 CMP2 output INTCMP2 Remark n = 8: 78K0/FY2-L n = 6 to 8: 78K0/FA2-L, 78K0/FB2-L R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 386 The output latches of P23 to P25, P26 at this time may be 0 or 1. PM2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Note 78K0/FB2-L only Figure 12-11. Format of Port Mode Register 2 (PM2) (a) 78K0/FY2-L...
  • Page 387 78K0/Fx2-L CHAPTER 12 COMPARATORS When using P23/ANI3/CMP2+, P24/ANI4/CMP0+, P25/ANI5/CMP1+, P26/ANI6/CMPCOM, set the registers according to the pin function to be used (refer to Tables 12-3 and 12-4). Table 12-3. Setting Functions of P23/ANI3/CMP2+, P24/ANI4/CMP0+, P25/ANI5/CMP1+ Pins ADPC0 PM2 Register CMPmEN bit ADS Register P23/ANI3/CMP2+, P24/ANI4/CMP0+, Register...

  • Page 388: Operations Of Comparators

    78K0/Fx2-L CHAPTER 12 COMPARATORS 12.4 Operations of Comparators 12.4.1 Starting comparator operation (using internal reference voltage for comparator reference voltage) Figure 12-12. Example of Setting Procedure When Starting Comparator Operation (Using Internal Reference Voltage for Comparator Reference Voltage) Start Setting the pin to be used as ADPC0 register setting a comparator input to analog input.
  • Page 389 78K0/Fx2-L CHAPTER 12 COMPARATORS Figure 12-13. Example of Setting Procedure When Changing Internal Reference Voltage Start Clearing (0) the CnOE bit of CnCTL and disabling CnOE bit setting the comparator output. Changing the internal reference voltage level by CnRVM register setting using the CnVRS0 to CnVRS4 bits of CnRVM.

  • Page 390: Starting Comparator Operation (Using Input Voltage From Cmpcom Pin For Comparator Reference Voltage)

    12.4.2 Starting comparator operation (using input voltage from CMPCOM pin for comparator reference voltage) Figure 12-14. Example of Setting Procedure When Starting Comparator Operation (Using Input Voltage from Comparator Common (CMPCOM) Pin for Comparator Reference Voltage (78K0/FB2-L Only)) Start Setting the pin to be used as a comparator input and ADPC0 register setting comparator common input to analog input.

  • Page 391: Chapter 13 Serial Interface Uart6

    78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 CHAPTER 13 SERIAL INTERFACE UART6 13.1 Functions of Serial Interface UART6 Serial interface UART6 are mounted onto all 78K0/Fx2-L microcontroller products. Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
  • Page 392 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Caution 6. If data is continuously transmitted, the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro. However, this does not affect the result of communication because the reception side initializes the timing when it has detected a start bit.
  • Page 393 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-2. LIN Reception Operation Wakeup Sync Sync field Identifier Data field Data field Checksum signal frame break field field field LIN Bus 13-bit Data Data Data SBF reception reception reception reception reception reception <5>...
  • Page 394 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-3. Port Configuration for LIN Reception Operation P61/SDAA0/RxD6 RXD6 input Port mode (PM61) Output latch (P61) P00/INTP0/TI000 INTP0 input Port mode Port input (PM00) switch control (ISC0) Output latch <ISC0> (P00) 0: Select INTP0 (P00) 1: Select RxD6 (P61) TI000 input Port input...

  • Page 395: Configuration Of Serial Interface Uart6

    78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 The peripheral functions used in the LIN communication operation are shown below. <Peripheral functions used> • External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. • 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the sync field (SF) length and divides it by the number of bits.
  • Page 396 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 397 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows.

  • Page 398: Registers Controlling Serial Interface Uart6

    78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 13.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following ten registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
  • Page 399 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> ASIM6 POWER6 TXE6 RXE6 PS61 PS60 ISRM6 POWER6 Enables/disables operation of internal operation clock Note 1 Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously Note 2...
  • Page 400 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
  • Page 401 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H.
  • Page 402 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
  • Page 403 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
  • Page 404 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
  • Page 405 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
  • Page 406 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
  • Page 407 INTP0 input source selection INTP0 Remark 78K0/FY2-L, 78K0/FA2-L: TI000/INTP0/P00, RxD6/SDAA0/P61 78K0/FB2-L: TI000/INTP0/P00, P121/X1/TOOLC0/<TI000>/<INTP0>, RxD6/SDAA0/P61 Port mode register 6 (PM6) This register set port 6 input/output in 1-bit units. PM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 408 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (9) Port output mode register 6 (POM6) This register sets the output mode of P60 and P61 in 1-bit units. When using the P60/TxD6/SCLA0 pin as the data output of serial interface UART6/DALI, clear POM60 to 0. This register can be set by a 1-bit or 8-bit memory manipulation instruction.

  • Page 409: Operation Of Serial Interface Uart6

    78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 13.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.

  • Page 410: Asynchronous Serial Interface (Uart) Mode

    78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 13.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
  • Page 411 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 13-2. Relationship Between Register Settings and Pins POWER TXE6 RXE6 PM60 PM61 POM60 POM61 UART6 Pin Function Operation SCLA0/ SDAA0/ Note Note Note Note Note...
  • Page 412 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-14 and 13-15 show the format and waveform example of the normal transmit/receive data. Figure 13-14. Format of Normal UART Transmit/Receive Data 1.
  • Page 413 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-15. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
  • Page 414 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
  • Page 415 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
  • Page 416 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
  • Page 417 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-17 shows an example of the continuous transmission processing flow. Figure 13-17. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6.
  • Page 418 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-18 shows the timing of starting continuous transmission, and Figure 13-19 shows the timing of ending continuous transmission. Figure 13-18. Timing of Starting Continuous Transmission Start Start Start Data (1) Parity Stop Data (2) Parity Stop INTST6...
  • Page 419 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-19. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
  • Page 420 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
  • Page 421 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
  • Page 422 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
  • Page 423 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 SBF reception When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, refer to Figure 13-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.

  • Page 424: Dedicated Baud Rate Generator

    78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
  • Page 425 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 Figure 13-25. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...

  • Page 426: Calculation Of Baud Rate

    78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 13.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. XCLK6 • Baud rate = [bps] 2 × k : Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register XCLK6 Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255) Table 13-4.
  • Page 427 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (2) Error of baud rate The baud rate error can be calculated by the following expression. Actual baud rate (baud rate with error) • Error (%) = − 1 × 100 [%] Desired baud rate (correct baud rate) Cautions 1.
  • Page 428 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
  • Page 429 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − 1 BRmax = (FLmin/11) Brate 21k + 2...
  • Page 430 78K0/Fx2-L CHAPTER 13 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.

  • Page 431: Chapter 14 Serial Interface Iica

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA CHAPTER 14 SERIAL INTERFACE IICA 14.1 Functions of Serial Interface IICA Serial interface IICA is mounted onto all 78K0/Fx2-L microcontroller products. Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLA0) line and a...
  • Page 432 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-1. Block Diagram of Serial Interface IICA Internal bus IICA status register 0 (IICAS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 0 (IICACTL0) Sub-circuit for standby IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Filter Slave address Start...
  • Page 433 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-2 shows a serial bus configuration example. Figure 14-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU1 Master CPU2 SDAA0 SDAA0 Slave CPU1 Slave CPU2 Serial clock SCLA0 SCLA0 Address 0 Address 1...

  • Page 434: Configuration Of Serial Interface Iica

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 14-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register (IICA) Slave address register 0 (SVA0) Control registers IICA control register 0 (IICACTL0) IICA status register 0 (IICAS0) IICA flag register 0 (IICAF0)
  • Page 435 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (2) Slave address register 0 (SVA0) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. This register can be set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
  • Page 436 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (11) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1. However, in the communication reservation disabled status (IICRSV bit = 1), when the bus is not released (IICBSY bit = 1), start condition requests are ignored and the STCF bit is set to 1.

  • Page 437: Registers Controlling Serial Interface Iica

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following ten registers. • IICA control register 0 (IICACTL0) • IICA status register 0 (IICAS0) • IICA flag register (IICAF0) • IICA control register 1 (IICACTL1) •...
  • Page 438 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-5. Format of IICA Control Register 0 (IICACTL0) (1/4) Address: FFA7H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICACTL0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C operation enable Note 1 Stop operation.
  • Page 439 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-5. Format of IICA Control Register 0 (IICACTL0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected Disable Enable If the WUP0 of the IICA control register 1 (IICACTL1) is 1, no stop condition interrupt will be generated even if SPIE0 = 1.
  • Page 440 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-5. Format of IICA Control Register 0 (IICACTL0) (3/4) Note STT0 Start condition trigger Do not generate a start condition. When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: •...
  • Page 441 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-5. Format of IICA Control Register 0 (IICACTL0) (4/4) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing • For master reception: Cannot be set to 1 during transfer.
  • Page 442 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (2) IICA status register 0 (IICAS0) This register indicates the status of I IICAS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears this register to 00H.
  • Page 443 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-6. Format of IICA Status Register 0 (IICAS0) (2/3) EXC0 Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1) •...
  • Page 444 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-6. Format of IICA Status Register 0 (IICAS0) (3/3) ACKD0 Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) •...
  • Page 445 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-7. Format of IICA Flag Register 0 (IICAF0) Note Address: FFA9H After reset: 00H <7> <6> <1> <0> Symbol IICAF0 STCF IICBSY STCEN IICRSV STCF STT0 clear flag Generate start condition Start condition generation unsuccessful: clear STT0 flag Condition for clearing (STCF = 0) Condition for setting (STCF = 1) •...
  • Page 446 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (4) IICA control register 1 (IICACTL1) This register is used to set the operation mode of I C and detect the statuses of the SCLA0 and SDAA0 pins. IICACTL1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only.
  • Page 447 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-8. Format of IICA Control Register 1 (IICACTL1) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) The SCLA0 pin was detected at low level. The SCLA0 pin was detected at high level. Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1) •...
  • Page 448 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (5) IICA low-level width setting register (IICWL) This register is used to set the low-level width of the SCLA0 pin signal that is output by serial interface IICA being in master mode. This register can be set by an 8-bit memory manipulation instruction. Set this register while operation of I C is disabled (bit 7 (IICE0) of the IICA control register 0 (IICACTL0) is 0).
  • Page 449 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (8) Port output mode register 6 (POM6) This register sets the output mode of P60 and P61 in 1-bit units. During I C communication, set POM60 and POM61 to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.

  • Page 450: Pin Configuration

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.4 I C Bus Mode Functions 14.4.1 Pin configuration The serial clock pin (SCLA0) and serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 ..This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.

  • Page 451: Setting Transfer Clock By Using Iicwl And Iicwh Registers

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.4.2 Setting transfer clock by using IICWL and IICWH registers (1) Setting transfer clock on master side Transfer clock = IICWL + IICWH + f At this time, the optimal setting values of the IICWL and IICWH registers are as follows. (The fractional parts of all setting values are rounded up.) •...

  • Page 452: Start Conditions

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 14-15 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I bus’s serial data bus.

  • Page 453: Addresses

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.

  • Page 454: Acknowledge (Ack)

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.

  • Page 455: Stop Condition

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.

  • Page 456: Wait

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
  • Page 457 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-21. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock IICA data write (cancel wait) IICA SCLA0...

  • Page 458: Canceling Wait

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.7 Canceling wait The I C usually cancels a wait state by the following processing. • Writing data to IICA shift register (IICA) • Setting bit 5 (WREL0) of IICA control register 0 (IICACTL0) (canceling wait) •...

  • Page 459: Interrupt Request (Intiica0) Generation Timing And Wait Control

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 0 (IICACTL0) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 14-2. Table 14-2.

  • Page 460: Address Match Detection Method

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.9 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when a local address has been set to the slave address register 0 (SVA0) and when the address set to SVA0 matches the slave address sent by the master device, or when an extension code has been received.

  • Page 461: Arbitration

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.12 Arbitration When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration.
  • Page 462 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Table 14-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...

  • Page 463: Wakeup Function

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match.
  • Page 464 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-24. Flow When Setting WUP = 0 upon Address Match (Including Extension Code Reception) STOP mode state Note INTIICA0 = 1? WUP = 0 Wait Waits for 5 clocks. Reading IICAS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
  • Page 465 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Use the following flows to perform the processing to release the STOP mode other than by an interrupt request (INTIICA0) generated from serial interface IICA. Figure 14-25. When Operating as Master Device after Releasing STOP Mode other than by INTIICA0 START SPIE0 = 1 WUP = 1...

  • Page 466: Communication Reservation

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
  • Page 467 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-26 shows the communication reservation timing. Figure 14-26. Communication Reservation Timing Write to Program processing STT0 = 1 IICA Communi- Set SPD0 cation Hardware processing STD0 reservation INTIICA0 SCLA0 SDAA0 Generate by master device with bus mastership Remark IICA: IICA shift register...
  • Page 468 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-28. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Note 1 Secures wait time by software.
  • Page 469 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) = 1) When bit 1 (STT0) of the IICA control register 0 (IICACTL0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.

  • Page 470: Cautions

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.15 Cautions (1) When STCEN (bit 1 of IICA flag register 0 (IICAF0)) = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication status (the IICBSY flag (bit 6 of the IICAF0 register) = 1) is recognized regardless of the actual bus status.

  • Page 471: Communication Operations

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the 78K0/Fx2-L microcontrollers as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing.
  • Page 472 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 14-29. Master Operation in Single-Master System START Note Initializing I C bus Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 14.3 (9) Port mode register 6 (PM6)). IICWL, IICWH ←...
  • Page 473 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 14-30. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see 14.3 (9) Port mode register 6 (PM6)). IICWL, IICWH ←...
  • Page 474 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-30. Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STT0 = 1 (generates a start condition). Note Secure wait time by software. Wait MSTS0 = 1? INTIICA0 interrupt occurs? Waits for bus release (communication being reserved).
  • Page 475 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-30. Master Operation in Multi-Master System (3/3) Starts communication Writing IICA (specifies an address and transfer direction). INTIICA0 interrupt occurs? Waits for detection of ACK. MSTS0 = 1? ACKD0 = 1? TRC0 = 1? ACKE0 = 1 WTIM0 = 0 WTIM0 = 1...
  • Page 476 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
  • Page 477 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
  • Page 478 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed.
  • Page 479 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.5.17 Timing of I C interrupt request (INTIICA0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIICA0, and the value of the IICAS0 register when the INTIICA0 signal is generated are shown below. Remark Start condition AD6 to AD0: Address...
  • Page 480 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B Note...
  • Page 481 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 SPT0 = 1 ↓ ↓ AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICAS0 = 1000×110B...
  • Page 482 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 1010×110B 2: IICAS0 = 1010×000B Note 3: IICAS0 = 1010×000B (Sets WTIM0 to 1)
  • Page 483 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 0001×000B...
  • Page 484 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B...
  • Page 485 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICAS0 = 0001×110B...
  • Page 486 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0...
  • Page 487 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0...
  • Page 488 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICAS0 = 0010×010B 2: IICAS0 = 0010×000B...
  • Page 489 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICAS0 = 0010×010B 2: IICAS0 = 0010×000B...
  • Page 490 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0...
  • Page 491 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result.
  • Page 492 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 0101×110B 2: IICAS0 = 0001×100B 3: IICAS0 = 0001××00B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care...
  • Page 493 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 0110×010B 2: IICAS0 = 0010×110B 3: IICAS0 = 0010×100B 4: IICAS0 = 0010××00B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
  • Page 494 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 0110×010B Sets LREL0 = 1 by software 2: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
  • Page 495 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICAS0 = 10001110B 2: IICAS0 = 01000100B 3: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) AD6 to AD0 R/W ACK...
  • Page 496 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (ii) Extension code AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 D7 to D0 1: IICAS0 = 1000×110B 2: IICAS0 = 01100010B Sets LREL0 = 1 by software 3: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
  • Page 497 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1)
  • Page 498 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1) 3: IICAS0 = 1000××00B (Sets STT0 to 1)
  • Page 499 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1)

  • Page 500: Timing Charts

    78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA 14.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICAS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
  • Page 501 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-33. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device IICA ← address IICA ← data Note 1 IICA ACKD0 STD0...
  • Page 502 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-33. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device IICA ← data Note 1 IICA ← data Note 1 IICA ACKD0 STD0...
  • Page 503 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-33. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device IICA ← data Note 1 IICA ← address IICA ACKD0 STD0...
  • Page 504 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-34. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address Processing by master device IICA ← address IICA ←...
  • Page 505 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-34. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Data Processing by master device IICA ← FFH Note 1 IICA ← FFH Note 1 IICA ACKD0 STD0...
  • Page 506 78K0/Fx2-L CHAPTER 14 SERIAL INTERFACE IICA Figure 14-34. Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Stop condition Processing by master device IICA ← address IICA ←...

  • Page 507: Chapter 15 Serial Interface Csi11

    78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 CHAPTER 15 SERIAL INTERFACE CSI11 Item 78K0/FY2-L (16 Pins) 78K0/FA2-L (20 Pins) 78K0/FB2-L (30 Pins) Serial interface Not mounted Mounted CSI11 15.1 Functions of Serial Interface CSI11 Serial interface CSI11 has the following two modes.
  • Page 508 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-1. Block Diagram of Serial Interface CSI11 Internal bus SO11 output Serial I/O shift Transmit buffer Output SI11/P36 register 11 (SIO11) register 11 (SOTB11) SO11/P37 selector Output latch Transmit data Output latch (P37) controller SSI11 PM35...

  • Page 509: Registers Controlling Serial Interface Csi11

    78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 (2) Serial I/O shift register 11 (SIO11) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO11 if bit 6 (TRMD11) of serial operation mode register 11 (CSIM11) is 0.
  • Page 510 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-2. Format of Serial Operation Mode Register 11 (CSIM11) Note 1 Address: FF88H After reset: 00H R/W Symbol <7> CSIM11 CSIE11 TRMD11 SSE11 DIR11 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 Note 3 Disables operation...
  • Page 511 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-3. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol CSIC11 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 Specification of data transmission/reception timing Type SCK11 D7 D6 D5 D4 D3 D2 D1 D0 SO11 SI11 input timing SCK11...
  • Page 512 At this time, the output latches of P35, P36, and P02 may be 0 or 1. PM0 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 15-4. Format of Port Mode Register 0 (PM0) (78K0/FB2-L) Address: FF20H After reset: FFH...

  • Page 513: Operation Of Serial Interface Csi11

    78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 15.4 Operation of Serial Interface CSI11 Serial interface CSI11 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 15.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the SCK11, SI11, SO11, and SSI11 pins can be used as ordinary I/O port pins in this mode.

  • Page 514: Wire Serial I/O Mode

    78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 15.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK11), serial output (SO11), and serial input (SI11) lines.
  • Page 515 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 The relationship between the register settings and pins is shown below. Table 15-2. Relationship Between Register Settings and Pins CSIE11 TRMD11 SSE11 PM36 P36 PM37 P37 PM35 P35 PM02 P02 CSI11 Pin Function Operation SO11/ SCK11/ SSI11/...
  • Page 516 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD11) of serial operation mode register 11 (CSIM11) is 1. Transmission/reception is started when a value is written to transmit buffer register 11 (SOTB11).
  • Page 517 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-6. Timing in 3-Wire Serial I/O Mode (1/2) Note (a) Transmission/reception timing (Type 1: TRMD11 = 1, DIR11 = 0, CKP11 = 0, DAP11 = 0, SSE11 = 1 Note SSI11 SCK11 Read/write trigger SOTB11 55H (communication data) SIO11...
  • Page 518 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-6. Timing in 3-Wire Serial I/O Mode (2/2) Note (b) Transmission/reception timing (Type 2: TRMD11 = 1, DIR11 = 0, CKP11 = 0, DAP11 = 1, SSE11 = 1 Note SSI11 SCK11 Read/write trigger 55H (communication data) SOTB11 SIO11...
  • Page 519 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-7. Timing of Clock/Data Phase (a) Type 1: CKP11 = 0, DAP11 = 0, DIR11 = 0 SCK11 SI11 capture SO11 Writing to SOTB11 or reading from SIO11 CSIIF11 CSOT11 (b) Type 2: CKP11 = 0, DAP11 = 1, DIR11 = 0 SCK11 SI11 capture SO11...
  • Page 520 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 (3) Timing of output to SO11 pin (first bit) When communication is started, the value of transmit buffer register 11 (SOTB11) is output from the SO11 pin. The output operation of the first bit at this time is described below. Figure 15-8.
  • Page 521 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-8. Output Operation of First Bit (2/2) (c) Type 2: CKP11 = 0, DAP11 = 1 SCK11 Writing to SOTB11 or reading from SIO11 SOTB11 SIO11 Output latch First bit 2nd bit 3rd bit SO11 (d) Type 4: CKP11 = 1, DAP11 = 1 SCK11...
  • Page 522 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 (4) Output value of SO11 pin (last bit) After communication has been completed, the SO11 pin holds the output value of the last bit. Figure 15-9. Output Value of SO11 Pin (Last Bit) (1/2) (a) Type 1: CKP11 = 0, DAP11 = 0 SCK11 ( ←...
  • Page 523 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 Figure 15-9. Output Value of SO11 Pin (Last Bit) (2/2) (c) Type 2: CKP11 = 0, DAP11 = 1 SCK11 Writing to SOTB11 or ( ← Next request is issued.) reading from SIO11 SOTB11 SIO11 Output latch SO11...
  • Page 524 78K0/Fx2-L CHAPTER 15 SERIAL INTERFACE CSI11 (5) SO11 output (refer to Figure 15-1) The status of the SO11 output is as follows depending on the setting of CSIE11, TRMD11, DAP11, and DIR11. Table 15-3. SO11 Output Status Note 1 CSIE11 TRMD11 DAP11 DIR11...

  • Page 525: Chapter 16 Multiplier

    78K0/Fx2-L CHAPTER 16 MULTIPLIER CHAPTER 16 MULTIPLIER 16.1 Functions of Multiplier The multiplier is mounted onto all 78K0/Fx2-L microcontroller products. The multiplier has the following functions. • Can execute calculation of 8 bits × 8 bits = 16 bits. • Can execute calculation of 16 bits × 16 bits = 32 bits. Figure 16-1 shows the block diagram of the multiplier.

  • Page 526: Configuration Of Multiplier

    78K0/Fx2-L CHAPTER 16 MULTIPLIER 16.2 Configuration of Multiplier (1) 16-bit higher multiplication result storage register and 16-bit lower multiplication result storage register (MUL0H, MUL0L) These two registers, MUL0H and MUL0L, are used to store a 32-bit multiplication result. In the case of multiplication of 8 bits by 8 bits, the 16 bits of the multiplication result are stored in MUL0L. In the case of multiplication of 16 bits by 16 bits, the higher 16 bits of the multiplication result are stored in MUL0H and the lower 16 bits, in MUL0L, so that a total of 32 bits of the multiplication result can be stored.
  • Page 527 78K0/Fx2-L CHAPTER 16 MULTIPLIER (2) Multiplication input data registers A, B (MULA, MULB) These are 16-bit registers that store data for multiplication. The multiplier multiplies the values of MULA and MULB. MULA and MULB can be set by an 8-bit or 16-bit memory manipulation instruction. Reset signal generation clears these registers to 0000H.

  • Page 528: Operation Of Multiplier

    78K0/Fx2-L CHAPTER 16 MULTIPLIER 16.3 Operation of Multiplier The result of the multiplication can be obtained by storing the values in the MULA and MULB registers and then reading the MUL0H and MUL0L registers after waiting for 1 clock. The result can also be obtained after 1 clock or more has without elapsed, even when fixing either of MULA or MULB and rewrite the other of these.

  • Page 529: Chapter 17 Interrupt Functions

    78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS CHAPTER 17 INTERRUPT FUNCTIONS Item 78K0/FY2-L (16 Pins) 78K0/FA2-L (20 Pins) 78K0/FB2-L (30 Pins) Maskable External 3 interrupts Internal 17.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control.
  • Page 530 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (1/2) Interrupt Internal/ Basic Default Interrupt Source Vector FY2-L FA2-L FB2-L Note Type External Configuration Priority Table Name Trigger Note 1 Type Address Pins Pins Pins Note 3 √ √ √...
  • Page 531 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1. Interrupt Source List (2/2) Interrupt Internal/ Basic Default Interrupt Source Vector FY2-L FA2-L FB2-L Note Type External Configuration Priority Table Name Trigger Note 1 Type Address Pins Pins Pins − − √ √ √...
  • Page 532 Standby release signal Remark m = 0, 1: 78K0/FY2-L m = 0 to 3: 78K0/FA2-L m = 0 to 5: 78K0/FB2-L Interrupt request flag Interrupt enable flag ISP: In-service priority flag Interrupt mask flag Priority specification flag R01UH0068EJ0203 Rev.2.03...
  • Page 533 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1. Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Interrupt Vector table Priority controller request address generator R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 534: Registers Controlling Interrupt Functions

    78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.3 Registers Controlling Interrupt Functions The following 7 types of registers are used to control the interrupt functions. • Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) • Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) •...
  • Page 535 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
  • Page 536 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/FY2-L) Address: FFE0H After reset: 00H R/W Symbol <7> <2> <1> <0> IF0L SREIF6 PIF1 PIF0 LVIIF Address: FFE1H After reset: 00H Symbol <7>...
  • Page 537 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/FA2-L) Address: FFE0H After reset: 00H R/W Symbol <7> <4> <3> <2> <1> <0> IF0L SREIF6 PIF3 PIF2 PIF1 PIF0 LVIIF Address: FFE1H After reset: 00H Symbol <7>...
  • Page 538 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-4. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) (78K0/FB2-L) Address: FFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF0L SREIF6 PIF5 PIF4 PIF3 PIF2 PIF1...
  • Page 539 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction.
  • Page 540 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-6. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/FA2-L) Address: FFE4H After reset: FFH Symbol <7> <4> <3> <2> <1> <0> MK0L SREMK6 PMK3 PMK2 PMK1 PMK0 LVIMK Address: FFE5H After reset: FFH Symbol <7>...
  • Page 541 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) (78K0/FB2-L) Address: FFE4H After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0L SREMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0...
  • Page 542 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction.
  • Page 543 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-9. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/FA2-L) Address: FFE8H After reset: FFH Symbol <7> <4> <3> <2> <1> <0> PR0L SREPR6 PPR3 PPR2 PPR1 PPR0 LVIPR Address: FFE9H After reset: FFH Symbol <7>...
  • Page 544 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/FB2-L) Address: FFE8H After reset: FFH Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR0L SREPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0...
  • Page 545 (4) Port alternate switch control register (MUXSEL) This register assigns the pin function. The interrupt input (INTP0) function can be assigned to the P121 pin of the 78K0/FB2-L. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
  • Page 546 Remark m = 0, 1: 78K0/FY2-L m = 0 to 3: 78K0/FA2-L m = 0 to 5: 78K0/FB2-L Figure 17-12. Format of External Interrupt Rising Edge Enable Registers (EGPCTL0, EGPCTL1) and External Interrupt Falling Edge Enable Registers (EGNCTL0, EGNCTL1) (1/3)
  • Page 547 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-12. Format of External Interrupt Rising Edge Enable Registers (EGPCTL0, EGPCTL1) and External Interrupt Falling Edge Enable Registers (EGNCTL0, EGNCTL1) (2/3) (b) 78K0/FA2-L Address: FF48H After reset: 00H Symbol EGPCTL0 EGP7 EGP6 EGP3 EGP2 EGP1 EGP0 Address: FF49H...
  • Page 548 Falling edge Rising edge Both rising and falling edges Caution Be sure to clear bits 1 to 7 of EGPCTL1 and EGNCTL1 to 0 in the 78K0/FB2-L. Remark n = 0 to 8 m = 0 to 5 R01UH0068EJ0203 Rev.2.03...
  • Page 549 P32 pin input INTP3 EGP6 EGN6 CMP0 output INTCMP0 EGP7 EGN7 CMP1 output INTCMP1 EGP8 EGN8 CMP2 output INTCMP2 (c) 78K0/FB2-L Detection Enable Bit Edge Detection Interrupt Request Signal Signal EGP0 EGN0 P00 or P121 pin INTP0 Note input EGP1 EGN1...
  • Page 550 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.

  • Page 551: Interrupt Servicing Operations

    78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
  • Page 552 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-14. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated...

  • Page 553: Software Interrupt Request Acknowledgment

    78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-15. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock)

  • Page 554: Multiple Interrupt Servicing

    78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1).
  • Page 555 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-17. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0)
  • Page 556 78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-17. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 1...

  • Page 557: Interrupt Request Hold

    78K0/Fx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.

  • Page 558: Chapter 18 Standby Function

    78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function The standby function is mounted onto all 78K0/Fx2-L microcontroller products. The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode.

  • Page 559: Registers Controlling Standby Function

    78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION 18.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, refer to CHAPTER 5 CLOCK GENERATOR. (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
  • Page 560 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Figure 18-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H Symbol OSTC MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status = 10 MHz = 20 MHz μ...

  • Page 561: Standby Function Operation

    78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Figure 18-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz = 20 MHz μ μ 204.8 102.4 μ...
  • Page 562 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
  • Page 563 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
  • Page 564 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-4.

  • Page 565: Stop Mode

    78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Table 18-2. Operation in Response to Interrupt Request in HALT Mode Release Source MK×× PR×× Operation × Maskable interrupt Next address request instruction execution × Interrupt servicing execution Next address instruction execution × Interrupt servicing execution ×...
  • Page 566 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Table 18-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
  • Page 567 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware.
  • Page 568 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION (2) STOP mode release Figure 18-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is Generated) STOP mode release STOP mode High-speed system clock (X1 oscillation) High-speed system clock (external clock input) Internal high-speed oscillation clock Wait for oscillation...
  • Page 569 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed.
  • Page 570 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Figure 18-6. STOP Mode Release by Interrupt Request Generation (2/2) (3) When internal high-speed oscillation clock is used as CPU clock Interrupt request STOP instruction Standby release signal Normal operation Normal operation (internal high-speed (internal high-speed Note 1 oscillation clock) STOP mode...
  • Page 571 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-7.
  • Page 572 78K0/Fx2-L CHAPTER 18 STANDBY FUNCTION Figure 18-7. STOP Mode Release by Reset (2/2) (2) When internal high-speed oscillation clock is used as CPU clock STOP instruction Reset signal Reset Normal operation Normal operation processing Reset (internal high-speed (internal high-speed (12 to 51 μs) Status of CPU oscillation clock) STOP mode...

  • Page 573: Chapter 19 Reset Function

    78K0/Fx2-L CHAPTER 19 RESET FUNCTION CHAPTER 19 RESET FUNCTION The reset function is mounted onto all 78K0/Fx2-L microcontroller products. The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of the low-voltage detector (LVI) External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is...
  • Page 574 78K0/Fx2-L CHAPTER 19 RESET FUNCTION R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 575 78K0/Fx2-L CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization (102 to 407 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing Normal operation...
  • Page 576 78K0/Fx2-L CHAPTER 19 RESET FUNCTION Figure 19-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization (102 to 407 μs) STOP instruction execution Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing...
  • Page 577 78K0/Fx2-L CHAPTER 19 RESET FUNCTION Table 19-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (X1 and X2 pins are input port mode) Clock input invalid (EXCLK pin is input port mode) EXCLK Operation stopped...
  • Page 578 Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding to each product as indicated below after release of reset. Products Internal High-Speed RAM Capacity Capacity 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L μ μ − PD78F0854 PD78F0857 4 KB 384 bytes μ...
  • Page 579 78K0/Fx2-L CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (2/4) Hardware Status After Reset Note 1 Acknowledgment Clock operation mode select register (OSCCTL) Processor clock control register (PCC) Internal oscillation mode/PLL control register (RCM) Main OSC control register (MOC) Main clock mode register (MCM) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS)
  • Page 580 78K0/Fx2-L CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (3/4) Hardware Status After Reset Note Acknowledgment A/D converter 10-bit A/D conversion result register (ADCR) 0000H 8-bit A/D conversion result register L (ADCRL) 8-bit A/D conversion result register H (ADCRH) A/D converter mode register 0 (ADM0) Analog input channel specification register (ADS) A/D port configuration register 0 (ADPC0)
  • Page 581 78K0/Fx2-L CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (4/4) Hardware Status After Reset Note 1 Acknowledgment Serial interface CSI11 Transmit buffer register 11 (SOTB11) Serial I/O shift register 11 (SIO11) Serial operation mode register 11 (CSIM11) Serial clock selection register 11 (CSIC11) Serial interface IICA IICA shift register (IICA)

  • Page 582: Register For Confirming Reset Source

    78K0/Fx2-L CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/Fx2-L microcontrollers. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.

  • Page 583: Chapter 20 Power-On-Clear Circuit

    78K0/Fx2-L CHAPTER 20 POWER-ON-CLEAR CIRCUIT CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) is mounted onto all 78K0/Fx2-L microcontroller products. The power-on-clear circuit has the following functions. • Generates internal reset signal at power on. •...

  • Page 584: Configuration Of Power-On-Clear Circuit

    78K0/Fx2-L CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 20-1. Figure 20-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 20.3 Operation of Power-on-Clear Circuit •...
  • Page 585 78K0/Fx2-L CHAPTER 20 POWER-ON-CLEAR CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) When LVI is OFF upon power application (option byte: LVISTART = 0) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt...
  • Page 586 78K0/Fx2-L CHAPTER 20 POWER-ON-CLEAR CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) When LVI is ON upon power application (option byte: LVISTART = 1) Set LVI to be Set LVI to be Set LVI to be used for interrupt used for reset...

  • Page 587: Cautions For Power-On-Clear Circuit

    78K0/Fx2-L CHAPTER 20 POWER-ON-CLEAR CIRCUIT 20.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of POR, reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
  • Page 588 78K0/Fx2-L CHAPTER 20 POWER-ON-CLEAR CIRCUIT Figure 20-3. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on-clear/external reset generated...

  • Page 589: Chapter 21 Low-Voltage Detector

    78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR CHAPTER 21 LOW-VOLTAGE DETECTOR 21.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) is mounted onto all 78K0/Fx2-L microcontroller products. The low-voltage detector has the following functions. • The LVI circuit compares the supply voltage (V ) with the LVI detection voltage (V ), and generates an internal reset or internal interrupt signal.

  • Page 590: Configuration Of Low-Voltage Detector

    78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR 21.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 21-1. Figure 21-1. Block Diagram of Low-Voltage Detector N-ch Internal reset signal − INTLVI Reference voltage source Low-voltage detection level Low-voltage detection register selection register (LVIS) (LVIM)
  • Page 591 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Note 2 Address: FFBEH After reset: 00H <7> <1> <0> Symbol LVION LVIMD LVIF LVIM Notes 3, LVION Enables low-voltage detection operation Disables operation Enables operation Note 3 LVIMD Low-voltage detection operation mode (interrupt/reset) selection...
  • Page 592 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The generation of a reset signal other than an LVI reset clears this register to 00H. Figure 21-3.

  • Page 593: Operation Of Low-Voltage Detector

    78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR 21.4 Operation of Low-Voltage Detector The low-voltage detector can be used in the following two modes. (1) Used as reset (LVIMD = 1) Compares the supply voltage (V ) and LVI detection voltage (V ), generates an internal reset signal when V <...

  • Page 594: When Used As Reset

    78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR 21.4.1 When used as reset (1) When LVI default start function stopped is set (LVISTART = 0) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS).
  • Page 595 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-4. Timing of Low-Voltage Detector Internal Reset Signal Generation (LVISTART = 0) Set LVI to be used for reset Supply voltage (V = 1.61 V (TYP.) = 1.59 V (TYP.) Time LVIMK flag Note 1 (set by software) <1>...
  • Page 596 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR (2) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as described in 21.4.1 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 21-5.

  • Page 597: When Used As Interrupt

    78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR 21.4.2 When used as interrupt (1) When LVI default start function stopped is set (LVISTART = 0) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS).
  • Page 598 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-6. Timing of Low-Voltage Detector Interrupt Signal Generation (LVISTART = 0) Supply voltage (V = 1.61 V (TYP.) = 1.59 V (TYP.) Note 3 Note 3 Time LVIMK flag (set by software) <1> Note 1 <8>...
  • Page 599 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR (2) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as described in 21.4.2 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 21-7.

  • Page 600: Cautions For Low-Voltage Detector

    78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR 21.5 Cautions for Low-Voltage Detector In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVI detection voltage ), the operation is as follows depending on how the low-voltage detector is used. Operation example 1: When used as reset The system may be repeatedly reset and released from the reset status.
  • Page 601 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-8. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset Note Check the reset source Initialization processing <1> LVI reset ;...
  • Page 602 78K0/Fx2-L CHAPTER 21 LOW-VOLTAGE DETECTOR Figure 21-8. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Power-on-clear/external reset generated Reset processing by low-voltage detector...

  • Page 603: Chapter 22 Regulator

    78K0/Fx2-L CHAPTER 22 REGULATOR CHAPTER 22 REGULATOR 22.1 Regulator Overview The 78K0/Fx2-L microcontrollers contain a circuit for operating the device with a constant voltage. At this time, in order μ to stabilize the regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1 Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.

  • Page 604: Cautions For Self Programming

    78K0/Fx2-L CHAPTER 22 REGULATOR 22.3 Cautions for Self Programming 1. Make sure that the regulator output voltage mode is fixed when executing self programming or EEPROM emulation. 2. Program area can be rewritten by using the self programming library in normal power mode. 3.

  • Page 605: Chapter 23 Option Byte

    78K0/Fx2-L CHAPTER 23 OPTION BYTE CHAPTER 23 OPTION BYTE 23.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/Fx2-L microcontrollers is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions.

  • Page 606: Format Of Option Byte

    78K0/Fx2-L CHAPTER 23 OPTION BYTE (3) 0082H/1082H  Internal high-speed oscillation clock frequency selection • 4 MHz (TYP.) • 8 MHz (TYP.) Caution Set a value that is the same as that of 0082H to 1082H because 0082H and 1082H are switched during the boot swap operation.
  • Page 607 78K0/Fx2-L CHAPTER 23 OPTION BYTE Figure 23-1. Format of Option Byte (1/3) Note Address: 0080H/1080H WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC WINDOW1 WINDOW0 Watchdog timer window open period 100% WDTON Operation control of watchdog timer counter/illegal access detection Counter operation disabled (counting stopped after reset), illegal access detection operation disabled Counter operation enabled (counting started after reset), illegal access detection operation enabled WDCS2...
  • Page 608 78K0/Fx2-L CHAPTER 23 OPTION BYTE Figure 23-1. Format of Option Byte (2/3) Notes 1, 2 Address: 0081H/1081H LVISTART LVISTART LVI default start operation control LVI is OFF by default upon power application (LVI default start function stopped) LVI is ON by default upon power application (LVI default start function enabled) Notes 1.
  • Page 609 78K0/Fx2-L CHAPTER 23 OPTION BYTE Figure 23-1. Format of Option Byte (3/3) Note Address: 0083H/1083H OCDPSEL OCDPSEL Pin selection used during on-chip debugging TOOLC1/P31, TOOLD1/P32 TOOLC0/X1, TOOLD0/X2 Note Set a value that is the same as that of 0083H to 1083H because 0083H and 1083H are switched during the boot swap operation.
  • Page 610 78K0/Fx2-L CHAPTER 23 OPTION BYTE Here is an example of description of the software for setting the option bytes. CSEG AT 0080H OPTION: DB ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ;...

  • Page 611: Chapter 24 Flash Memory

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY CHAPTER 24 FLASH MEMORY The 78K0/Fx2-L microcontrollers incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 24.1 Internal Memory Size Switching Register Select the internal memory capacity using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction.

  • Page 612: Writing With Flash Memory Programmer

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY Table 24-1. Set Values of Internal Memory Size Switching Register Products IMS Setting 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L μ μ − PD78F0854 PD78F0857 μ μ μ PD78F0855 PD78F0858 PD78F0864 μ μ μ PD78F0856 PD78F0859 PD78F0865 24.2 Writing with Flash Memory Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.

  • Page 613: Programming Environment

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.3 Programming Environment The environment required for writing a program to the flash memory of the 78K0/Fx2-L microcontrollers are illustrated below. Figure 24-2. Environment for Writing Program to Flash Memory (1) When using the TOOLC0 and TOOLD0 pins QB-MINI2 FlashPro5 RS-232-C...

  • Page 614: Connection Of Pins On Board

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.4 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.

  • Page 615: Reset Pin

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.4.2 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator.

  • Page 616: On-Board Writing When Connecting Crystal/Ceramic Resonator

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.4.7 On-board writing when connecting crystal/ceramic resonator To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.

  • Page 617: Programming Method

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.5 Programming Method 24.5.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 24-6. Flash Memory Manipulation Procedure Start Flash memory programming mode is set Manipulate flash memory End? 24.5.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0/Fx2-L microcontrollers in the flash memory programming mode.
  • Page 618 78K0/Fx2-L CHAPTER 24 FLASH MEMORY Table 24-5. Flash Memory Control Commands Classification Command Name Function Verify Verify Compares the contents of a specified area of the flash memory with data transmitted from the programmer. Erase Chip Erase Erases the entire flash memory. Block Erase Erases a specified area in the flash memory.

  • Page 619: Security Settings

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.6 Security Settings The 78K0/Fx2-L microcontrollers support a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
  • Page 620 78K0/Fx2-L CHAPTER 24 FLASH MEMORY Table 24-7. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be Can be performed erased.

  • Page 621: Processing Time For Each Command When Pg-Fp5 Is Used (Reference)

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.7 Processing Time for Each Command When PG-FP5 Is Used (Reference) The following table shows the processing time for each command (reference) when the PG-FP5 is used as a dedicated flash memory programmer. Table 24-9. Processing Time for Each Command When PG-FP5 Is Used (Reference) (1/2) (1) Products with internal ROMs of the 4 KB: μPD78F0854, 78F0857 Command of PG-FP5 Port: UART-Internal-OSC (Internal high-speed oscillation clock (f...
  • Page 622 78K0/Fx2-L CHAPTER 24 FLASH MEMORY Table 24-9. Processing Time for Each Command When PG-FP5 Is Used (Reference) (2/2) (3) Products with internal ROMs of the 16 KB: μPD78F0856, 78F0859, 78F0865 Command of PG-FP5 Port: UART-Internal-OSC (Internal high-speed oscillation clock (f : 8 MHz (typ.)), Speed: 500,000 bps Signature...

  • Page 623: Flash Memory Programming By Self-Programming

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.8 Flash Memory Programming by Self-Programming The 78K0/Fx2-L microcontrollers support a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/Fx2-L microcontroller self-programming library, it can be used to upgrade the program in the field.

  • Page 624: Register Controlling Self Programming Mode

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.8.1 Register controlling self programming mode The self programming mode is controlled by the self programming mode control register (FPCTL). FPCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears FPCTL to 00H. Figure 24-8.
  • Page 625 78K0/Fx2-L CHAPTER 24 FLASH MEMORY Figure 24-9. Flow of Self Programming (Rewriting Flash Memory) Start of self programming Setting FLMDPUP to 1 FlashStart Setting operating environment FlashEnv CheckFLMD FlashBlockBlankCheck Normal completion? FlashBlockErase FlashWordWrite FlashBlockVerify Normal completion? FlashBlockErase FlashWordWrite FlashBlockVerify Normal completion? Normal completion Error...

  • Page 626: Boot Swap Function

    78K0/Fx2-L CHAPTER 24 FLASH MEMORY 24.8.3 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem. Note Before erasing boot cluster 0 , which is a boot program area, by self-programming, write a new boot program to boot...
  • Page 627 78K0/Fx2-L CHAPTER 24 FLASH MEMORY Figure 24-11. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 Program Program Program Program Program Program Program Boot Program cluster 1 Program Program 1 0 0 0 H Boot program Boot program Boot program...

  • Page 628: Creating Rom Code To Place Order For Previously Written Product

    CHAPTER 24 FLASH MEMORY 24.9 Creating ROM Code to Place Order for Previously Written Product Before placing an order with Renesas Electronics for a previously written product, the ROM code for the order must be created. To create the ROM code, use the Hex Consolidation Utility (hereafter abbreviated to HCU) on the finished programs (hex files) and optional data (such as security settings for flash memory programs).

  • Page 629: Chapter 25 On-Chip Debug Function

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. When transitioning to STOP mode during on-chip debugging, oscillation of the internal high- speed oscillator continues, but the on-chip debug operation is not affected.
  • Page 630 78K0/Fx2-L CHAPTER 25 ON-CHIP DEBUG FUNCTION Figure 25-1. Connection Example of QB-MINI2 and 78K0/Fx2-L Microcontrollers (1/3) (1) When using the TOOLC0 and TOOLD0 pins (X1 oscillator or EXCLK input clock is not used, both debugging and programming are performed) Target connector Target device 3 k to 10 kΩ...
  • Page 631 78K0/Fx2-L CHAPTER 25 ON-CHIP DEBUG FUNCTION Figure 25-1. Connection Example of QB-MINI2 and 78K0/Ix2 Microcontrollers (2/3) (2) When using the TOOLC0 and TOOLD0 pins (with X1/X2 oscillator is used, both debugging and programming are performed) Target connector Target device Note 1 RESET_OUT RESET Note 3...

  • Page 632: On-Chip Debug Security Id

    78K0/Fx2-L CHAPTER 25 ON-CHIP DEBUG FUNCTION Figure 25-1. Connection Example of QB-MINI2 and 78K0/Fx2-L Microcontrollers (3/3) (3) When using the TOOLC1 and TOOLD1 pins (both debugging and programming are performed) Target connector Target device 3 k to 10 kΩ Note 1 RESET_OUT RESET Note 3...

  • Page 633: Securing Of User Resources

    78K0/Fx2-L CHAPTER 25 ON-CHIP DEBUG FUNCTION Table 25-1. On-Chip Debug Security ID Address On-Chip Debug Security ID 0085H to 008EH Any ID code of 10 bytes 1085H to 108EH 25.3 Securing of User Resources QB-MINI2 uses the user memory spaces (shaded portions in Figure 25-2) to implement communication with the target device, or each debug functions.

  • Page 634: Chapter 26 Instruction Set

    78K0/Fx2-L CHAPTER 26 INSTRUCTION SET CHAPTER 26 INSTRUCTION SET This chapter lists each instruction set of the 78K0/Fx2-L microcontrollers in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 26.1 Conventions Used in Operation List 26.1.1 Operand identifiers and specification methods Operands are written in the “Operand”...

  • Page 635: Description Of Operation Column

    78K0/Fx2-L CHAPTER 26 INSTRUCTION SET 26.1.2 Description of operation column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...

  • Page 636: Operation List

    78K0/Fx2-L CHAPTER 26 INSTRUCTION SET 26.2 Operation List Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − r ← byte 8-bit data r, #byte transfer (saddr) ← byte saddr, #byte − sfr ← byte sfr, #byte Note 3 −...
  • Page 637 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − rp ← word 16-bit data MOVW rp, #word transfer (saddrp) ← word saddrp, #word − sfrp ← word sfrp, #word AX ←...
  • Page 638 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A, CY ← A − byte × × × 8-bit A, #byte operation (saddr), CY ← (saddr) − byte ×...
  • Page 639 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − A ← A ∨ byte × 8-bit A, #byte operation (saddr) ← (saddr) ∨ byte × saddr, #byte Note 3 −...
  • Page 640 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − AX, CY ← AX + word × × × 16-bit ADDW AX, #word operation − AX, CY ← AX − word ×...
  • Page 641 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 CY ← CY ∧ (saddr.bit) × AND1 CY, saddr.bit manipulate − CY ← CY ∧ sfr.bit × CY, sfr.bit − CY ←...
  • Page 642 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 − (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) Call/return CALL !addr16 PC ← addr16, SP ← SP − 2 −...
  • Page 643 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET Clocks Flag Instruction Mnemonic Operands Bytes Operation Group Z AC CY Note 1 Note 2 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 Conditional saddr.bit, $addr16 branch − PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr16 −...

  • Page 644: Instructions Listed By Addressing Type

    78K0/Fx2-L CHAPTER 26 INSTRUCTION SET 26.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Note Second Operand #byte saddr !addr16...
  • Page 645 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note Second Operand #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp...
  • Page 646 78K0/Fx2-L CHAPTER 26 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruction BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 647: Chapter 27 Electrical Specifications ((A) Grade Products)

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
  • Page 648 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) (2) Non-port functions Function 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L 16 Pins 20 Pins 30 Pins Power supply, , AV , AV , AV ground Regulator REGC Reset RESET Clock X1, X2, EXCLK oscillation Interrupt...
  • Page 649 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +6.5 Supply voltage −0.5 to +0.3 −0.5 to V...
  • Page 650 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit −10 Output current, high Per pin P00 to P02, P30 to P37, P60, P61...
  • Page 651 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. X1 Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = AV = 0 V) Resonator Recommended Circuit...
  • Page 652 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Internal High-speed Oscillator Characteristics = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, V = AV = 0 V) Resonator...
  • Page 653 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (1/5) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 654 0.7V alternate function is disabled (default), INTP0SEL0 = TM00SEL0 = 0 When switching with 0.7V alternate function is enabled (78K0/FB2-L only), INTP0SEL0 = 1 or TM00SEL0 = 1 Input voltage, low P37, P122 0.3V P20 to P27, P70 0.3AV P60, P61 (I/O port mode) 0.3V...
  • Page 655 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (3/5) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 656 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (4/5) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 657 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Notes 1. Total current flowing into the internal power supply (V ), including the input leakage current flowing when the level of the input pin is fixed to V or V . However, the current flowing into the pull-up resistors, the pull-down resistors and the output current of the port are not included.
  • Page 658 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (5/5) = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 659 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. AC Characteristics (1) Basic operation = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 660 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. vs. V (Main System Clock Operation, RMC = 00H (Normal Power Mode)) Guaranteed operation range 0.01 Supply voltage V R01UH0068EJ0203 Rev.2.03...
  • Page 661 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. vs. V (Main System Clock Operation, RMC = 56H (Low Power Mode)) Guaranteed operation range 0.01 Supply voltage V AC Timing Test Points...
  • Page 662 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TI Timing TIL0 TIH0 TI000, TI010 TIL5 TIH5 TI51 Interrupt Request Input Timing INTL INTH INTP0 to INTP5 RESET Input Timing...
  • Page 663 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) Serial interface = −40 to +85°C, 1.8 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 664 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (b) IICA Parameter Symbol Conditions Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. ≥...
  • Page 665 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (c) CSI11 (master mode, SCK11... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤...
  • Page 666 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing IICA: SCLA0 HD: DAT HIGH SU: STA HD: STA SU: STO HD: STA SU: DAT SDAA0...
  • Page 667 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Analog Characteristics (1) A/D Converter = −40 to +85°C, 1.8 V ≤ AV ≤ V ≤...
  • Page 668 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) Comparator = −40 to +85°C, 2.7 V ≤ AV ≤ V ≤ 5.5 V, V = AV = 0 V) Parameter...
  • Page 669 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (3) POC = −40 to +85°C, V = 0 V) Parameter Symbol Conditions MIN. TYP.
  • Page 670 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (4) Supply Voltage Rise Time = −40 to +85°C, V = 0 V) Parameter Symbol Conditions MIN.
  • Page 671 78K0/Fx2-L CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (5) LVI = −40 to +85°C, V ≤ V ≤ 5.5 V, AV ≤ V = 0 V) Parameter Symbol...
  • Page 672 15 years erase = power programmer is Note 1 rewrite mode used, and the (RMC = libraries provided 00H) by Renesas Electronics are used When the Retention: 10000 Times EEPROM 5 years emulation libraries provided by Renesas Electronics are...

  • Page 673: Chapter 28 Electrical Specifications ((A2) Grade Products)

    Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
  • Page 674 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (2) Non-port functions Function 78K0/FY2-L 78K0/FA2-L 78K0/FB2-L 16 Pins 20 Pins 30 Pins Power supply, , AV , AV , AV ground Regulator REGC Reset RESET Clock X1, X2, EXCLK oscillation Interrupt...
  • Page 675 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +6.5 Supply voltage −0.5 to +0.3 −0.5 to V...
  • Page 676 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit −10 Output current, high Per pin P00 to P02, P30 to P37, P60, P61...
  • Page 677 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. X1 Oscillator Characteristics = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EV = AV = 0 V)
  • Page 678 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Internal High-speed Oscillator Characteristics = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, V = EVss = AV = 0 V) Resonator...
  • Page 679 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (1/5) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 680 0.7V alternate function is disabled (default), INTP0SEL0 = TM00SEL0 = 0 When switching with 0.7V alternate function is enabled (78K0/FB2-L only), INTP0SEL0 = 1 or TM00SEL0 = 1 Input voltage, low P37, P122 0.3V P20 to P27, P70 0.3AV P60, P61 (I/O port mode) 0.3V...
  • Page 681 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (3/5) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 682 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (4/5) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 683 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Notes 1. Total current flowing into the internal power supply (V ), including the input leakage current flowing when the level of the input pin is fixed to V or V . However, the current flowing into the pull-up resistors, the pull-down resistors and the output current of the port are not included.
  • Page 684 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (5/5) = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 685 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. AC Characteristics (1) Basic operation = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 686 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. vs. V (Main System Clock Operation, RMC = 00H (Normal Power Mode)) Guaranteed operation range 0.01 Supply voltage V R01UH0068EJ0203 Rev.2.03...
  • Page 687 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. vs. V (Main System Clock Operation, RMC = 56H (Low Power Mode)) Guaranteed operation range 0.01 Supply voltage V AC Timing Test Points...
  • Page 688 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TI Timing TIL0 TIH0 TI000, TI010 TIL5 TIH5 TI51 Interrupt Request Input Timing INTL INTH INTP0 to INTP5 RESET Input Timing...
  • Page 689 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) Serial interface = −40 to +125°C, 2.7 V ≤ V ≤ 5.5 V, AV ≤...
  • Page 690 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (b) IICA Parameter Symbol Conditions Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. ≥...
  • Page 691 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (c) CSI11 (master mode, SCK11... internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤...
  • Page 692 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing IICA: SCLA0 HD: DAT HIGH SU: STA HD: STA SU: STO HD: STA SU: DAT SDAA0...
  • Page 693 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Analog Characteristics (1) A/D Converter = −40 to +125°C, 2.7 V ≤ AV ≤ V ≤...
  • Page 694 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) Comparator = −40 to +125°C, 2.7 V ≤ AV ≤ V ≤ 5.5 V, V = AV = 0 V) Parameter...
  • Page 695 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. = −40 to +125°C, V = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage 1.52...
  • Page 696 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (4) Supply Voltage Rise Time = −40 to +125°C, V = 0 V) Parameter Symbol Conditions MIN.
  • Page 697 78K0/Fx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (5) LVI = −40 to +125°C, V ≤ V ≤ 5.5 V, AV ≤ V =0 V) Parameter Symbol...
  • Page 698 15 years erase = power programmer is Note 1 rewrite mode used, and the (RMC = libraries provided 00H) by Renesas Electronics are used When the Retention: 10000 Times EEPROM 5 years emulation libraries provided by Renesas Electronics are...

  • Page 699: Chapter 29 Package Drawings

    78K0/Fx2-L CHAPTER 29 PACKAGE DRAWINGS CHAPTER 29 PACKAGE DRAWINGS 29.1 78K0/FY2-L μ • PD78F0854MAA-FAA-G, 78F0855MAA-FAA-G, 78F0856MAA-FAA-G, 78F0854MAA2-FAA-G, 78F0855MAA2-FAA-G, 78F0856MAA2-FAA-G 16-PIN PLASTIC SSOP (4.4x5.0) detail of lead end (UNIT:mm) ITEM DIMENSIONS ± 5.00 0.15 ± 5.20 0.15 ± 4.40 0.20 ± 6.40 0.20 1.725 MAX.

  • Page 700: K0/Fa2-L

    78K0/Fx2-L CHAPTER 29 PACKAGE DRAWINGS 29.2 78K0/FA2-L μ • PD78F0857MCA-CAA-G, 78F0858MCA-CAA-G, 78F0859MCA-CAA-G, 78F0857MCA2-CAA-G, 78F0858MCA2-CAA-G, 78F0859MCA2-CAA-G 20-PIN PLASTIC SSOP (7.62 mm (300)) detail of lead end (UNIT:mm) ITEM DIMENSIONS 6.50±0.10 0.325 0.65 (T.P.) 0.22 +0.10 NOTE −0.05 Each lead centerline is located within 0.13 mm 0.10±0.05 of its true position (T.P.) at maximum material 1.30±0.10...

  • Page 701: K0/Fb2-L

    78K0/Fx2-L CHAPTER 29 PACKAGE DRAWINGS 29.3 78K0/FB2-L μ • PD78F0864MCA-CAB-G, 78F0865MCA-CAB-G, 78F0864MCA2-CAB-G, 78F0865MCA2-CAB-G 30-PIN PLASTIC SSOP (7.62mm (300)) detail of lead end (UNIT:mm) ITEM DIMENSIONS 9.70±0.10 0.30 0.65 (T.P.) NOTE 0.22 +0.10 −0.05 Each lead centerline is located within 0.13 mm of its 0.10±0.05...

  • Page 702: Chapter 30 Recommended Soldering Conditions

    CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an Renesas Electronics sales representative. For technical information, see the following website.

  • Page 703: Chapter 31 Cautions For Wait

    ) is stopped, do not access the registers listed above using an access method in which a wait request is issued. Remarks 1. n = 0 : 78K0/FY2-L, 78K0/FA2-L n = 0, 1 : 78K0/FB2-L 2. The clock is the CPU clock (f R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 704 78K0/Fx2-L CHAPTER 31 CAUTIONS FOR WAIT Table 31-1. Registers That Generate Wait and Number of CPU Wait Clocks (2/2) Peripheral Register Access Number of Wait Clocks Hardware Serial interface ASIS6 Read 1 clock (fixed) UART6 Serial interface IICAS0 Read 1 clock (fixed) IICA A/D converter ADM0...

  • Page 705: Appendix A Development Tools

    78K0/Fx2-L APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/Fx2-L microcontrollers. Figure A-1 shows the development tool configuration. R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...
  • Page 706 Notes 1. Download the device file for 78K0/Fx2-L microcontrollers (DF780865) and the integrated debugger ID78K0- QB from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). The project manager PM+ is included in the assembler package. PM+ cannot be used other than with Windows Instruction simulation version is included in the software package.
  • Page 707 Notes 1. Download the device file for 78K0/Fx2-L microcontrollers (DF780865) and the integrated debugger ID78K0- QB from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). The project manager PM+ is included in the assembler package. PM+ cannot be used other than with Windows.

  • Page 708: A.1 Software Package

    If the versions of RA78K0 and CC78K0 are Ver.4.00 or later, different versions of RA78K0 and CC78K0 can be installed on the same machine. The DF780865 can be used in common with the RA78K0, CC78K0, ID78K0-QB, and system simulator. Download the DF780865 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). R01UH0068EJ0203 Rev.2.03 Jun 29, 2012...

  • Page 709: A.3 Flash Memory Programming Tools

    • FA-78F0557MA-FAA-RX : For 78K0/FY2-L FA-78F0756MC-CAB-RX • FA-78F0567MC-CAA-RX : For 78K0/FA2-L Flash memory programming adapter • FA-78F0756MC-CAB-RX : For 78K0/FB2-L Remarks 1. FL-PR5, FA-78F0557MA-FAA-RX, FA-78F0567MC-CAA-RX, and FA-78F0756MC-CAB-RX are products of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-42-750-4172 Naito Densei Machida Mfg. Co., Ltd.

  • Page 710: A.4 Debugging Tools (Hardware)

    78K0-OCD board. Target connector specifications 16-pin general-purpose connector (2.54 mm pitch) Remark Download the software for operating the QB-MINI2 from the download site for development tools (http://www2.renesas.com/micro/en/ods/index.html). A.5 Debugging Tools (Software) Note ID78K0-QB This debugger supports the in-circuit emulators for the 78K0 microcontrollers. The Integrated debugger ID78K0-QB is Windows-based software.

  • Page 711: Appendix B Revision History

    78K0/Fx2-L APPENDIX B REVISION HISTORY APPENDIX B REVISION HISTORY B.1 Major Revisions in This Edition Page Description Classification CHAPTER 21 LOW-VOLTAGE DETECTOR p.594 Modification of When LVI default start function stopped is set (LVISTART = 0) p.597 Modification of When LVI default start function stopped is set (LVISTART = 0) CHAPTER 27 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS) p.655 Modification of Pull-up resistor in DC Characteristics (3/5)

  • Page 712: B.2 Revision History Of Preceding Editions

    When Using Alternate Function (78K0/FA2-L) (1/2) Addition of Note 3 to Table 4-14 Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/FB2-L) (2/2) Addition of Note to Figure 5-1 Block Diagram of Clock Generator CHAPTER 5 CLOCK...
  • Page 713 Addition of 6.4 (1) Interval timer operation to (3) Capture function Change of 6.5 (1) PWM output operation (single output) to (4) PWM output operation (TMX0 and TMX1 synchronous start mode) (78K0/FB2-L only) Addition of Notes 1, 2 to Figure 6-43 Block Diagram of 16-Bit Timer X0 Output Configuration to Figure 6-45.
  • Page 714 (EGNCTL0, EGNCTL1) Change of Figure 12-2 Format of Comparator 0 Control Register (C0CTL) (78K0/FA2-L, 78K0/FB2-L) to Figure 12-4 Format of Comparator 2 Control Register (C2CTL) Change of Figure 12-5 Format of DA0 Internal Reference Voltage Selection Register...
  • Page 715 78K0/Fx2-L APPENDIX B REVISION HISTORY (4/6) Edition Description Chapter Change of Figure 19-1 Block Diagram of Reset Function to Figure 19-4 Timing of CHAPTER 19 RESET Rev.2.00 Reset in STOP Mode by RESET Input FUNCTION CHAPTER 20 POWER- Deletion of Note that “These are preliminary values and subject to change”. ON-CLEAR CIRCUIT Change of Figure 20-2 Timing of Generation of Internal Reset Signal by Power-on- Clear Circuit and Low-Voltage Detector...
  • Page 716 Rev.2.01 Modification of, and addition of Notes 2, 3 to Table 2-2. Pin I/O Circuit Types CHAPTER 2 PIN (78K0/FY2-L) to Table 2-4. Pin I/O Circuit Types (78K0/FB2-L) FUNCTIONS Modification of Table 3-6. Special Function Register List CHAPTER 3 CPU ARCHITECTURE Modification of Figure 6-3.
  • Page 717 TIMERS X0 AND X1 Modification of Figure 6-22. (d) 16-bit timer X1 operation control register 1 (TX1CTL1) (78K0/FB2-L only) Modification of 6.4 (3) Capture function Modification of Remarks 1. and Remarks 2. in 6.4 (3) Capture function Change of Figure 6-24. Basic Timing Example of Capture Function Operation Modification of Remarks 1.
  • Page 718 78K0/Fx2-L User’s Manual: Hardware Publication Date: Rev.0.01 Sep 9, 2009 Rev.2.03 Jun 29, 2012 Published by: Renesas Electronics Corporation...
  • Page 719 SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada...
  • Page 720 78K0/Fx2-L R01UH0068EJ0203...

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