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7542 Group
(14) Port P3
0
Direction
register
Data bus
Port latch
Capture 1 input
Capture 1 input control
(16) Port P3
3
Direction
register
Data bus
Port latch
INT
input control
1
INT
input
1
(18) Port P3
6
Direction
register
Data bus
Port latch
INT
input control
1
INT
input
1
P1
, P1
, P1
, P3
0
2
3
*
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 22 Block diagram of ports (3)
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Pull-up control
Drive capacity
control
Pull-up control
Drive capacity
control
Pull-up control
Drive capacity
control
P3 input level
selection bit
*
, and P3
input level are switched to the CMOS/TTL level by the port P1P3 control register.
6
7
Page 23 of 134
(15) Ports P3
P3
1,
2
Compare output control
Direction
register
Data bus
Port latch
Compare output
(17) Ports P3
P3
4,
5
Direction
register
Data bus
Port latch
(19) Port P3
7
Direction
register
Data bus
Port latch
INT
input
0
Pull-up control
Drive capacity
control
Pull-up control
Drive capacity
control
Pull-up control
Drive capacity
control
P3 input level
selection bit
*
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