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7542 Group
(1) Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an "H" level and the X
oscillator stops. At this time, timer 1 is set
IN
to "01
" and prescaler 1 is set to "FF
16
bilization time set bit after release of the STP instruction is "0". On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is "1". Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. f(X
connected to the input of prescaler 1. When an external interrupt
is accepted, oscillation is restarted but the internal clock φ remains
at "H" until timer 1 underflows. As soon as timer 1 underflows, the
internal clock φ is supplied. This is because when a ceramic oscil-
lator is used, some time is required until a start of oscillation. In
case oscillation is restarted by reset, no wait time is generated. So
apply an "L" level to the RESET pin while oscillation becomes
stable, or set the wait time by on-chip oscillator operation after
system is released from reset until the oscillation is stabled.
With the FLASH version, the internal power supply circuit is
changed to low power consumption mode for consumption current
reduction at the time of STP instruction execution.
Although an internal power supply circuit is usually changed to the
normal operation mode at the time of the return from an STP in-
struction, since a certain time is required to start the power supply
to FLASH and operation of FLASH to be enabled, set wait time
100 µs or more with the FLASH version by the oscillation stabiliza-
tion time set function after release of the STP instruction which
used the timer 1.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
"H" level, but the oscillator does not stop. The internal clock re-
starts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to "1" before the STP or WIT instruction is executed.
Notes on Clock Generating Circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to "1", set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting an on-chip os-
cillator. Then, a ceramic oscillation or an RC oscillation is selected
by setting bit 5 of the CPU mode register.
• Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
" when the oscillation sta-
16
)/16 is forcibly
IN
Page 61 of 134
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU "M37542RSS" is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
• Clock division ratio, X
oscillation control, on-chip oscillator control
IN
The state transition shown in Fig. 81 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), X
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 81.
• Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O,
Serial I/O2, A/D converter, Watchdog timer)
A count source of watchdog timer is affected by the clock divi-
sion selection bit of the CPU mode register.
The f(X
) clock is supplied to the watchdog timer when select-
IN
ing f(X
) as the CPU clock.
IN
The on-chip oscillator output is supplied to the watchdog timer
when selecting the on-chip oscillator output as the CPU clock.
b7
b0
CPU mode register
(CPUM: address 003B
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
"M37542RSS".)
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 77 Structure of CPU mode register
oscillation
IN
, initial value: 80
)
16
16
Processor mode bits (Note 1)
b1 b0
0
0 Single-chip mode
0
1
Not available
1
0
1
1
Stack page selection bit
0 : 0 page
1 : 1 page
On-chip oscillator oscillation control bit
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
X
oscillation control bit
IN
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
Oscillation mode selection bit (Note 1)
0 : Ceramic oscillation
1 : RC oscillation
Clock division ratio selection bits
b7 b6
0
0 : f(φ) = f(X
)/2 (High-speed mode)
IN
0
1 : f(φ) = f(X
)/8 (Middle-speed mode)
IN
1
0 : applied from on-chip oscillator
1
1 : f(φ) = f(X
) (Double-speed mode)(Note 2)
IN
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