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7542 Group
Timers
The 7542 Group has 4 timers: timer 1, timer X, timer A and timer
B.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches "0", an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to "1".
• Frequency divider for timer
According to the clock division selection bits (b7 and b6) of CPU
mode register (003B
), the count source of frequency divider is
16
set as follows;
b7b6 = "00"(high-speed), "01"(middle-speed), "11"(double-speed): X
b7b6 = "10"(On-chip oscillator): On-chip oscillator
Timer 1
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
"1".
Prescaler 1 is an 8-bit prescaler and counts the signal which is the
oscillation frequency divided by 16.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows. The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is writ-
ten to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex-
ecuted, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal which is the oscillation frequency di-
vided by 16. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach "00
", an underflow occurs at the next count clock, and
16
the prescaler 1 latch is reloaded into Prescaler 1 and count contin-
ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the under-
flow signal of Prescaler 1 is input. When the contents of Timer 1
reach "00
", an underflow occurs at the next count clock, and the
16
timer 1 latch is reloaded into Timer 1 and count continues. The di-
vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1) (m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Timer 1 cannot stop counting by software.
Rev.3.02
Oct 31, 2006
REJ03B0006-0302
Page 30 of 134
Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to "1".
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows.The value of timer X latch is set to Timer X when Timer
X underflows.
When writing to Prescaler X (PREX) is executed, the value is writ-
ten to both the prescaler X latch and Prescaler X.
When writing to Timer X (TX) is executed, the value is written to
both the timer X latch and Timer X.
IN
When reading from Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, each count value is read out.
Timer X can be selected in one of 4 operating modes by setting
the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach "00
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) pro-
vided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the under-
flow signal of Prescaler X is input. When the contents of Timer X
reach "00
", an underflow occurs at the next count clock, and the
16
timer X latch is reloaded into Timer X and count continues. The di-
vision ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1) (m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR
The output level of CNTR
tive edge switch bit. When the CNTR
the output of CNTR
0
the output is started at "L" level.
Also, the inverted waveform of pulse output from CNTR
be output from TX
OUT
valid bit.
When using a timer in this mode, set the port P1
tion registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P1
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR
rising or falling by the CNTR
", an underflow occurs at the next count
16
pin can be selected by the CNTR
0
active edge switch bit is "0",
0
pin is started at "H" level. When this bit is "1",
pin by setting "1" to the P0
/CNTR
4
pin input signal can be selected from
0
active edge switch bit .
0
pin.
0
ac-
0
pin can
0
/TX
output
3
OUT
and P0
direc-
4
3
pin.
0
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