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Renesas V850 Series User Manual

Renesas V850 Series User Manual

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V850E2/PG4-L

32

Renesas microcomputers

V850 Series

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.02

Jul 2014

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Summary of Contents for Renesas Renesas V850 Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 Notes for CMOS devices (1) Voltage Waveform distortion due to input noise or a reflected wave may cause application malfunction. If the input of the CMOS device stays in the area between VIL wafeform at input (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take pin: care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through...
Page 4 How to Use This Manual Readers This manual is intended for users who wish to understand the functions of the V850E2/PG4-L and design application systems using the following V850E2/ PG4-L microcontrollers: Purpose This manual is intended to give users an understanding of the hardware functions of the V850E2/PG4-L shown in the Organization below.
Page 5 Table of Contents Section 1 Introduction ....................21 Overview............................21 Characteristics ..........................22 List of Functions..........................25 Field of Application ........................27 Information for Ordering........................ 27 Pin Connection Diagram (Top View) .................... 28 Configuration of Functional Blocks ....................34 1.7.1 Internal Block Diagram .......................
Page 6 2.9.2 List of Control Registers ..................... 96 2.10 Port 4 ............................97 2.10.1 Alternative Functions ......................97 2.10.2 List of Control Registers ..................... 98 2.11 Port 5 ............................99 2.11.1 Alternative Functions ......................99 2.11.2 List of Control Registers ....................100 2.12 Port 8 ............................
Page 7 3.7.2 System Error Notification Function Registers in Detail............. 135 Section 4 Interrupt Functions ..................139 Features............................139 List of Interrupt Sources......................141 Interrupt Controller Control Registers ..................149 4.3.1 ICxx: EI Level Interrupt Control Register ................149 4.3.2 IMRm (m = 0 to 13): EI Level Interrupt Mask Register ............. 156 4.3.3 ISPR –...
Page 8 5.4.1 Characteristics........................200 5.4.2 Setting Registers ......................202 5.4.3 Availability of Writing to Control Registers................ 207 DMAC Control Registers ......................208 5.5.1 DTRC0: DMA Transfer Request Control Register 0............208 5.5.2 DTRSn (n = 0 to 7): DMA Transfer Request Select Register ........... 209 5.5.3 DSAnL (n = 0 to 7): DMA Source Address Register L............
Page 9 Handling of Pins.......................... 246 6.4.1 Power Supply ........................246 6.4.2 Pins........................... 246 6.4.3 Reset Pin .......................... 246 6.4.4 FLMD0 Pin........................247 6.4.5 Port Pins ........................... 247 Option-Setting Bytes........................248 6.5.1 OPBT0 - Option Byte Verification Register............... 249 Product Identification ........................250 Setting the FLMD Pin........................
Page 10 8.3.1 Overview of Reset Controller Registers ................293 8.3.2 Details of Reset Controller Registers ................294 8.3.3 Details of Software Reset Control Registers ..............298 8.3.4 Details of Protection Command Registers................ 299 Power-on Flag/Low Voltage Indicator (POF/LVI)................ 300 8.4.1 Overview of the POF/LVI Function ................... 300 8.4.2 Operation..........................
Page 11 10.4.1 Overview of SGA Registers....................359 10.4.2 SGA Registers Details...................... 360 Section 11 Data CRC Function A (DCRA)..............378 11.1 DCRA Features .......................... 378 11.2 Functional Overview ........................379 11.3 Functional Description ........................ 381 11.4 Registers............................. 382 11.4.1 DCRA Registers Overview ....................382 11.4.2 DCRA Registers Details ....................
Page 12 13.8.3 Channel Output Modes Controlled Synchronously by TAUBn Signals ......425 13.9 Start Timing in Each Operating Modes..................427 13.9.1 Interval Timer Mode, Judge Mode, Capture Mode, and Up/Down Count Mode....427 13.9.2 Event Mode ........................428 13.9.3 Other Operating Modes ....................428 13.10 TAUBnTTOUTm Output and INTTAUBnIm Generation when Counter Starts or Restarts (TAUBnMD0 bit) ......................
Page 13 Section 14 Timer Array Unit J (TAUJ)................619 14.1 Features of TAUJ........................619 14.2 Functional Overview ........................621 14.2.1 Terms ..........................623 14.3 Functional Description ........................ 624 14.3.1 Timer Operation Functions ....................625 14.4 General Operating Procedure..................... 626 14.5 Operating Modes ........................627 14.6 Concepts of Synchronous Channel Operation ................
Page 14 15.1 Functions of TSG2n........................718 15.2 Functional Overview ........................720 15.3 Configuration ..........................721 15.4 Registers............................. 722 15.4.1 TSG2n Registers Overview ....................722 15.4.2 TSG2n Register Details....................724 15.5 Basic Operation .......................... 773 15.5.1 Basic Operation of 16-Bit Counter..................773 15.5.2 Functions of Compare Registers ..................
Page 15 16.3 Configuration ..........................911 16.4 Registers............................. 912 16.4.1 TPBAn Registers Overview ....................912 16.4.2 TPBAn Registers Details ....................913 16.5 Basic Operation .......................... 926 16.5.1 Basic Operation of Counter ....................926 16.5.2 Compare Register Rewrite Operation ................927 16.5.3 Duty Rewrite Operation ....................930 16.5.4 Basic Operation Example ....................
Page 16 19.2.1 Block Diagram ........................ 1021 19.2.2 Peak and Valley of Timer Counter, and Peak and Valley Interrupts ......1022 19.3 Registers........................... 1023 19.3.1 Registers Overview ......................1023 19.3.2 Registers Details ......................1024 19.4 Basic Functions ........................1030 19.4.1 Hi-Z Control Functions....................1030 19.4.2 Asynchronous Hi-Z Control for Pin Inputs ..............
Page 17 20.9.2 FCN Stop Mode......................1121 20.9.3 Example of Using Power Save Modes ................1122 20.10 Interrupt Function........................1123 20.11 Diagnosis Functions and Special Operating Modes ..............1124 20.11.1 Receive-only Mode......................1124 20.11.2 Single-shot Mode......................1125 20.11.3 Self-test Mode ........................ 1126 20.11.4 Receive/Transmit Operations in Each Operating Mode ..........
Page 18 22.5.2 Reception Interrupt Request URTHnTIR................ 1243 22.5.3 Status Interrupt Request URTHnTIS ................1243 22.6 Operation ..........................1244 22.6.1 Data Formats........................1244 22.6.2 Clock Synchronous Mode....................1247 22.6.3 Handshake Mode ......................1248 22.6.4 Consecutive Two-Frame Transfer Mode ................ 1250 22.6.5 Extension bit Detection/ID Compare-Match Detection ........... 1252 22.6.6 BF Transmission/Reception Format ................
Page 19 23.4.5 A/D Conversion Result Registers ................... 1329 23.4.6 A/D Conversion Result Upper/Lower Limit Comparison Registers ........ 1337 23.4.7 Diagnosis Function Control Registers ................1341 23.4.8 Channel Sample and Hold Function Setting Register ............ 1344 23.5 Usage Notes ..........................1345 23.5.1 Range of Channel Input Voltage ..................
Page 20 27.6 AC Characteristics ........................1502 27.6.1 Measurement Conditions....................1502 27.6.2 Clock Timing (CLKOUT)....................1503 27.6.3 Timing in Turning the Power Supply On and Off ............1504 27.6.4 Regulator Characteristics ....................1506 27.6.5 Reset Timing ........................1507 27.6.6 Interrupt Timing ......................1508 27.6.7 ESOn Timing ........................
Page 21 Jul 17, 2014 Section 1 Introduction V850E2/PG4-L(µPD70F4154, µPD70F4155) is a product in the V850 Series of single-chip microcomputers from Renesas Electronics. This section gives an overview of the V850E2/PG4-L. 1.1 Overview This 32-bit single-chip microcomputer is a best fit for applying high-speed...
Page 22 V850E2/PG4-L Section 1 Introduction 1.2 Characteristics CPU core V850E2M: 2 units (with lockstep operation) One CPU core for normal operation (master CPU), and one CPU core to monitor the first for normal operation (checker CPU) Number of Normal instructions: 98 instructions Debug instructions: 3 Minimum...
Page 23 V850E2/PG4-L Section 1 Introduction DMA controller 8-channel configuration Transfer unit: 8, 16, 32, or 128 bits Maximum number of transfers: 32768(2 Transfer type: 2-cycle transfer (dual-address transfer) Transfer mode: single transfer/single step transfer Target to transfer: peripheral I/O peripheral I/O, RAM peripheral I/O, RAM RAM, peripheral I/O flash, RAM flash, peripheral I/O D- flash, RAM D- flash Transfer requests: peripheral I/O and software...
Page 24 V850E2/PG4-L Section 1 Introduction Internal connecting Peripheral Interconnection (PIC): 1 unit function Interlocking operations (simultaneous starting and so on) are obtainable through connection to timers and peripheral I/O Forcibly stopping Timer option unit (TAPA): 2 units output Unit for controlling the Hi-Z state of pins for the TAUB and TSG2 timer Generating clock Frequency multiplication by PLL clock synthesizer signals...
Page 25 V850E2/PG4-L Section 1 Introduction 1.3 List of Functions Series Name V850E2/PG4-L PD70F4154 PD70F4155 Product On-chip memory Code flash 384 Kbytes 384 Kbytes Data flash 16 Kbytes 16 Kbytes 24 Kbytes 24 Kbytes Operating Ta: 125C (max.) 80 MHz (max.) 80 MHz (max.) frequency Oscillation frequency 16 MHz...
Page 26 V850E2/PG4-L Section 1 Introduction Series Name V850E2/PG4-L PD70F4154 PD70F4155 Product Power-supply For internal use 3.0 V to 5.5 V 3.0 V to 5.5 V voltages Internal Included Included regulator For interfaces 3.0 V to 5.5 V 3.0 V to 5.5 V For A/D converter 4.2 V - 5.5 V 4.2 V - 5.5 V...
Page 27 For details on the quality standards and fields of application, refer to the following document issued by Renesas: NEC Semiconductor Device Quality Standards (document reference number: C11531J). The former company name remains in the document but it is still a valid Renesas document. R01UH0336EJ0102 Rev.1.02 Page 27 of 1538...
Page 28 V850E2/PG4-L Section 1 Introduction 1.6 Pin Connection Diagram (Top View) PD70F4154, PD70F4155 AVDD0 AVSS0 AVREF0P AVREF0M ADCA0I7 ADCA0I8 ADCA0I9 ADCA0I10 ADCA0I11 ADCA0I12 ADCA0I13 ADCA0I14 ADCA0I15 ADCA0I16 ADCA0I17 ADCA0I18 P5_0/URTH0RXD/INTP0 P5_1/URTH0TXD/ADCA0TRG0/INTP3 P5_2/INTP2/URTH0SC/ADCA0TRG1/INTP4 P5_3/ADCA0TRG0/INTP3/URTH0CTS/ADCA0TRG2/INTP5 EVDD EVSS ERROROUT P1_0/NMI/CLKOUT/OSTM1O/TSG20O7 R01UH0336EJ0102 Rev.1.02 Page 28 of 1538 Jul 17, 2014...
Page 29 V850E2/PG4-L Section 1 Introduction Table 1-1 List of Pin Numbers and Names (1/3) Number Pin Name P0_0/ADCA0TRG2/INTP5/URTH0RXD/INTP0 P0_1/ADCA0TRG1/INTP4/URTH0TXD P0_2/ADCA0TRG0/INTP3/URTH0SC P0_3/CLKOUT/URTH0CTS REGC0 REGC1 OSCVSS OSCVDD DCUEVTO/RESETOUT DCUTDO/JP0_1/FPDT DCUTRDY/RESETOUT/JP0_5 DCUTCK/JP0_2/FPCK DCUTMS/JP0_3 DCUTDI/FPDR/LPDIO DCUTRST RESET EVSS EVDD P1_0/NMI/CLKOUT/OSTM1O/TSG20O7 P1_1/TAUJ0I0/TAUJ0O0/TSG20O1 P1_2/TAUJ0I1/TAUJ0O1/TSG20O2 P1_3/TAUJ0I2/TAUJ0O2/TSG20O3 P1_4/TAUJ0I3/TAUJ0O3/TSG20O4 P1_5/TSG20O5 P1_6/TSG20O6 P1_7/CSIG0SI/URTH0RXD/INTP0/TSG20O7 P1_8/TPB0O/CSIG0SO/URTH0TXD...
Page 30 V850E2/PG4-L Section 1 Introduction Table 1-1 List of Pin Numbers and Names (2/3) Number Pin Name P2_1/TAUB0I3/TAUB0O3/TAUB0I2/TAUB0O2/CSIG1RYI P2_2/TAUB0I5/TAUB0O5/TAUB0I4/TAUB0O4/TAUB0O10 P2_3/TAUB0I7/TAUB0O7/TAUB0I6/TAUB0O6/TAUB0O12 P2_4/TAUB0I9/TAUB0O9/TAUB0I8/TAUB0O8/TAUB0O14 P2_5/TAUB0I11/TAUB0O11/TAUB0I10/TAUB0O10 P2_6/TAUB0I13/TAUB0O13/TAUB0I12/TAUB0O12 P2_7/TAUB0I15/TAUB0O15/TAUB0I14/TAUB0O14 P3_0/URTH1RXD/INTP1 P3_1/URTH1TXD P3_2/CSIG1SI P3_3/CSIG1SO/TPB0O P3_4/CSIG1SC P3_5/INTP2/FCN1TX P3_6/FCN1RX P4_0/URTH1RXD/INTP1/FCN0TX P4_1/URTH1TXD/TSG20PTSI0/ENCA0E0/FCN0RX P8_0/TAUB0O15/OSTM1O/TGLOUT FLMD1 FLMD0 EVSS EVDD EVDD EVSS P4_2/CSIG1SI/TSG20PTSI1/ENCA0E1/OSTM1O P4_3/CSIG1SO/TSG20PTSI2/ENCA0EC/OSTM0O/URTH1CTS P4_4/CSIG1SC/URTH1RTS/ESO0/INTP6/CSIG0RYO P4_5/ADCA0CNV2/INTP7/CSIG1RYO...
Page 31 V850E2/PG4-L Section 1 Introduction Table 1-1 List of Pin Numbers and Names (3/3) Number Pin Name AVSS0 AVREF0P AVREF0M ADCA0I7 ADCA0I8 ADCA0I9 ADCA0I10 ADCA0I11 ADCA0I12 ADCA0I13 ADCA0I14 ADCA0I15 ADCA0I16 ADCA0I17 ADCA0I18 P5_0/URTH0RXD/INTP0 P5_1/URTH0TXD/ADCA0TRG0/INTP3 P5_2/INTP2/URTH0SC/ADCA0TRG1/INTP4 P5_3/ADCA0TRG0/INTP3/URTH0CTS/ADCA0TRG2/INTP5 EVDD EVSS ERROROUT R01UH0336EJ0102 Rev.1.02 Page 31 of 1538 Jul 17, 2014...
Page 32 V850E2/PG4-L Section 1 Introduction Pin Name ADCA0I1 - ADCA0I18 : Analog input ADCA0TRG0 - : ADC trigger input ADCA0TRG2 : ADC status output ADCA0CNV0 - ADCA0CNV2 AVDD0 : Analog power supply AVREF0P : Analog reference voltage (positive) AVREF0M : Analog reference voltage (minimal) AVSS0 : Analog ground CLKOUT...
Page 33 V850E2/PG4-L Section 1 Introduction JP0_1 - JP0_3, : PortJP0 (JTAG) JP0_5 LPDIO : 1pin debug Input/Output : Non-maskable interrupt input OSTM0O, OSTM1O : Operation system timer output OSCVDD : OSC power supply OSCVSS : OSC ground P0_0 - P0_3 : Port 0 P1_0 - P1_9 : Port 1 P2_0 - P2_7...
Page 34 V850E2/PG4-L Section 1 Introduction 1.7 Configuration of Functional Blocks 1.7.1 Internal Block Diagram R01UH0336EJ0102 Rev.1.02 Page 34 of 1538 Jul 17, 2014...
Page 35 V850E2/PG4-L Section 1 Introduction 1.7.2 Internal Units Processing of almost all instructions is executed in a single clock cycle under 7-stage pipeline control. The CPU includes a multiplier (16 bits × 16 bits  32 bits, or 32 bits × 32 bits ...
Page 36 V850E2/PG4-L Section 1 Introduction Clock Generation An external oscillator is connected to the X1 and X2 pins as an input clock. The signal from the oscillator is input to the PLL1 synthesizer for frequency multiplying (the multiple is switched by optional bytes). The PLL1 output is supplied as the internal system clock and the frequency-divided clock is supplied as the peripheral clock.
Page 37 V850E2/PG4-L Section 1 Introduction (16) Ports Port pins capable of operation as general-purpose port pins and as control pins are listed below. Port Control Function Port 0 Bitwise I/O Serial interface (UARTH0) I/O External interrupt (INTP0, INTP3 to INTP5) input A/D converter (ADCA0) input Baud rate generator (BRG0 (CLKOUT)) output Port 1...
Page 38 V850E2/PG4-L Section 2 Port Functions Section 2 Port Functions This section contains a generic description of the port control functions. 2.1 Port Functions Port groups This product has the following numbers of port groups. Table 2-1 Port Groups Port Groups Product name µPD70F4154 µPD70F4155...
Page 39 V850E2/PG4-L Section 2 Port Functions 2.2 Overview The microcontroller has various pins for input/output functions, known as ports. The ports are organized in port groups. The microcontroller also has several control registers to allocate non-general purpose input/output functions to the pins. For a description of the terms pin, port, and port group, see Section 2.2.1, Terms.
Page 40 V850E2/PG4-L Section 2 Port Functions 2.2.2 Pin Function Configuration The pins can operate in three different general modes. • Port mode (PMCn.PMCn_m = 0) In port mode, the pin operates as a general purpose I/O port. PMn.PMn_m selects input or output. •...
Page 41 V850E2/PG4-L Section 2 Port Functions Table 2-4 Alternative Mode Selection Overview (PMCn.PMCn_m = 1) Register Function PIPC* PFCE Alternative output mode 1 (ALT-OUT1) Alternative input mode 1 (ALT-IN1) Alternative output mode 2 (ALT-OUT2) Alternative input mode 2 (ALT-IN2) Alternative output mode 3 (ALT-OUT3) Alternative input mode 3 (ALT-IN3)
Page 42 V850E2/PG4-L Section 2 Port Functions Table 2-5 Pins on which a Single Control Mode and Multiple Alternate Functions are Multiplexed Alternative Function Pin Port Pin Control Mode ADCA0TRG0/INTP3 P0_2 ALT-IN1 P5_1 ALT-IN4 P5_3 ALT-IN2 ADCA0TRG1/INTP4 P0_1 ALT-IN1 P5_2 ALT-IN4 ADCA0TRG2/INTP5 P0_0 ALT-IN1 P5_3...
Page 43 V850E2/PG4-L Section 2 Port Functions 2.2.3 Pin Data Input/Output The registers used for data input and output are described below. The sources of the data for output and of data read via the PPRn register will differ with the pin mode. Output data In port mode (PMCn.PMCn_m = 0), the data of Pn.Pn_m is output to pin Pn_m.
Page 44 V850E2/PG4-L Section 2 Port Functions • PMCn.PMCn_m This bit selects port mode (PMCn_m = 0) or alternative mode (PMCn_m = 1). • PMn.PMn_m This bit selects input (PMn_m = 1) or output (PMn_m = 0) in port mode (PMCn_m = 0) and software I/O control alternative function mode (PMCn_m = 1, PIPCn_m = 0).
Page 45 V850E2/PG4-L Section 2 Port Functions 2.2.4 Port Control Logic Diagram The following figure shows the logic diagram of the port control function. Caution This figure shows the logics for reference; not show the actual circuits. Enable PUn_m PBDCn_m PMn_m PMSRn_m Enable PIBCn_m PMCn_m...
Page 46 V850E2/PG4-L Section 2 Port Functions 2.3 Port Group Configuration Registers This section starts with an overview of all configuration registers, and then presents all registers in detail. The configuration registers are grouped as follows: • 2.3.2 Pin Function Configuration Registers •...
Page 47 V850E2/PG4-L Section 2 Port Functions Table 2-8 JTAG Port Group Configuration Registers Register Name Shortcut Address JTAG port register FF44 0000 JTAG port set reset register JPSR0 FF44 0010 JTAG port pin read register JPPR0 FF44 0020 JTAG port mode register JPM0 FF44 0030 JTAG port NOT register...
Page 48 V850E2/PG4-L Section 2 Port Functions 2.3.2 Pin Function Configuration Registers PMCn – Port Mode Control Register This register specifies whether the individual pins of port group n are in port mode or in alternative mode (n = 0 to 5, 8). Access Readable and writable in 16-bit units.
Page 49 V850E2/PG4-L Section 2 Port Functions PMCSRn – Port Mode Control Set Reset Register n This register provides an alternative method to write data to the PMCn register. The upper 16 bits specify whether the value PMCn.PMCn_m is set by a write operation to PMCn.PMCn_m or is defined by the lower 16 bits of PMCSRn (n = 0 to 5, 8).
Page 50 V850E2/PG4-L Section 2 Port Functions PIPCn – Port IP Control Register This register specifies whether the I/O direction of pin Pn_m is controlled by the port mode register PMn.PMn_m or by an alternative function. If pin Pn_m is operated in alternative mode (PMCn.PMCn_m = 1) and the alternative function requires to directly control the I/O direction of Pn_m, PIPCn.PIPCn_m must be set to 1 as well.
Page 51 V850E2/PG4-L Section 2 Port Functions PMn – Port Mode Register The PMn register specifies whether the individual pins of the port group n are in input mode or in output mode (n = 0 to 5, 8). Access Readable and writable in 16-bit units. Address Refer to Table 2-7, Port Group Configuration Registers.
Page 52 V850E2/PG4-L Section 2 Port Functions PMSRn – Port Mode Set Reset Register n This register provides an alternative method to write data to the PMn register. The upper 16 bits specify whether the value PMn.PMn_m is set by a write operation to PMn.PMn_m or is defined by the lower 16 bits of PMSRn (n = 0 to 5, 8).
Page 53 V850E2/PG4-L Section 2 Port Functions PIBCn – Port Input Buffer Control Register In input port mode (PMCn.PMCn_m = 0 and PMn.PMn_m = 1), this register enables/disables the port pin's input buffer (n = 0 to 5, 8). Access Readable and writable in 16-bit units. Address Refer to Table 2-7, Port Group Configuration Registers.
Page 54 V850E2/PG4-L Section 2 Port Functions PFCn – Port Function Control Register This register, together with register PFCEn, specifies an alternative function of the pins. Some alternative functions require direct I/O control of pin Pn_m. For such alternative functions PIPCn.PIPCn_m must be set to 1 as well. For other alternative functions, input/output must be specified by PMn.PMn_m (n = 0 to 5, 8).
Page 55 V850E2/PG4-L Section 2 Port Functions 2.3.3 Pin Data Input/Output Registers PBDCn – Port Bi-Direction Control Register This register enables the input buffer, thus the Pn_m pin level is always read via PPRn.PPRn_m (n = 0 to 5, 8). Access Readable and writable in 16-bit units. Address Refer to Table 2-7, Port Group Configuration Registers Initial value...
Page 56 V850E2/PG4-L Section 2 Port Functions PPRn – Port Pin Read Register This register reflects the actual level of pin Pn_m, the value of the Pn.Pn_m bit or the level of an alternative output function. The value which is read depends on various control settings as described in Table 2-6, PPRn_m Read Values (n = 0 to 5, 8).
Page 57 V850E2/PG4-L Section 2 Port Functions PNOTn – Port NOT Register This register allows to invert a bit Pn_m of the port register Pn without directly writing to Pn (n = 0 to 5, 8). Access Writing in 16-bit units is the only form of access. The register is always read as 0000 Address Refer to Table 2-7, Port Group Configuration Registers.
Page 58 V850E2/PG4-L Section 2 Port Functions PSRn – Port Set Reset Register This register provides an alternative method to write data to the Pn register. The upper 16 bits specify whether the value Pn.Pn_m is set by a write operation to Pn.Pn_m or is defined by the lower 16 bits of PSRn (n = 0 to 5, 8). Access Readable and writable in 32-bit units.
Page 59 V850E2/PG4-L Section 2 Port Functions 2.3.4 Configuration of Electrical Characteristics Registers PUn – Pull-Up Option Register This register specifies whether pull-up resistor is connected to an input pin (n = 0 to 5, 8). Access Readable and writable in 16-bit units. Address Refer to Table 2-7, Port Group Configuration Registers.
Page 60 V850E2/PG4-L Section 2 Port Functions PODCn – Port Open Drain Control Register This register selects push-pull or open-drain as output buffer function (n = 2). For correspondence with the SPC function of the SENT interface in this product, this setting is only available for the TAUB0 pin of port 2. Access Readable and writable in 32-bit units.
Page 61 V850E2/PG4-L Section 2 Port Functions 2.3.5 Port Register Protection PPCMDn – Port Register Protection Command Register This register is a command register for (n = 2). Access Writable in 8-bit units. When read, it is always read as 0. Address Refer to Table 2-7, Port Group Configuration Registers.
Page 62 V850E2/PG4-L Section 2 Port Functions Protected Port Registers PODCn - Port Open Drain Control Register Sequence for Writing to a Protected Port Register Start Step 1 Step 2 Step 3 Step 4 Step 5 Figure 2-1 Sequence for Writing to a Protected Port Register Step 1 Initialize the sequence of writing by writing A5 to register PPCMD.
Page 63 V850E2/PG4-L Section 2 Port Functions 2.4 Port Group Configuration This section shows an overview of the port groups. See Table 2-26, List of Port Groups. Table 2-30, List of States of Port Pins, shows the changes in pin function when this microcontroller is reset, or is at each stand-by mode.
Page 64 V850E2/PG4-L Section 2 Port Functions 2.4.1 List of Ports and Pins List of Port Groups Table 2-26 List of Port Groups (1/2) Port Group Port Alternative Alternative Alternative Alternative Name Name Mode 1 Mode 2 Mode 3 Mode 4 Characteristics P0_0 ADCA0TRG2/ —...
Page 65 V850E2/PG4-L Section 2 Port Functions Table 2-26 List of Port Groups (2/2) Port Group Port Alternative Alternative Alternative Alternative Name Name Mode 1 Mode 2 Mode 3 Mode 4 Characteristics P3_0 — — URTH1RXD/ — • Input/output port INTP1 • Inputs and outputs are specifiable in 1-bit units.
Page 66 V850E2/PG4-L Section 2 Port Functions List of Pins Other than Port Pins Table 2-27 List of Pins Other than Port Pins (1/6) Pin Name Function INTC Input for non-maskable external interrupt requests INTP0 Input for maskable external interrupt requests INTP1 INTP2 INTP3 INTP4...
Page 67 V850E2/PG4-L Section 2 Port Functions Table 2-27 List of Pins Other than Port Pins (2/6) Pin Name Function TAUB0 TAUB0I0 Input for the TAUB0 channel TAUB0I1 TAUB0I2 TAUB0I3 TAUB0I4 TAUB0I5 TAUB0I6 TAUB0I7 TAUB0I8 TAUB0I9 TAUB0I10 TAUB0I11 TAUB0I12 TAUB0I13 TAUB0I14 TAUB0I15 TAUB0O0 Output for the TAUB0 channel TAUB0O1...
Page 68 V850E2/PG4-L Section 2 Port Functions Table 2-27 List of Pins Other than Port Pins (3/6) Pin Name Function TAUJ0 TAUJ0I0 Input for the TAUJ0 channel TAUJ0I1 TAUJ0I2 TAUJ0I3 TAUJ0O0 Output for the TAUJ0 channel TAUJ0O1 TAUJ0O2 TAUJ0O3 TSG20 TSG20O1 Pulse output for the TSG20 TSG20O2 TSG20O3 TSG20O4...
Page 69 V850E2/PG4-L Section 2 Port Functions Table 2-27 List of Pins Other than Port Pins (4/6) Pin Name Function UARTH1 URTH1TXD Output for serial data transmission from UART1 URTH1RXD Input for serial data reception by UART1 URTH1CTS Input for hand-shake signal in UART1 transmission URTH1RTS Output for hand-shake signal in UART1 reception URTH1SC...
Page 70 V850E2/PG4-L Section 2 Port Functions Table 2-27 List of Pins Other than Port Pins (5/6) Pin Name Function ADCA0 ADCA0I1 Analog inputs for the A/D converter ADCA0I2 ADCA0I3 ADCA0I4 ADCA0I5 ADCA0I6 ADCA0I7 ADCA0I8 ADCA0I9 ADCA0I10 ADCA0I11 ADCA0I12 ADCA0I13 ADCA0I14 ADCA0I15 ADCA0I16 ADCA0I17 ADCA0I18...
Page 71 V850E2/PG4-L Section 2 Port Functions Table 2-27 List of Pins Other than Port Pins (6/6) Pin Name Function Other DCUEVTO Output for event-trigger signal debugger RESETOUT, Output for debugger reset RESETOUT LPDIO Single-pin debugging input/output pin RESET RESET Input for system reset CLOCK For connection of crystal for system clock oscillation MODE...
Page 72 V850E2/PG4-L Section 2 Port Functions Handling of Unused Port Pins Table 2-28 Handling of Unused Port Pins (1/3) Port Group Port Alternative Alternative Alternative Alternative Input/Output Handling of Name Name Mode 1 Mode 2 Mode 3 Mode 4 Circuit Type Unused Pins P0_0 ADCA0TRG2/...
Page 73 V850E2/PG4-L Section 2 Port Functions Table 2-28 Handling of Unused Port Pins (2/3) Port Group Port Alternative Alternative Alternative Alternative Input/Output Handling of Name Name Mode 1 Mode 2 Mode 3 Mode 4 Circuit Type Unused Pins P3_0 — — URTH1RXD/ —...
Page 74 V850E2/PG4-L Section 2 Port Functions Table 2-28 Handling of Unused Port Pins (3/3) Port Group Port Alternative Alternative Alternative Alternative Input/Output Handling of Name Name Mode 1 Mode 2 Mode 3 Mode 4 Circuit Type Unused Pins JP0* JP0_1 Type TDO In input mode: Set the pins as inputs JP0_2...
Page 75 V850E2/PG4-L Section 2 Port Functions Handling of Unused Pins Other than Port Pins Table 2-29 Handling of Unused Pins Other than Port Pins (1/2) Input/Output Pin Name Circuit Type Handling FLMD0 Type2-W Must be used. Connect this pin to EVSS via a resistance no less than 270 kΩ FLMD1 Type2-I Must be used.
Page 76 V850E2/PG4-L Section 2 Port Functions Table 2-29 Handling of Unused Pins Other than Port Pins (2/2) Input/Output Pin Name Circuit Type Handling — Must be used. — OSCVDD — OSCVSS — EVDD — EVSS — REGC0 — REGC1 — Note 1. It is alternative with JTAG ports. When OPBT0.FOP31=0, JTAG ports are enabled. When OPBT0.FOP31=1, Nexus interface is enabled.
Page 77 V850E2/PG4-L Section 2 Port Functions Type 3 Type 7 P-ch P-ch Comparator N-ch Data N-ch VREF (threshold voltage) Type 2-1 Type 2-X TTL input Schmitt-triggered input with hysteresis characteristics Type 5-W Type 2-W Pull-up Pull-up P-ch P-ch enable enable Pull-down Data N-ch enable...
Page 78 V850E2/PG4-L Section 2 Port Functions Type TDO, RDY Type TCK, TMS Pull-up Pull-up enable P-ch enable Data Data P-ch IN/OUT IN/OUT Output disable Output N-ch disable Data Data input enable TTL input Control signal Input enable Control input enable Type ERROROUT Type LPDIO Data data...
Page 79 V850E2/PG4-L Section 2 Port Functions States of Port Pins Table 2-30 List of States of Port Pins (1/2) Immedi- ately after BIST for Releasing Self- the CPU Port diagnosis Core Group Alter-native Alter-native Alter-native Alter-native from Name Name Mode 1 Mode 2 Mode 3 Mode 4...
Page 80 V850E2/PG4-L Section 2 Port Functions Table 2-30 List of States of Port Pins (2/2) Immedi- ately after BIST for Releasing Self- the CPU Port diagnosis Core Group Alter-native Alter-native Alter-native Alter-native from Name Name Mode 1 Mode 2 Mode 3 Mode 4 Reset Running...
Page 81 V850E2/PG4-L Section 2 Port Functions States of Pins Other than Port Pins Table 2-31 List of States of Pins Other than Port Pins (1/2) Immediately after BIST for Self- Releasing the diagnosis is CPU Core Pin Name Reset Running from Reset Halt Mode FLMD0 —...
Page 82 V850E2/PG4-L Section 2 Port Functions Table 2-31 List of States of Pins Other than Port Pins (2/2) Immediately after BIST for Self- Releasing the diagnosis is CPU Core Pin Name Reset Running from Reset Halt Mode ADCA0I1 — — Operable Operable ADCA0I2 ADCA0I3...
Page 83 V850E2/PG4-L Section 2 Port Functions Pin States under Specified Conditions 1. Port pins are in the Hi-Z state during an external reset in on-chip debugging mode. Self-diagnosis BIST is not executed after release from an external reset in on-chip debugging mode. 2.
Page 84 V850E2/PG4-L Section 2 Port Functions 2.5 Functions of Pull-Up and Pull-Down Resistors This section describes target pins for pull-up and pull-down resistors. 2.5.1 Details of Pull-Up and Pull-Down Resistors Pull-Up and Pull-Down Resistors for Port Pins Table 2-32 List of Pull-Up and Pull-Down Resistors for Port Pins (1/3) Port Group Port...
Page 85 V850E2/PG4-L Section 2 Port Functions Table 2-32 List of Pull-Up and Pull-Down Resistors for Port Pins (2/3) Port Group Port Alternative Alternative Alternative Alternative Pull-Up Resistor, Name Name Mode 1 Mode 2 Mode 3 Mode 4 Pull-Down Resistor P2_0 TAUB0I1/ TAUB0I0/ URTH1SC CSIG0RYI...
Page 86 V850E2/PG4-L Section 2 Port Functions Table 2-32 List of Pull-Up and Pull-Down Resistors for Port Pins (3/3) Port Group Port Alternative Alternative Alternative Alternative Pull-Up Resistor, Name Name Mode 1 Mode 2 Mode 3 Mode 4 Pull-Down Resistor P5_0 — —...
Page 87 V850E2/PG4-L Section 2 Port Functions Pull-Up and Pull-Down Resistors for Pins Other than Port Pins Table 2-33 List of Pull-Up and Pull-Down Resistors for Pins Other than Port Pins (1/2) Pin Name Pull-Up Resistor, Pull Down Resistor Software pull-up/pull-down FLMD0 (initial value: pull-down on) Always pull-down FLMD1...
Page 88 V850E2/PG4-L Section 2 Port Functions Table 2-33 List of Pull-Up and Pull-Down Resistors for Pins Other than Port Pins (2/2) Pin Name Pull-Up Resistor, Pull Down Resistor ADCA0I1 Software pull-down (initial value: off) ADCA0I2 ADCA0I3 ADCA0I4 ADCA0I5 ADCA0I6 ADCA0I7 ADCA0I8 ADCA0I9 ADCA0I10 ADCA0I11...
Page 89 V850E2/PG4-L Section 2 Port Functions 2.6 Port 0 This section describes alternative functions and control registers of port 0. 2.6.1 Alternative Functions Alternative Functions of Port 0 Table 2-34 List of Alternative Functions of Port 0 Control Mode (PMC = 1) Alternative Mode 1 Alternative Mode 2 Alternative Mode 3...
Page 90 V850E2/PG4-L Section 2 Port Functions 2.6.2 List of Control Registers Port 0 Control Registers Table 2-35 List of Port 0 Control Registers Number of Bits Name ― √ ― ― ― ― ― ― ― ― ― ― ― ― ―...
Page 91 V850E2/PG4-L Section 2 Port Functions 2.7 Port 1 This section describes alternative functions and control registers of port 1. 2.7.1 Alternative Functions Alternative Functions of Port 1 Table 2-36 List of Alternative Functions of Port 1 Control Mode (PMC = 1) Alternative Mode 1 Alternative Mode 2 Alternative Mode 3...
Page 92 V850E2/PG4-L Section 2 Port Functions 2.7.2 List of Control Registers Port 1 Control Registers Table 2-37 List of Port 1 Control Registers Number of Bits Name ― √ ― ― ― ― ― ― ― √ √ √ √ √ √...
Page 93 V850E2/PG4-L Section 2 Port Functions 2.8 Port 2 This section describes alternative functions and control registers of port 2. 2.8.1 Alternative Functions Alternative Functions of Port 2 Table 2-38 List of Alternative Functions of Port 2 Control Mode (PMC = 1) Alternative Mode 1 Alternative Mode 2 Alternative Mode 3...
Page 94 V850E2/PG4-L Section 2 Port Functions 2.8.2 List of Control Registers Port 2 Control Register Table 2-39 List of Port 2 Control Registers Number of Bits Name ― √ ― ― ― ― ― ― ― ― ― √ √ √ √...
Page 95 V850E2/PG4-L Section 2 Port Functions 2.9 Port 3 This section describes alternative functions and control registers of port 3. 2.9.1 Alternative Functions Port 3 Control Registers Table 2-40 List of Alternative Functions of Port 3 Control Mode (PMC = 1) Alternative Mode 1 Alternative Mode 2 Alternative Mode 3...
Page 96 V850E2/PG4-L Section 2 Port Functions 2.9.2 List of Control Registers List of Port 3 Control Registers Table 2-41 List of Port 3 Control Registers Number of Bits Name ― √ ― ― ― ― ― ― ― ― ― ― √...
Page 97 V850E2/PG4-L Section 2 Port Functions 2.10 Port 4 This section describes alternative functions and control registers of port 4. 2.10.1 Alternative Functions Alternative Functions of Port 4 Table 2-42 List of Alternative Functions of Port 4 Control Mode (PMC = 1) Alternative Mode 1 Alternative Mode 2 Alternative Mode 3...
Page 98 V850E2/PG4-L Section 2 Port Functions 2.10.2 List of Control Registers Port 4 Control Registers Table 2-43 List of Port 4 Control Registers Number of Bits Name ― √ ― ― ― ― ― ― ― ― ― √ √ √ √...
Page 99 V850E2/PG4-L Section 2 Port Functions 2.11 Port 5 This section describes alternative functions and control registers of port 5. 2.11.1 Alternative Functions Alternative Functions of Port 5 Table 2-44 List of Alternative Functions of Port 5 Control Mode (PMC = 1) Alternative Mode 1 Alternative Mode 2 Alternative Mode 3...
Page 100 V850E2/PG4-L Section 2 Port Functions 2.11.2 List of Control Registers Port 5 Control Registers Table 2-45 List of Port 5 Control Registers Number of Bits Name ― √ ― ― ― ― ― ― ― ― ― ― ― ― ―...
Page 101 V850E2/PG4-L Section 2 Port Functions 2.12 Port 8 This section describes alternative functions and control registers of port 8. 2.12.1 Alternative Functions Alternative Functions of Port 8 Table 2-46 List of Alternative Functions of Port 8 Control Mode (PMC = 1) Alternative Mode 1 Alternative Mode 2 Alternative Mode 3...
Page 102 V850E2/PG4-L Section 2 Port Functions 2.13 JTAG Port 0 This section describes alternative functions and control registers of JTAG port 2.13.1 Alternative Functions Alternative Functions of JTAG Port 0 The JTAG port 0 has no any alternative function pin. 2.13.2 List of Control Registers JTAG Port 0 Control Registers Table 2-48 List of JTAG Port 0 Control Registers...
Page 103 V850E2/PG4-L Section 2 Port Functions 2.14 Cancelling Noise on Pins This section describes the noise-filtering insertion pin, filter groups, noise- cancellation sampling clock, and control registers. 2.14.1 Details of Noise Cancellation Digital Filter Function The input signal is sampled with the sampling frequency fs. If the input is sampled at the same level in a specified number of successive samples, the signal level is judged as valid and the filter output signal is changed accordingly.
Page 104 V850E2/PG4-L Section 2 Port Functions Noise Filter Insertion Pins and Filter Groups Table 2-49 List of Noise Filter Insertion Pins and Filter Groups (1/2) Port Group Filter Insertion Name Port Pin Filter Group P0_0 INTP0 DNF_INTP-G0 INTP5 DNF_INTP-G1 ADCA0TRG2 ADTRG P0_1 INTP4 DNF_INTP-G1...
Page 105 V850E2/PG4-L Section 2 Port Functions Table 2-49 List of Noise Filter Insertion Pins and Filter Groups (2/2) Port Group Filter Insertion Name Port Pin Filter Group P4_0 INTP1 DNF_INTP-G0 P4_1 TSG20PTSI0/ DNF_TSG20-G0 ENCA0E0 P4_2 TSG20PTSI1/ DNF_TSG20-G0 ENCA0E1 P4_3 TSG20PTSI2/ DNF_TSG20-G1 ENCA0EC P4_4 ESO0...
Page 106 V850E2/PG4-L Section 2 Port Functions Noise Filter Insertion Pins and Filter Groups for Table 2-50 List of Filter Insertion Pins and Filter Groups for Pins Other than Port Pin Name Filter Insertion Pin Filter Group FLMD0 FLMD0 FLMD0 FLMD1 FLMD1 FLMD1 RESET RESET...
Page 107 V850E2/PG4-L Section 2 Port Functions Noise-Cancelling Intervals and Sampling Clock for Noise Cancellation Table 2-51 List of Noise-Cancelling Intervals and Sampling Clock for Noise Cancellation (1/2) Noise-Cancelling Intervals and Sampling Clock for Noise Cancellation Type (Analog or (Clock Selection Filter Group Function Block Target Pin Digital)
Page 108 V850E2/PG4-L Section 2 Port Functions Table 2-51 List of Noise-Cancelling Intervals and Sampling Clock for Noise Cancellation (2/2) Noise-Cancelling Intervals and Sampling Clock for Noise Cancellation Type (Analog or (Clock Selection Filter Group Function Block Target Pin Digital) Group) DNF_TAUJ0-G0 TAUJ0 TAUJ0I0 Digital filter...
Page 109 V850E2/PG4-L Section 2 Port Functions 2.14.2 Control Registers The following registers control and run the digital noise filter. Table 2-53 The List of Registers for the Digital Noise Canceller Register Function Name Address Digital noise canceller control register DNFAnCTL <DNFn_base> + n × 100 Digital noise canceller enable register DNFAnEN <DNFn_base>...
Page 110 V850E2/PG4-L Section 2 Port Functions DNFAnCTL – Digital Noise Canceller Control Register This register is used to select the sampling clock for the digital noise canceller. Access Readable and writable in 8-bit units. Address Refer to Table 2-53, The List of Registers for the Digital Noise Canceller. Initial value DNFAnNFSTS[1:0] DNFAnPRS[2:0]...
Page 111 V850E2/PG4-L Section 2 Port Functions Table 2-55 List of DNFAnCTL registers Register Name/ Address Filter Group Target Pin DNFA0CTL DNF_NMI-G0 FF410000 DNFA1CTL DNF_INTP-G0 INTP0, INTP1, INTP2 FF410100 DNFA2CTL DNF_INTP-G1 INTP3, INTP4, INTP5 FF410200 DNFA3CTL DNF_INTP-G2 INTP6, INTP7, INTP8, FF410300 INTP9 DNFA4CTL DNF_TAUB0-G0 TAUB0I0, TAUB0I1...
Page 112 V850E2/PG4-L Section 2 Port Functions DNFAnEN – Digital Noise Canceller Enable Register This register specifies enabling and disabling of the digital noise cancellers. Access Readable and writable in 16-bit units. Address Refer to Table 2-53, The List of Registers for the Digital Noise Canceller. Initial value 0000 DNFAnNFEN[15:8]...
Page 113 V850E2/PG4-L Section 2 Port Functions Caution 1. When writing to DNFAnEN registers, be sure to write 0 to DNFAnEN.DNAFnENm bits for which “0” is the entry as shown in Table 2-57, List of DNFAnEN Registers. Operation is not guaranteed if any such bit is set to 1.
Page 114 V850E2/PG4-L Section 2 Port Functions Digital Noise Canceller Enable Register L This register is the 8 lower-order bits of DNFAnEN register. Access This register is readable/writable in 8 or 1-bit units. Address Refer to Table 2-53, The List of Registers for the Digital Noise Canceller. Initial value DNFAnNFEN[7:0] For details of each bit operation, see DNFAnEN register.
Page 115 V850E2/PG4-L Section 2 Port Functions Digital Noise Filter Sampling Clock Control Register This register selects the digital noise filter sampling clock. Access Readable and writable in 16-bit units. Address Refer to Table 2-53, The List of Registers for the Digital Noise Canceller. Initial value 0000 DNFSCKSL6[1:0]...
Page 116 V850E2/PG4-L Section 2 Port Functions 2.15 Edge Detection This section the pins and control registers used with edge detection. 2.15.1 Details of Edge Detection Pins for Use in Edge Detection Table 2-59 List of Pins for Use in Edge Detection Target Pin Control Register Name FCLA0CTL0...
Page 117 V850E2/PG4-L Section 2 Port Functions 2.15.2 Control Register FCLAnCTLm-Filter Control Register This register specifies operation of the edge detection function. Access Readable and writable in 8-bit units. Address Refer to Table 2-61, List of FCLAnCTLm Registers. Initial value FCLAn FCLAn INTFm INTRm Table 2-60...
Page 118 V850E2/PG4-L Section 3 CPU System Function Section 3 CPU System Function This section describes the registers of the CPU, the operation modes, the address space and the memory areas. For details on the functions of the CPU, refer to manuals as indicated below. Table 3-1 Descriptions of CPU Functions V850E2M...
Page 119 V850E2/PG4-L Section 3 CPU System Function • Flash and cache: – 8 Kbytes, 2-way associative (4 Kbytes per way) • Interrupt controller (INTC) • DMA controller (DMAC) • Processor protection functions – Memory protection unit (MPU) Protection against illegal execution from or data manipulation of CPU memory areas (up to 5 areas in instruction space, up to 6 areas in data space) –...
Page 120 V850E2/PG4-L Section 3 CPU System Function 3.1.1 Peripheral Protection Unit PPU base address The addresses of the peripheral protection unit registers described in the “V850E2M Architecture Manual (R01US0001E)” are given as offset addresses. The base address is as follows: <PPU_base> = FFFF 5100 PPU areas and The control registers for each protected area comprise 4 registers.
Page 121 V850E2/PG4-L Section 3 CPU System Function Table 3-2 PPU Protected Areas and Modules (2/4) Protection Control Registers Bits Protection PPVn, PPTn, PPVnm, PPTnm, Range PPPn, PPSn PPPnm, PPSnm Size Module Name Address Range 64 KB POF/LVI control FF45 0000 - FF45 FFFF PBUS error/access control FCN, on-chip RAM FF46 0000...
Page 122 V850E2/PG4-L Section 3 CPU System Function Table 3-2 PPU Protected Areas and Modules (3/4) Protection Control Registers Bits Protection PPVn, PPTn, PPVnm, PPTnm, Range PPPn, PPSn PPPnm, PPSnm Size Module Name Address Range 4 KB TSG20 FF82 E000 - FF82 EFFF TPBA0 FF83 2000 - FF83 2FFF...
Page 123 V850E2/PG4-L Section 3 CPU System Function Table 3-2 PPU Protected Areas and Modules (4/4) Protection Control Registers Bits Protection PPVn, PPTn, PPVnm, PPTnm, Range PPPn, PPSn PPPnm, PPSnm Size Module Name Address Range 256 B CSIG0 FFFF E400 - FFFF E4FF CSIG1 FFFF E500 - FFFF E5FF...
Page 124 V850E2/PG4-L Section 3 CPU System Function 3.1.2 Important Reminders Please be aware of the following points regarding functions as described in the V850E2M Architecture Manual (R01US0001E). Branching Instructions and Loading Instructions When a branching instruction and a loading instruction are consecutive in memory, parallel execution of the pipelines means that the loading instruction which immediately follows the branching instruction is executed (but discarded by the CPU) even if the preceding instruction leads to a branch.
Page 125 V850E2/PG4-L Section 3 CPU System Function 3.2 Operation Modes This section describes the operation modes of this product and how the modes are selected. The following operation modes are available: • Normal operation mode • Flash programming mode After reset release by RESET pin, the microcontroller starts to fetch instructions from an internal boot ROM which contains the internal firmware.
Page 126 V850E2/PG4-L Section 3 CPU System Function 3.2.3 HALT Mode Setting and Operation of HALT Mode In normal operation mode, HALT mode is selected by executing a dedicated instruction (the HALT instruction). In HALT mode, pipeline operation of the CPU is stopped but clock signals continue to be supplied to the clock oscillation circuit and other on-chip peripheral modules.
Page 127 V850E2/PG4-L Section 3 CPU System Function 3.3 Address Space This section describes the address space of the CPU (sizes and addresses of the CPU address space and physical address space). The address range of data space and program space together with their wraparound properties are presented.
Page 128 V850E2/PG4-L Section 3 CPU System Function Wrap-Around of Data Space If an operand address calculation exceeds 32 bits, only the lower 32 bits of the result are considered. Therefore, the addresses FFFF FFFF and 0000 0000 are contiguous addresses. This results in a wrap-around of the data space: Data space FFFF FFFE FFFF FFFF...
Page 129 V850E2/PG4-L Section 3 CPU System Function 3.4 Conditions for Boundary Operations 3.4.1 Program Space Branching to the peripheral I/O area or consecutive fetching from the RAM area to peripheral I/O area should not proceed. Such branching or consecutive fetching can lead to the fetching of undefined data. Caution Executing an executable instruction allocated to a location within 48 bytes of the last address of a memory area (code flash or on-chip RAM) may lead to an...
Page 130 V850E2/PG4-L Section 3 CPU System Function 3.5 Memory Mapping This section describes memory maps for the CPU and the address map for DMA. 3.5.1 Memory Map for DMA Access For details, refer to Section 5.3.3, Memory Map for DMA Access. R01UH0336EJ0102 Rev.1.02 Page 130 of 1538 Jul 17, 2014...
Page 131 V850E2/PG4-L Section 3 CPU System Function 3.5.2 Memory Map Memory Map FFFF FFFF PBUS peripheral I/O area (32 Kbytes) FFFF 8000 FFFF 7FFF CPU peripheral Program area I/O area (4 Kbytes) (256 Mbytes) FFFF 7000 0FFF FFFF FFFF 6FFF On-chip peripheral I/O area (4 Kbytes) FFFF 6000 FFFF 5FFF...
Page 132 V850E2/PG4-L Section 3 CPU System Function 3.6 CPU-Related Registers This section describes CPU related registers. 3.6.1 Overview of CPU-Related Registers Table 3-5 List of CPU-Related Registers Register Name Symbol Address Processor element identifier register PEID FFFF 6490 Data flash access wait setting register DCLKWAIT FF43 6000 R01UH0336EJ0102 Rev.1.02...
Page 133 V850E2/PG4-L Section 3 CPU System Function 3.6.2 CPU-Related Registers in Detail PEID - Processor Element Identifier Register The PEID register returns the processor-element identifier of the last accessing CPU. Access Readable in 16 bit-units Address FFFF 6490 Initial value 0001 PEID[15:0] Table 3-6 PEID Register...
Page 134 V850E2/PG4-L Section 3 CPU System Function 3.7 System Error Notification Function This section describes the registers involved in system error notification. 3.7.1 Overview of System Error Notification Registers Table 3-8 List of System Error Notification Function Registers Register Name Symbol Address System error control register SEG_CONT...
Page 135 V850E2/PG4-L Section 3 CPU System Function 3.7.2 System Error Notification Function Registers in Detail SEG_CONT – System Error Control Register (SEG_CONT, SEG_CONTL) This register is used to set up the generation of SYSERR exceptions due to system error sources. Access SEG_CONT is readable/writable in 16-bit units.
Page 136 V850E2/PG4-L Section 3 CPU System Function Table 3-9 SEG_CONT Register Bit Position Bit Name Function SEG_ DMA error notification enable CONT This bit is used to set the behavior when DMA access leads to the following DMAE errors. • Uncorrectable ECC error in access to data in the code-flash area •...
Page 137 V850E2/PG4-L Section 3 CPU System Function SEG_FLAG – System Error Flag Register (SEG_FLAG, SEG_FLAGL) This register is used to store results of the detection of system errors. When a system error is detected, the flag corresponding to the error source is set to 1. Setting flags by directly writing to the register is also possible, providing a way to intentionally generate SYSERR exceptions.
Page 138 V850E2/PG4-L Section 3 CPU System Function Table 3-10 SEG_FLAG Register Bit Position Bit Name Function SEG_ DMA error flag FLAG This flag is set when DMA access leads to the following errors. DMAF • Uncorrectable error generated from flash ROM in response to attempted access to data in the code-flash area •...
Page 139 V850E2/PG4-L Section 4 Interrupt Functions Section 4 Interrupt Functions 4.1 Features An event where a specific event forces branching from a currently running program to a different program is called an exception. This section describes the exception processing functions of this product. Table 4-1 List of Exception Sources Exception...
Page 140 V850E2/PG4-L Section 4 Interrupt Functions The following three exceptions from Table 4-1 are called interrupts, and are thus described in this section. All other exceptions and their handling are described in the V850E2M Architecture Manual (R01US0001E). ○ FE level non-maskable interrupt (FENMI): One source (generating factors: INTCME, INTWDTA0NMI, or INTCLMA1, INTCLMA2) •...
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Page 149 V850E2/PG4-L Section 4 Interrupt Functions 4.3 Interrupt Controller Control Registers Meaning of xx xx denotes the identifying names of the individual peripheral units. 4.3.1 ICxx: EI Level Interrupt Control Register An ICxx register is provided for every EI level-maskable interrupt (EIINT) channel, and is used to configure control conditions.
Page 150 V850E2/PG4-L Section 4 Interrupt Functions Table 4-3 Addresses and Bits of the Interrupt Control Registers (1/6) Register Address ICCMEL FFFF6000 MKCME P3CME P2CME P1CME P0CME ICCMEH FFFF6001 RFCME ICISGL FFFF6002 MKISG P3ISG P2ISG P1ISG P0ISG ICISGH FFFF6003 RFISG ICWDTA0NMIL FFFF6004 MKWDTA0NMI P3WDTA0NMI P2WDTA0NMI...
Page 151 V850E2/PG4-L Section 4 Interrupt Functions Table 4-3 Addresses and Bits of the Interrupt Control Registers (2/6) Register Address ICP8L FFFF6032 MKP8 P3P8 P2P8 P1P8 P0P8 ICP8H FFFF6033 RFP8 ICP9L FFFF6034 MKP9 P3P9 P2P9 P1P9 P0P9 ICP9H FFFF6035 RFP9 ICDMA0L FFFF6038 MKDMA0 P3DMA0 P2DMA0...
Page 152 V850E2/PG4-L Section 4 Interrupt Functions Table 4-3 Addresses and Bits of the Interrupt Control Registers (3/6) Register Address ICTAUJ0I3L FFFF6062 MKTAUJ0I3 P3TAUJ0I3 P2TAUJ0I3 P1TAUJ0I3 P0TAUJ0I3 ICTAUJ0I3H FFFF6063 RFTAUJ0I3 ICTAUB0I0L FFFF606C MKTAUB0I0 P3TAUB0I0 P2TAUB0I0 P1TAUB0I0 P0TAUB0I0 ICTAUB0I0H FFFF606D RFTAUB0I0 ICTAUB0I1L FFFF606E MKTAUB0I1 P3TAUB0I1 P2TAUB0I1...
Page 153 V850E2/PG4-L Section 4 Interrupt Functions Table 4-3 Addresses and Bits of the Interrupt Control Registers (4/6) Register Address ICCSIG0IRL FFFF60C8 MKCSIG0IR P3CSIG0IR P2CSIG0IR P1CSIG0IR P0CSIG0IR ICCSIG0IRH FFFF60C9 RFCSIG0IR ICCSIG0ICL FFFF60CA MKCSIG0IC P3CSIG0IC P2CSIG0IC P1CSIG0IC P0CSIG0IC ICCSIG0ICH FFFF60CB RFCSIG0IC ICCSIG1IREL FFFF60CC MKCSIG1IRE P3CSIG1IRE P2CSIG1IRE...
Page 154 V850E2/PG4-L Section 4 Interrupt Functions Table 4-3 Addresses and Bits of the Interrupt Control Registers (5/6) Register Address ICTSG20I01L FFFF6104 MKTSG20I01 P3TSG20I01 P2TSG20I01 P1TSG20I01 P0TSG20I01 ICTSG20I01H FFFF6105 RFTSG20I01 ICTSG20I02L FFFF6106 MKTSG20I02 P3TSG20I02 P2TSG20I02 P1TSG20I02 P0TSG20I02 ICTSG20I02H FFFF6107 RFTSG20I02 ICTSG20I03L FFFF6108 MKTSG20I03 P3TSG20I03 P2TSG20I03...
Page 155 V850E2/PG4-L Section 4 Interrupt Functions Table 4-3 Addresses and Bits of the Interrupt Control Registers (6/6) Register Address ICTPBA0IPATL FFFF615E MKTPBA0IPAT P3TPBA0IPAT P2TPBA0IPAT P1TPBA0IPAT P0TPBA0IPAT ICTPBA0IPATH FFFF615F RFTPBA0IPAT ICTAPA0IPEK0L FFFF616A MKTAPA0IPEK0 P3TAPA0IPEK0 P2TAPA0IPEK0 P1TAPA0IPEK0 P0TAPA0IPEK0 ICTAPA0IPEK0H FFFF616B RFTAPA0IPEK0 ICTAPA0IVLY0L FFFF616C MKTAPA0IVLY0 P3TAPA0IVLY0 P2TAPA0IVLY0...
Page 156 V850E2/PG4-L Section 4 Interrupt Functions 4.3.2 IMRm (m = 0 to 13): EI Level Interrupt Mask Register These registers are for aggregating the ICxx.MKxx bits. Bits of the IMRm register reflect settings of the corresponding ICxx.MKxx bits. Corresponding ICxx.MKxx bits also reflect the settings of IMRm registers. Caution The IMRm.IMRmEIMKn bits for interrupt sources not listed in Table 4-2 must always be set to 1.
Page 157 V850E2/PG4-L Section 4 Interrupt Functions EI Level Interrupt Mask Register 1 (IMR1) Access Readable/writable in 1-, 8-, or 16-bit units. All of the corresponding IMR1EIMK [31:16] bits are updated simultaneously in response to writing in 8- or 16-bit units. Address FFFF 6402 Initial value FFFF...
Page 158 V850E2/PG4-L Section 4 Interrupt Functions EI Level Interrupt Mask Register 3 (IMR3) Access Readable/writable in 1-, 8-, or 16-bit units. All of the corresponding IMR3EIMK [63:48] bits are updated simultaneously in response to writing in 8- or 16-bit units. Address FFFF 6406 Initial value FFFF...
Page 159 V850E2/PG4-L Section 4 Interrupt Functions EI Level Interrupt Mask Register 5 (IMR5) Access Readable/writable in 1-, 8-, or 16-bit units. All of the corresponding IMR5EIMK [95:80] bits are updated simultaneously in response to writing in 8- or 16-bit units. Address FFFF 640A Initial value FFFF...
Page 160 V850E2/PG4-L Section 4 Interrupt Functions EI Level Interrupt Mask Register 7 (IMR7) Access Readable/writable in 1-, 8-, or 16-bit units. All of the corresponding IMR7EIMK [127:112] bits are updated simultaneously in response to writing in 8- or 16-bit units. Address FFFF 640E Initial value FFFF...
Page 161 V850E2/PG4-L Section 4 Interrupt Functions (10) EI Level Interrupt Mask Register 9 (IMR9) Access Readable/writable in 1-, 8-, or 16-bit units. All of the corresponding IMR9EIMK [159:144] bits are updated simultaneously in response to writing in 8- or 16-bit units. Address FFFF 6412 Initial value...
Page 162 V850E2/PG4-L Section 4 Interrupt Functions (12) EI Level Interrupt Mask Register 11 (IMR11) Access Readable/writable in 1-, 8-, or 16-bit units. All of the corresponding IMR11EIMK[191:176] bits are updated simultaneously in response to writing in 8- or 16-bit units. Address FFFF 6416 Initial value FFFF...
Page 163 V850E2/PG4-L Section 4 Interrupt Functions (14) EI Level Interrupt Mask Register 13 (IMR13) Access Readable/writable in 1-, 8-, or 16-bit units. All of the corresponding IMR12EIMK[223:208] bits are updated simultaneously in response to writing in 8- or 16-bit units. Address FFFF 641A Initial value FFFF...
Page 164 V850E2/PG4-L Section 4 Interrupt Functions 4.3.3 ISPR In-Service Priority Register – This register holds the interrupt priority of EI level maskable interrupt (EIINT) that is being processed by the CPU. When this register receives a response to interrupt request reception from the CPU core, the bit corresponding to the interrupt priority of that interrupt request is set.
Page 165 V850E2/PG4-L Section 4 Interrupt Functions 4.3.4 PMR Priority Mask Register – This register specifies an interrupt priority by which an interrupt request flag of EI level maskable interrupt (EIINT) is to be masked. It disables all at once the interrupt requests from the EIINT channel for which the interrupt priority specified by this register is set.
Page 166 V850E2/PG4-L Section 4 Interrupt Functions 4.3.5 ISPC In-Service Priority Clear Register – This register is for the clearing of settings for interrupt priority and for the control of operations. Follow the procedure below to clear ISPR. 1. Write FFFF to ISPC.ISCPC[15:0] (as a 16-bit unit). 2.
Page 167 V850E2/PG4-L Section 4 Interrupt Functions 4.3.6 SCR Selected Channel Hold Register – This register holds the channel number of the EI level maskable interrupt (EIINT). The value of this register is updated when an interrupt vector is reported to the CPU core. Access This register is read-only and is read in 8- or 16-bit units.
Page 168 V850E2/PG4-L Section 4 Interrupt Functions 4.3.7 ICSR Interrupt Controller Status Register – This register indicates the operation status of the interrupt controller. Access This register is read-only and is read in 1-, 8-, or 16-bit units. Either the eight higher-order bits [15:8] or lower-order bits [7:0] may be accessed by reading in 8-bit units.
Page 169 V850E2/PG4-L Section 4 Interrupt Functions 4.3.8 FNC FE Level NMI Status Register – This register is a flag register that indicates the state of control for FE level non-maskable interrupt (FENMI). Access This register is read-only and is read in 1-, 8-, or 16-bit units. Either the eight higher-order bits [15:8] or lower-order bits [7:0] may be accessed by reading in 8-bit units.
Page 170 V850E2/PG4-L Section 4 Interrupt Functions 4.3.9 FIC FE Level INT Status Register – This register is a flag register that indicates the state of control for FE level maskable interrupt (FEINT). Access This register is read-only and is read in 1-, 8-, or 16-bit units. Either the eight higher-order bits [15:8] or lower-order bits [7:0] may be accessed by reading in 8-bit units.
Page 171 V850E2/PG4-L Section 4 Interrupt Functions 4.3.10 INTCFGB FE level Interrupt Switch Register – This register specifies the destination for output from an interrupt source that is switchable between FE-level and EI-level operation. Once a value has been written to this register, the value is locked into the register until a reset.
Page 172 V850E2/PG4-L Section 4 Interrupt Functions 4.3.11 INTSTR0B – Error Interrupt Source Storage Register This register identifies whether an interrupt request is generated or not from an interrupt source that is switchable between FE-level and EI-level operation. An individual bit is set by either the generation of an interrupt from the corresponding source or writing to the corresponding bit in the INTSTS0B register.
Page 173 V850E2/PG4-L Section 4 Interrupt Functions 4.3.12 INTSTC0B – Interrupt Request Flag Clearing Register This register is used to clear error interrupt source flags. Writing 1 to a bit corresponding to an interrupt request flag that you wish to clear causes clearing of the corresponding flag in the interrupt request flag storage register (INTSTR0B) and the value of the bit in this register reverts to Access This register is write-only with writing in 1- or 8-bit units.
Page 174 V850E2/PG4-L Section 4 Interrupt Functions 4.3.13 INTSTS0B – Interrupt Request Flag Setting Register This register sets an interrupt error source flag. Writing 1 to a bit corresponding to an interrupt request flag that you wish to set causes setting of the corresponding flag in the interrupt error source storage register to 1 and the value of the bit in this register reverts to 0.
Page 175 V850E2/PG4-L Section 4 Interrupt Functions 4.4 Interrupt Acknowledgment and Restoring This section describes the operation during interrupt acknowledgment and restoring from interrupt servicing. 4.4.1 FE Level Non-Maskable Interrupt Caused by FENMI Interrupt Request When an FENMI interrupt is requested, an FE level non-maskable interrupt is generated in CPU.
Page 176 V850E2/PG4-L Section 4 Interrupt Functions FENMI interrupt request INTC acknowledged FNC.FNRF ICSR.FNE =1? ICSR.FNR FE level non-maskable Interrupt request is retained interrupt CPU processing FEPC PC value on return FEPSW FEIC Exception code PSW.NP PSW.ID PSW.EP MPM.AUE = 1? PSW.PP PSW.NPV PSW.DMP PSW.IMP...
Page 177 V850E2/PG4-L Section 4 Interrupt Functions 4.4.2 Restore from FE Level Non-Maskable Interrupt (FENMI) An FE level non-maskable interrupt (FENMI) cannot be restored since it is an interrupt used in cases such as when a fatal system error occurs. Execute a system reset after exception processing.
Page 178 V850E2/PG4-L Section 4 Interrupt Functions FEINT interrupt request INTC acknowledged FNC.FNRF ICSR.FNE = 1 or ICSR.FIE = 1? ICSR.FNR FE level maskable Interrupt request is retained interrupt CPU processing PSW.NP = 0 FEPC PC value on return FEPSW FEIC Exception code PSW.NP Interrupt request is retained PSW.ID...
Page 179 V850E2/PG4-L Section 4 Interrupt Functions 4.4.4 Restore from FE Level Maskable Interrupt (FEINT) Servicing Restore from FE level maskable interrupt (FEINT) servicing is performed using the FERET instructions. Execution of the FERET instruction while the PSW.EP bit status is cleared (0) causes restore processing from the FE level maskable interrupt (FEINT).
Page 180 V850E2/PG4-L Section 4 Interrupt Functions 4.4.5 EI Level Maskable Interrupt Caused by EIINT Interrupt Request An EI level-maskable interrupt leads to an EIINT interrupt request for the CPU: the transition to the interrupt handler is in accord with the setting of the IMR register in the interrupt controller (INTC).
Page 181 V850E2/PG4-L Section 4 Interrupt Functions EIINT interrupt request INTC acknowledged EIC.EIRF Corresponding IMR = 1? EIINT interrupt request with priority level lower than ISPR? Priority level masked by PMR? ICSR.PMF ICSR.FNE = 1 or ICSR.FIE = 1? ICSR.EIR EI level maskable Interrupt request is retained interrupt request CPU processing...
Page 182 V850E2/PG4-L Section 4 Interrupt Functions 4.4.6 Restore from EI Level Maskable Interrupt (EIINT) Restore from EI level maskable interrupt (EIINT) is performed using the EIRET instruction. Execution of the EIRET instruction while the PSW.EP bit status is cleared (0) causes restore processing from the interrupt. Completely restoring from interrupt servicing when the PSW.EP bit is "1"...
Page 183 V850E2/PG4-L Section 4 Interrupt Functions 4.5 Interrupt Operation 4.5.1 Mask Function of EI Level Maskable Interrupt (EIINT) Interrupt masking can be specified for each respective interrupt channel of EIINT. Interrupt masking is performed by doing the following register settings. ICxx.MKxx Operation Masks interrupt.
Page 184 V850E2/PG4-L Section 4 Interrupt Functions Table 4-4 Example of EIINT Interrupt Priority Level Settings and Priority Levels EIINT P3xx to P0xx Setting Priority Level During Operation EIINT0 EIINT1 EIINT2 EIINT3 EIINT4 EIINT5 EIINT6 EIINT7 EIINT8 EIINT9 EIINT10 During interrupt servicing, the interrupt controller also processes multiple interrupts acknowledging other interrupts.
Page 185 V850E2/PG4-L Section 4 Interrupt Functions Multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced is shown in Figure 4-6. When an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore, when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the interrupt service program) to set the interrupt enable mode.
Page 186 V850E2/PG4-L Section 4 Interrupt Functions Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are enabled.
Page 187 V850E2/PG4-L Section 4 Interrupt Functions Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k priority is lower than that of i. (level 1) k that occurs after j is acknowledged because it has the higher priority.
Page 188 V850E2/PG4-L Section 4 Interrupt Functions Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first Default priority Servicing of interrupt request c...
Page 189 V850E2/PG4-L Section 4 Interrupt Functions 4.5.3 Priority Mask Function The priority mask function prohibits in batch EIINT interrupts of the specified interrupt priority level. The interrupt masking priority level is specified with the PMR register. Masking and acknowledgment can be set for each priority level. The following operations are possible using this function.
Page 190 V850E2/PG4-L Section 4 Interrupt Functions 4.5.4 Pending Interrupt Report Function The state of the currently pending interrupt can be checked with the pending interrupt report function. This function allows checking of the following states. • When interrupts that are masked only by the priority mask function (PMR) exist The ICSR.PMF bit is set to 1.
Page 191 V850E2/PG4-L Section 4 Interrupt Functions 4.6 Exception Handler Address Switching Function Interrupt handler addresses can be switched by software. For details, refer to V850E2M Architecture Manual (R01US0001E). 4.7 Interrupt Response Times Response times from the generation of an interrupt request until activation of interrupt servicing are described below.
Page 192 V850E2/PG4-L Section 5 DMA Module Section 5 DMA Module The direct memory access (DMA) module is described in this section. 5.1 DMA in Overview DMA channels: This product has 8 DMA channels. Instances index n, n, m, and l are used as shown below: m, and l •...
Page 193 V850E2/PG4-L Section 5 DMA Module Table 5-1 List of DMA Trigger Sources (1/3) DTFRn.IFCn[6:0] DMA Trigger Register Source INTIN000 INTP0 INTIN001 INTP1 INTIN002 INTP2 INTIN003 INTP3 INTIN004 INTP4 INTIN005 INTP5 INTIN006 INTP6 INTIN007 INTP7 INTIN008 INTP8 INTIN009 INTP9 INTIN010 Reserved INTIN011 INTDMA0 INTIN012...
Page 194 V850E2/PG4-L Section 5 DMA Module Table 5-1 List of DMA Trigger Sources (2/3) DTFRn.IFCn[6:0] DMA Trigger Register Source INTIN040 INTTAUB0I13 INTIN041 INTTAUB0I14 INTIN042 INTTAUB0I15 INTIN043 Reserved INTIN044 Reserved INTIN045 Reserved INTIN046 Reserved INTIN047 Reserved INTIN048 Reserved INTIN049 Reserved INTIN050 Reserved INTIN051 Reserved INTIN052...
Page 195 V850E2/PG4-L Section 5 DMA Module Table 5-1 List of DMA Trigger Sources (3/3) DTFRn.IFCn[6:0] DMA Trigger Register Source INTIN080 INTURTH1IT INTIN081 Reserved INTIN082 Reserved INTIN083 Reserved INTIN084 INTTSG20I11 INTIN085 INTTSG20I12 INTIN086 INTTSG20IPEK INTIN087 INTTSG20IVLY INTIN088 Reserved INTIN089 Reserved INTIN090 Reserved INTIN091 Reserved INTIN092...
Page 196 V850E2/PG4-L Section 5 DMA Module 5.2 Definitions The following terms are defined for use in this section,. Table 5-2 List of Term Definitions Terms Meaning DMA transfer The period from the start of a DMA cycle until assertion of INTDMA DMA cycle Period taken to transfer a single transfer unit once, from the start of the cycle of reading by the on-chip system bus to completion of the write cycle.
Page 197 V850E2/PG4-L Section 5 DMA Module 5.3 Overview Direct memory access (DMA) is used to access data without going through the CPU. Internally, the subsystem of this product consists of two units: the DMAC and DTFR (DMA trigger factor register). The DMAC is capable of transferring data at high speeds using the internal system bus.
Page 198 V850E2/PG4-L Section 5 DMA Module INTIN[ l : 0 ] DMAC transfer factors [ l : 0 ] · · · DMA controller DTFR DMAC0 INTDMA[7:0] DMAC transfer completion interrupts DMAC transfer requests [7:0] (INTDMA[7:0]) INTCT[7:0] DMAC transfer count match interrupts INTIN[0] DMAC transfer factor [0] (INTCT[7:0])
Page 199 V850E2/PG4-L Section 5 DMA Module 5.3.3 Memory Map for DMA Access A memory map of the areas accessible by the DMA is given below. Memory Map Memory Map (Upper 256 Mbytes) (Lower 256 Mbytes) FFFF_FFFF H 0FFF_FFFF H On-chip peripheral I/O (PBUS) area FFFF_8000 H FFFF_7FFF H...
Page 200 V850E2/PG4-L Section 5 DMA Module 5.4 DMAC Function 5.4.1 Characteristics Channels 8 (0 channel to 7 channel) Unit of 8 bits data transfer 16 bits 32 bits 128 bits Caution When data-flash memory is selected as the source for transfer, specify the unit of data transfer as 32 or 128 bits.
Page 201 V850E2/PG4-L Section 5 DMA Module Transfer mode • Single transfer mode (when a hardware DNA transfer request is generated) When a hardware DMA transfer request is generated, the controller acquires bus mastership and then releases the bus after one cycle of transfer.
Page 202 V850E2/PG4-L Section 5 DMA Module 5.4.2 Setting Registers Table 5-4 DMAC Setting Registers (1/5) Bit Width for Operations Initial Address Symbol Register Name 16 32 Value √ √ FFFF7300 DTRC0 DMA transfer request control register 0 √ FFFF7310 DTRS0 DMA transfer request select register CH0 0000 √...
Page 203 V850E2/PG4-L Section 5 DMA Module Table 5-4 DMAC Setting Registers (2/5) Bit Width for Operations Initial Address Symbol Register Name 16 32 Value √ FFFF735C DNDA1 DMA next destination address register CH1 R/W 00000000 √ FFFF735C DNDA1L DMA next destination address register 0000 LCH1 √...
Page 204 V850E2/PG4-L Section 5 DMA Module Table 5-4 DMAC Setting Registers (3/5) Bit Width for Operations Initial Address Symbol Register Name 16 32 Value √ FFFF73AC DNSA3 DMA next source address register CH3 00000000 √ FFFF73AC DNSA3L DMA next source address register LCH3 0000 √...
Page 205 V850E2/PG4-L Section 5 DMA Module Table 5-4 DMAC Setting Registers (4/5) Bit Width for Operations Initial Address Symbol Register Name 16 32 Value √ FFFF73F6 DTCC4 DMA transfer count compare register CH4 0000 √ FFFF73F8 DTCT4 DMA transfer control register CH4 0000 √...
Page 206 V850E2/PG4-L Section 5 DMA Module Table 5-4 DMAC Setting Registers (5/5) Bit Width for Operations Initial Address Symbol Register Name 16 32 Value √ FFFF7448 DDC6 DMA destination chip select register CH6 0001 √ FFFF744C DNDA6 DMA next destination address register CH6 00000000 √...
Page 207 V850E2/PG4-L Section 5 DMA Module 5.4.3 Availability of Writing to Control Registers Control registers can be classified into the two groups shown in the table below: those which are always writable and those for which writing is prohibited while DMA transfer is enabled. However, all of the registers are always readable.
Page 208 V850E2/PG4-L Section 5 DMA Module 5.5 DMAC Control Registers 5.5.1 DTRC0: DMA Transfer Request Control Register 0 This eight-bit register includes an error flag and controls the suspension of DMA transfer that is currently in progress. Access This register is readable/writable in 8- or 1-bit units. Address FFFF 7300 Initial value...
Page 209 V850E2/PG4-L Section 5 DMA Module 5.5.2 DTRSn (n = 0 to 7): DMA Transfer Request Select Register This 16-bit register selects requests from the DMA transfer software and hardware. Access This register is readable/writable in 16-bit units. Address DTRS7: FFFF 7460 , DTRS6: FFFF 7430 , DTRS5: FFFF 7400 DTRS4: FFFF 73D0...
Page 210 V850E2/PG4-L Section 5 DMA Module 5.5.3 DSAnL (n = 0 to 7): DMA Source Address Register L This 16-bit register forms the 16 lower-order bits of a 32-bit register used to set a source for transfer over the corresponding DMA channel. Access This register is readable/writable in 16-bit units.
Page 211 V850E2/PG4-L Section 5 DMA Module 5.5.4 DSAnH (n = 0 to 7): DMA Source Address Register H This 16-bit register forms the 16 higher-order bits of a 32-bit register used to set a source for transfer over the corresponding DMA channel. Access This register is readable/writable in 16-bit units.
Page 212 V850E2/PG4-L Section 5 DMA Module 5.5.5 DSCn (n = 0 to 7): DMA Source Chip Select Register This 16-bit register selects the target chip-select area containing the transfer source. Access This register is readable/writable in 16-bit units. Address DSC7: FFFF 7468 , DSC6: FFFF 7438 , DSC5: FFFF 7408 DSC4: FFFF 73D8...
Page 213 V850E2/PG4-L Section 5 DMA Module 5.5.6 DNSAnL (n = 0 to 7): DMA Next Source Address Register L This 16-bit register forms the 16 lower-order bits of a 32-bit register used to set the next source for transfer over the corresponding DMA channel. Access This register is readable/writable in 16-bit units.
Page 214 V850E2/PG4-L Section 5 DMA Module 5.5.7 DNSAnH (n = 0 to 7): DMA Next Source Address Register H This 16-bit register forms the 16 higher-order bits of a 32-bit register used to set the next source for transfer over the corresponding DMA channel. Access This register is readable/writable in 16-bit units.
Page 215 V850E2/PG4-L Section 5 DMA Module 5.5.8 DNSCn (n = 0 to 7): DMA Next Source Chip Select Register This 16-bit register selects the target area containing the source for the next transfer. Access This register is readable/writable in 16-bit units. Address DNSC7: FFFF 7470 , DNSC6: FFFF 7440...
Page 216 V850E2/PG4-L Section 5 DMA Module 5.5.9 DDAnL (n = 0 to 7): DMA Destination Address Register L This 16-bit register forms the 16 lower-order bits of a 32-bit register used to set a destination for transfer over a DMA channel. Access This register is readable/writable in 16-bit units.
Page 217 V850E2/PG4-L Section 5 DMA Module 5.5.10 DDAnH (n = 0 to 7): DMA Destination Address Register H This 16-bit register forms the 16 higher-order bits of a 32-bit register used to set a destination for transfer over the corresponding DMA channel. Access This register is readable/writable in 16-bit units.
Page 218 V850E2/PG4-L Section 5 DMA Module 5.5.11 DDCn (n = 0 to 7): DMA Destination Chip Select Register This 16-bit register selects the target area containing the transfer destination. Access This register is readable/writable in 16-bit units. Address DDC7: FFFF 7478 , DDC6: FFFF 7448 , DDC5: FFFF 7418 DDC4: FFFF 73E8...
Page 219 V850E2/PG4-L Section 5 DMA Module 5.5.12 DNDAnL (n = 0 to 7): DMA Next Destination Address Register L This 16-bit register forms the 16 lower-order bits of a 32-bit register used to set the next destination for transfer over the corresponding DMA channel. Access This register is readable/writable in 16-bit units.
Page 220 V850E2/PG4-L Section 5 DMA Module 5.5.13 DNDAnH (n = 0 to 7): DMA Next Destination Address Register H This 16-bit register forms the 16 higher-order bits of a 32-bit register used to set the next destination for transfer over the corresponding DMA channel. Access This register is readable/writable in 16-bit units.
Page 221 V850E2/PG4-L Section 5 DMA Module 5.5.14 DNDCn (n = 0 to 7): DMA Next Destination Chip Select Register This 16-bit register selects the target area containing the next destination for transfer. Access This register is readable/writable in 16-bit units. Address DNDC7: FFFF 7480 , DNDC6: FFFF 7450 , DNDC5: FFFF 7420...
Page 222 V850E2/PG4-L Section 5 DMA Module 5.5.15 DTCn (n = 0 to 7): DMA Transfer Count Register This 16-bit register sets the number of times unit transfer on the DMA channel is to proceed. Access This register is readable/writable in 16-bit units. Address DTC7: FFFF 7482 , DTC6: FFFF 7452...
Page 223 V850E2/PG4-L Section 5 DMA Module 5.5.16 DNTCn (n = 0 to 7): DMA Next Transfer Count Register This 16-bit register sets the number of times transfer on the DMA channel is to proceed. Access This register is readable/writable in 16-bit units. Address DNTC7: FFFF 7484 , DNTC6: FFFF 7454...
Page 224 V850E2/PG4-L Section 5 DMA Module 5.5.17 DTCCn (n =0 to 7): DMA Transfer Count Compare Register The value in this 16-bit register is compared with that in the DMA transfer counter and interrupts are controlled accordingly. Access This register is readable/writable in 16-bit units. Address DTCC7: FFFF 7486 , DTCC6: FFFF 7456...
Page 225 V850E2/PG4-L Section 5 DMA Module 5.5.18 DTCTn (n = 0 to 7): DMA Transfer Control Register This 16-bit register sets transfer data size and direction (up or down) for counting of addresses. Access This register is readable/writable in 16-bit units. Address DTCT7: FFFF 7488 , DTCT6: FFFF 7458...
Page 226 V850E2/PG4-L Section 5 DMA Module Bit Position Bit Name Function DTCTnSACM1 DMA transfer source address counting direction DTCTnSACM0 These bits specify the direction (up or down) in which counting from the transfer source address for channel n is to proceed. DTCTnSACM1 DTCTnSACM0 Counting Direction...
Page 227 V850E2/PG4-L Section 5 DMA Module 5.5.19 DTSn (n = 0 to 7): DMA Transfer Status Register This 8-bit register is for checking the state of DMA transfer control. Access This register is readable and writable in 1- and 8-bit units. Address DTS7: FFFF 748A , DTS6: FFFF 745A...
Page 228 V850E2/PG4-L Section 5 DMA Module Bit Position Bit Name Function DTSnDTE DMA transfer enable This bit enables or disables DMA transfer. After a 1 is written to this bit, DMA transfer is executed once a DMA transfer request is issued. This bit is automatically cleared (to 0) on completion of DMA transfer if the DTCTnMLE bit is 0.
Page 229 V850E2/PG4-L Section 5 DMA Module 5.6 DMAC Function Details 5.6.1 DMAC Transfer Setting Flow The following figure shows the flow of DMAC transfer settings. Start Set DTS DTSnDTE ← 0 (disable DMA transfer) Set DSA (transfer source address) Set DSC (transfer source chip select) Set DDA (transfer destination address)
Page 230 V850E2/PG4-L Section 5 DMA Module 5.6.2 DMAC Transfer Modes The DMAC supports a single-transfer mode and single-step transfer mode as transfer modes. In either mode, transfer is executed in 2 cycles (dual address transfer) and therefore, a read cycle and a write cycle are generated each time transfer is executed.
Page 231 V850E2/PG4-L Section 5 DMA Module Hardware DMA transfer request 0 (input) Acknowledge 0 (output) Hardware DMA transfer request 1 (input) Acknowledge 1 (output) DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 DMA0 DMA0 Read Read Read Read Write Write Write Write Read Write...
Page 232 V850E2/PG4-L Section 5 DMA Module Hardware DMA transfer request 0 (input) Acknowledge 0 (output) · Software DMA transfer request (CH1) · DMA transfer count setting: 1 time DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 DMA0 DMA1 Read Read Read Read Write Write...
Page 233 V850E2/PG4-L Section 5 DMA Module 5.6.3 DMAC Channel Priority Control The priority of each DMAC0 channel is fixed and the order of priority is as follows: CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7. If another DMA transfer request with a high priority is generated while transfer is in progress, the request with the higher priority always takes precedence.
Page 234 V850E2/PG4-L Section 5 DMA Module 5.6.4 Conditions for Validity of DMA Transfer Requests Whether a request for DMA transfer on channel n is or is not acknowledged depends on the setting of the DTRC0ERR and DTRC0ADS bits of the DMA transfer request control register (DTRC0), the DTCTnMLE bit of the DMA transfer control register (DTCTn), and the DTSnTC and DTSnDTE bits of the DMA transfer status register (DTSn).
Page 235 V850E2/PG4-L Section 5 DMA Module 5.6.5 Next Address Function Next Address Setting Registers These registers are used to set the transfer information for the next transfer in advance while DMA transfer is in progress. This information is copied to the corresponding registers at the start of the last DMA cycle for the current transfer.
Page 236 V850E2/PG4-L Section 5 DMA Module 5.6.6 Suspending/Resuming DMA Transfer Suspending or Resuming DMA Transfer for All Channels through Software Subsequent DMA transfer can be suspended by setting the DMA transfer abort bit (DTRC0ADS) of the DMA transfer request control register (DTRC0). When this is done during a DMA cycle, DMA transfer is suspended on completion of the ongoing DMA cycle.
Page 237 V850E2/PG4-L Section 5 DMA Module 5.6.7 Error Responses Error Response Leading to Suspension of DMA Transfer When an error occurs at the DMA transfer source or transfer destination, DMAC sets the DMA transfer abort bit (DTRC0ADS) of the DMA transfer request control register (DTRC0) to suspend subsequent DMA transfer.
Page 238 V850E2/PG4-L Section 5 DMA Module 5.7 DTFR Functions Each DMA trigger factor register (DTFR) is used to select DMA trigger sources from among interrupt signals and to request DMA transfer by the DMAC. A DTFRn register (n = 7 to 0) is included to select the signals to be used for DMA transfer requests for each channel from among the m = 108 input interrupt signals.
Page 239 V850E2/PG4-L Section 5 DMA Module 5.8 DTFR Control Registers 5.8.1 DTFRn (n = 0 to 7): DMA Trigger Factor Register This 16-bit register selects an activating source to control the start of DMA transfer operations on the corresponding channel. Access This register is readable/writable in 16-bit units.
Page 240 V850E2/PG4-L Section 5 DMA Module 5.8.2 DRQCLR: DMA Request Clear Register This 16-bit register is used to clear activating sources for DAM transfer. Access This register is readable/writable in 16-bit units. Address FFFF 7B40 Initial value 0000 This register is initialized by a reset from any source. RQCR7 RQCR6 RQCR5...
Page 241 V850E2/PG4-L Section 5 DMA Module 5.8.3 DRQSTR: DMA Request Check Register This 16-bit register is used to check the state of DMA transfer requests. Access Only reading is possible and this must be in 16-bit units. Address FFFF 7B44 Initial value 0000 This register is initialized by a reset from any source.
Page 242 V850E2/PG4-L Section 6 Memory Modules Section 6 Memory Modules This section describes the memory modules. Products of this series are equipped with code flash memory, data flash memory, and RAM. Refer to Table 6-1, On-Chip Memory of V850E2/PG4-L Products for the memory size per product. Code flash memory is programmable in two ways: by a flash programmer or by self-programming.
Page 243 V850E2/PG4-L Section 6 Memory Modules 6.1 Features • Single-block erasure • Communicating with the dedicated flash programmer via a serial interface • Voltage for erasure/programming: erasure and programming only require a single power supply • On-board programming • Self-programming of the flash memory 6.1.1 Code Flash Memory •...
Page 244 V850E2/PG4-L Section 6 Memory Modules 6.1.2 Data Flash Memory • ROM capacity: 16 Kbytes • Erasure unit: single block (each taking up 32 bytes) • Programming unit: 2 bytes • Reading unit: 2 bytes • Methods of erasure and programming –...
Page 245 V850E2/PG4-L Section 6 Memory Modules 6.2 Programming Environment Programming, erasure, etc. are handled through a serial interface between the dedicated programmer and this product. Supply the operating clock for this product by mounting oscillators and capacitors to configure an oscillation circuit on the same board as this product.
Page 246 V850E2/PG4-L Section 6 Memory Modules 6.4 Handling of Pins For on-board programming, the target system requires a connector for connection to the dedicated flash programmer. When the transition is made to flash memory programming mode, all of the pins which are not used for flash memory programming are in the same state as just after a reset from normal operating mode (single-chip mode).
Page 247 V850E2/PG4-L Section 6 Memory Modules 6.4.4 FLMD0 Pin Input the high level on FLMD0 except for intervals over which pulses are input during operations in flash memory programming mode (programming, erasure, or reading). After the pulse input, keep the pin at the high level until flash- memory operations are completed.
Page 248 V850E2/PG4-L Section 6 Memory Modules 6.5 Option-Setting Bytes The “option bytes” specify product operation. Values of these bytes are programmed by using the dedicated flash programmer or a function for writing to them. Operation of the product with option bytes erased is not guaranteed. For details, refer to Section 6 OPBT0 - Option Byte Verification Register.
Page 249 V850E2/PG4-L Section 6 Memory Modules 6.5.1 OPBT0 - Option Byte Verification Register This register is used to check the settings of option bytes. Access This register can be read in 32-bit units. Address FF47 000C Initial value FFFF FFF9 The corresponding value is set when the source signal of any reset other than the software reset is generated.
Page 250 V850E2/PG4-L Section 6 Memory Modules 6.6 Product Identification PRDNAME Register This register provides identifying information for the product. Access This register can be read in 32-bit units. Address FF47 0028 (version 1.00 of the μPD70F4154) Initial value 103A0100 (version 1.00 of the μPD70F4155) 103B0100 Table 6-6 PRDNAME Register Contents...
Page 251 V850E2/PG4-L Section 6 Memory Modules PRDSELH Register This register provides identifying information for the product. Access This register can be read in 32-bit units. Address FF47 0024 Initial value FEDF A001 Table 6-7 PRDSELH Register Contents Bit Position Function 31 to 8 31 to 8 Bits Description FEDFA0...
Page 252 V850E2/PG4-L Section 6 Memory Modules PRDSELL Register This register provides identifying information for the product. Access This register can be read in 32-bit units. Address FF47 0020 Initial value 8000 10FF Table 6-8 PRDSELL Register Contents Bit Position Function 31 to 24 31 to 24 Bits Description Code flash memory (384 Kbytes)
Page 253 V850E2/PG4-L Section 6 Memory Modules 6.7 Setting the FLMD Pin Input the high level on the FLMD0 pin when flash-memory operations are to proceed. Use of the on-chip pull-up resistor is selectable by setting a bit in the FLMD control register (the FLMDCNT.FLMDPUP bit) to 1. Table 6-9 List of FLMD Pin Setting Registers Register Name...
Page 254 V850E2/PG4-L Section 6 Memory Modules FLMDPCMD - FLMD Protection Command Register This is the protection command register for FLMDCNT register. For details, refer to Section 6.7.2, Setting the FLMDCNT Register. Access This register can be written in 8-bit units. The value read is always 00 Address FF43 8004 Initial value...
Page 255 V850E2/PG4-L Section 6 Memory Modules 6.7.2 Setting the FLMDCNT Register The FLMDCNT register is protected against writing. Specifically, writing is only effective when performed in the following sequence. STEP1 Write the fixed value (A5 ) to the protection register (FLMDPCMD). STEP2 Write the new setting to the corresponding register (FLMDCNT).
Page 256 V850E2/PG4-L Section 7 Clock Generation Section 7 Clock Generation The clock generator (CG) controls the internal system clocks that are supplied to individual on-board units such as the CPU. It also monitors the input clock to detect abnormalities and has a baud-rate generator to produce the desired output clock signal on the CLKOUT pin.
Page 257 V850E2/PG4-L Section 7 Clock Generation 7.1 Overview of Clock Generation Functional Clock generation involves the following controls and functions. overview • Oscillator – External resonator: 8 MHz (PD70F4155), 16 MHz (PD70F4154) • Clock monitoring (CLMA0 to CLMA2) blocks – CLMA0 monitors the WDTCLKI clock and generates reset signals. This product does not support the generation of interrupt-request signals by CLMA0.
Page 258 V850E2/PG4-L Section 7 Clock Generation 7.2 Configuration INTCLMA1 Option byte CLMA1 CLMA1RES Main Checker CPU system CLK PLL1 Master CPU system CLK PCLK Timer (Internal PRS and BRG) Prescaler Serial (Internal PRS and BRG) CAN (Internal PRS and BRG) A/D (Internal PRS and BRG) SCLK1 BRGA0TCLK BRGA0...
Page 259 V850E2/PG4-L Section 7 Clock Generation 7.3 Selecting the Input Clock Signal The clock generator consists of an oscillator and PLL synthesizers and is capable of, generating internal system clocks at 48, 64, and 80 MHz when an external resonator (crystal oscillator or ceramic oscillator) running at 8 or 16 MHz is connected to the X1 and X2 pins.
Page 260 V850E2/PG4-L Section 7 Clock Generation 7.4 Clock Generating Circuit The structure of the clock generating circuit is described below. Structure of Clock Generating Circuit The circuit consists of the clock oscilation circuit and PLL1. • Main oscillator circuit (Main OSC) The clock signal f produced by the main oscillator circuit provides the clock for the main systems and is input to the PLL.
Page 261 V850E2/PG4-L Section 7 Clock Generation 7.5 Clock Output Function (CLKOUT) The clock-output function handles the output of a clock signal from CLKOUT pin. The signal for output from the CLKOUT pin can be frequency-divided by the baud-rate generator. The figure below is a schematic view of the clock output function. BRGA0CMP [7:0] CLKOUT pin...
Page 262 V850E2/PG4-L Section 7 Clock Generation Clock supply The baud-rate generator BRGA0 provides the following clock input. Table 7-3 Clock Source for BRGA0 BRGA0 Clock Source BRGATCLK Clock selected in the BRGCKCTL register (SCLK1 or PCLK) Interrupt The BRGA interrupt is as indicated in the following table. Table 7-4 BRGA Interrupt BRGA Signal...
Page 263 V850E2/PG4-L Section 7 Clock Generation 7.5.2 BRGA Registers for CLKOUT Function BRGA0 Clock Selection Register (BRGCKCTL) Register BRGCKCTL is an 8-bit register that selects the clock signal for input to the baud-rate generator (BRGA0). Access This register can be read/written in 8-bit units. Address FF42 0030 Initial value...
Page 264 V850E2/PG4-L Section 7 Clock Generation BRGA0 Control Register (BRGA0CTL) Register BRGA0CTL is an 8-bit register that enables counting by the counter, sets the prescaler period, and controls the output of BRGA0. The BRGA0ODIS and BRGA0CCS[1:0] bits can only be modified while the BRGA0CEF bit of BRGA0FLG register is set to 0.
Page 265 V850E2/PG4-L Section 7 Clock Generation Caution 1. Only write to the bits BRGA0CTL.BRGA0ODIS, BRGA0CTL.BRGA0CCS[1:0] and BRGA0CMP.BRGA0CMP[7:0] while the baud-rate counter is stopped (BRGA0FLG.BRGA0CEF = 0). Only reading is possible while the baud-rate generator is operating. The level of the CLKOUT signal and timing of INTBRG0 interrupts become undefined if settings are modified during operations.
Page 266 V850E2/PG4-L Section 7 Clock Generation BRGA0 Compare Register (BRGA0CMP) BRGA0CMP register stores the baud-rate counter comparison value. Access This register can be read/written in 8-bit units. Address FF83900C Initial value This register is initialized by a reset from any source. BRGA0CMP[7:0] Table 7-8 BRGA0CMP Register Contents...
Page 267 V850E2/PG4-L Section 7 Clock Generation 7.6 Single-Pin Debugging Clock (LPDCLK) This is a dedicated operating clock for the single-pin debugging interface. The clock will not stop until the voltage is cut off once it starts operating during single-pin debugging (LPDRES = high level). Therefore, even when a reset is generated during single-pin debugging, the Main OSC and PLL1 never stop.
Page 268 V850E2/PG4-L Section 7 Clock Generation 7.8 Clock Monitor A (CLMAn) Function This product has three instances of the clock monitor A. 7.8.1 Features of the Clock Monitors (CLMAn; n = 0, 1, 2) Table 7-10 Instances Clock Monitor A Number of instances Name CLMAn...
Page 269 V850E2/PG4-L Section 7 Clock Generation Interrupts and The interrupts and reset outputs of the CLMAn are listed in the table below. reset outputs Table 7-13 CLMAn Interrupts and Reset Outputs CLMAn Signal Function Connected to CLMA0: CLMA0RES CLMA0 error reset Reset controller CLMA0RES CLMA1: CLMA1RES...
Page 270 V850E2/PG4-L Section 7 Clock Generation 7.8.2 CLMA Enable and Start-Up Options CLMA Enable Monitoring of clock signals by a clock monitor is set up by setting the CLMAnCTL1, CLMAnCMPL, and CLMAnCMPH registers, and starts when the CLMAnCLME bit in the CLMAnCTL0 register is set to 1. 7.8.3 Functional Overview The clock monitor CLMAn indicates an abnormal frequency of the monitored clock.
Page 271 V850E2/PG4-L Section 7 Clock Generation 7.8.4 Functional Description The clock monitor CLMAn is used to ensure that the frequency of a clock (CLMAnTMON) stays between certain limits. Detection of Abnormal Clock Frequencies Method 1. CLMAn counts the rising edges of the monitored clock CLMAnTMON within 16 cycles of the sampling clock CLMAnTSMP and then compares the counter with the configured thresholds: –...
Page 272 V850E2/PG4-L Section 7 Clock Generation Calculating the Thresholds of CLMAnCMPL.CLMAnCMPL[11:0] and CLMAnCMPH.CLMAnCMPH[11:0] The compare registers CLMAnCMPL and CLMAnCMPH are configured with the minimum and maximum number of clock cycles of CLMAnTMON that are assumed to be valid within 16 cycles of the sampling clock CLMAnTSMP. The expected number of clock cycles is denoted by N.
Page 273 V850E2/PG4-L Section 7 Clock Generation Indication of Abnormal Clock Frequency exceeding the upper threshold indicates clock abnormalities as CLMAnTMON CLMAnTMON too high follows: 1. The reset request signal CLMAnRES (active low) is being output. 2. The peripheral reset signal PERRES is being generated and is resetting CLMAn.
Page 274 V850E2/PG4-L Section 7 Clock Generation Enabling CLMAn (Writing to the CLMAnCTL0 Register) The control register (CLMAnCTL0) is the write-protection register and is used to enable CLMAn. Note Once CLMAn is enabled, it cannot be disabled by software; it can only be disabled by a reset.
Page 275 V850E2/PG4-L Section 7 Clock Generation Examples of CLMAnCMPH and CLMAnCMPL Register Settings Table 7-16 Examples of CLMAnCMPH and CLMAnCMPL Register Settings Operating Frequency Main OSC Monitored Clock Sampling Clock CLMAnCMPH* CLMAnCMPL* CLMA0 48 MHz 8 MHz WDTCLKI Internal OSC/128 0049 0039 64 MHz (Main OSC/32)
Page 276 V850E2/PG4-L Section 7 Clock Generation Behavior (n = 1, 2) after a CLMAn Error-Interrupt Request (CLMAnTI; n = 1, 2) After a CLMA1 Error Interrupt Request (CLMA1TI) The error signal is conveyed to the SGA. The CPU will not operate if its system clock is stopped.
Page 277 V850E2/PG4-L Section 7 Clock Generation 7.8.5 Clock Monitor A Registers Clock monitor A is controlled and operated by the following registers. Register The list of register addresses of clock monitor A is given below. addresses Table 7-17 List of Clock Monitor Registers Register Name Symbol Address...
Page 278 V850E2/PG4-L Section 7 Clock Generation CLMAnCTL1 – CLMAn Control Register 1 This register specifies the signal to be output when the frequency of the clock signal being monitored (CLMAnTMON) is beyond the specified range. For details, refer to Section 7.8.4, (2) Indication of Abnormal Clock Frequency. Access This register can be read/written in 1- or 8-bit units.
Page 279 V850E2/PG4-L Section 7 Clock Generation CLMAnCMPH – CLMAn Compare Register H This register specifies the upper frequency threshold. For details, refer to Section 7.8.4, (1)-(a), Calculating the Thresholds of CLMAnCMPL.CLMAnCMPL[11:0] and CLMAnCMPH.CLMAnCMPH[11:0]. Access This register can be read/written in 16-bit units. It can only be written when CLMAn is disabled (CLMAnCTL0.CLMAnCLME = 0).
Page 280 V850E2/PG4-L Section 7 Clock Generation CLMAnCMPL – CLMAn Compare Register L This register specifies the lower frequency threshold. For details, refer to Section 7.8.4, (1)-(a), Calculating the Thresholds of CLMAnCMPL.CLMAnCMPL[11:0] and CLMAnCMPH.CLMAnCMPH[11:0]. Access This register can be read/written in 16-bit units. It can be written only when CLMAn is disabled (CLMAnCTL0.CLMAnCLME = 0).
Page 281 V850E2/PG4-L Section 7 Clock Generation CLMAnPCMD – CLMAn Protection Command Register This is the protection command register for CLMAnCTL0. For details, refer to Section 7.8.4, (3) Enabling CLMAn (Writing to the CLMAnCTL0 Register). Access This register can be written in 8-bit units. Address <CLMAn_base>...
Page 282 V850E2/PG4-L Section 8 Reset Controller Section 8 Reset Controller This section describes an overview of the reset controller. 8.1 Functional Overview This product incorporates a number of system reset functions. Features A reset can be caused by the following events. summary •...
Page 283 V850E2/PG4-L Section 8 Reset Controller Table 8-1 Reset Sources and Timing of Operations Internal Reset Signals* Self- Flash Reset Diagnostic Reset Input Sequence PLL Lock- Stabilization BIST RESF Source SYSRES LVICLR CPURES PERRES LPDRES Time* up Time* Time* Execution* Register ...
Page 284 V850E2/PG4-L Section 8 Reset Controller Internal Reset Signals The reset controller manages the generation of all internal reset signals upon occurrence of reset requests from various reset sources. • System reset SYSRES The system reset is generated by an external reset or the debug reset. SYSRES is applied to all microcontroller components.
Page 285 V850E2/PG4-L Section 8 Reset Controller 8.2 Functional Description 8.2.1 Reset Flags The reset flag register RESF provides reset flags for each reset source. If a reset has occurred, the assigned flag is set. This way the source of the reset can be evaluated. All flags in RESF are only cleared by SYSRES or by software clear request via the RESFC register.
Page 286 V850E2/PG4-L Section 8 Reset Controller 8.2.2 Low-Voltage Indicator (LVI) The low-voltage indicator circuit (LVI) permanently compares the power supply voltage VDD for the internal regulator with the LVI internal reference voltage If VDD falls below the internal reference voltage (VDD < V ), the internal reset signal LVIRES or the interrupt signal INTLVI is generated.
Page 287 V850E2/PG4-L Section 8 Reset Controller 8.2.3 External RESET A system reset is performed when a low level signal is applied to the RESET pin. SYSRES clears the RESF register to 8000 . The RESF.RESF15 bit represents the external RESET event. The RESF.RESF15 bit is not automatically cleared.
Page 288 V850E2/PG4-L Section 8 Reset Controller 8.2.4 Watchdog Timer Reset The watchdog timer can be configured to generate a reset if the watchdog time expires. After a watchdog reset, RESF.RESF2 for the watchdog timer reset flag (WDTA0RES) is set. RESF.RESF2 is not automatically cleared. It is cleared by •...
Page 289 V850E2/PG4-L Section 8 Reset Controller 8.2.6 Clock Monitor Reset The clock monitors supervise the various internal clock signals. On detecting deviation of a clock signal from the expected range, the corresponding monitor generates a reset. • CLMA0RES: A failure in the main oscillation circuit is being detected. •...
Page 290 V850E2/PG4-L Section 8 Reset Controller 8.2.7 Self-Diagnostic BIST Reset Self-diagnostic BIST is usually executed after release from any reset source (except SWRES). This kind of reset is generated after self-diagnostic BIST to initialize the circuits that are the target of self-diagnostic BIST. The generation of BISTRES is indicated by RESF.RESF7.
Page 291 V850E2/PG4-L Section 8 Reset Controller 8.2.9 Reset Flag Evaluation After any CPU reset (CPURES), the software starts at the reset vector which is always located at address 0000 0000 Because each reset source will set its respective reset flag, if the reset flag register RESF is equal to 0000 , a faulty software is assumed.
Page 292 V850E2/PG4-L Section 8 Reset Controller 8.2.10 Protection for Registers of the Reset Controller The write-protected registers are protected from inadvertent write access due to the execution of erroneous program code, etc. Write access to write-protected registers is only possible within a special sequence of instructions shown below.
Page 293 V850E2/PG4-L Section 8 Reset Controller 8.3 Registers This section contains a description of all registers of the reset controller. 8.3.1 Overview of Reset Controller Registers The reset controller is controlled and operated by the following registers. Table 8-2 List of the Reset Controller Registers Register Name Symbol Address...
Page 294 V850E2/PG4-L Section 8 Reset Controller 8.3.2 Details of Reset Controller Registers RESF - Reset Source Register This register contains information about which type of resets occurred since the last SYSRES (RESET/DBRES). Each following reset condition sets the corresponding flag in the register. For example, if a clock monitor CLMA0RES occurs after a watchdog timer reset WDTA0RES, this register reads 000C Access...
Page 295 V850E2/PG4-L Section 8 Reset Controller Caution If the generation of a reset and writing to the RESFC register are in contention, the setting for generation of the reset takes priority. Note After writing to the RESFS and RESFC registers, actual reflection of the written value in the register takes at least 6 cycles of the PLL input clock.
Page 296 V850E2/PG4-L Section 8 Reset Controller RESFC - Reset Source Clear Register This register clears the reset flags of the RESF register. Access This register can be read/written in 16-bit units. When read, the value returned is 0000 Address FF42 0028 Initial value 0000 This register is initialized by a reset from any source.
Page 297 V850E2/PG4-L Section 8 Reset Controller RESFS - Reset Source Set Register This register is for testing of the RESF register. Even if the flag corresponding to a reset source is set in the RESF register, the corresponding reset will not be generated.
Page 298 V850E2/PG4-L Section 8 Reset Controller 8.3.3 Details of Software Reset Control Registers SWRESA - Software Reset Register This register is used to generate a software reset SWRES. Access This register can only be written in 8-bit units. When read, the value returned is Writing to this register is protected by a special sequence of instructions by using the protection command register CSCPCMD.
Page 299 V850E2/PG4-L Section 8 Reset Controller 8.3.4 Details of Protection Command Registers CSCPCMD - Protection Command Register This register is the protection command register for the write protected reset controller registers. Access This register can be written in 8-bit units. When read, the value returned is 0. Address FF42 0014 Initial value...
Page 300 V850E2/PG4-L Section 8 Reset Controller 8.4 Power-on Flag/Low Voltage Indicator (POF/LVI) 8.4.1 Overview of the POF/LVI Function POF function The power-on flag (the POF.POF bit) is set to 1 if the power supply voltage for the internal regulator (VDD) falls below the POF detection voltage. LVI function The LVI sets the LVI detection flag (LVISF) to 1 and generates an interrupt signal (INTLVI) or a reset signal (LVIRES) if the power supply voltage for the...
Page 301 V850E2/PG4-L Section 8 Reset Controller 8.4.2 Operation POF Detection Monitoring of the power supply voltage for the internal regulator leads to setting of the power-on flag (the POF.POF bit) if the power supply voltage for the internal regulator falls below the prescribed detection voltage (both when the voltage is supplied and when the voltage is cut off).
Page 302 V850E2/PG4-L Section 8 Reset Controller LVI Operation Monitoring of the power supply voltage for the internal regulator after setting the LVICNT bit to 1 can be used to generate an interrupt signal (INTLVI) or a reset signal (LVIRES) in accord with the setting of the LVICNT.LVIMD bit when the power supply voltage for the internal regulator falls below the prescribed detection voltage.
Page 303 V850E2/PG4-L Section 8 Reset Controller (b) Using the LVI for the Output of Interrupt Request Signals <Starting LVI operation> 1. Set the interrupt controller so that the interrupt (INTLVI) is masked. 2. Set the LVICNT.LVIMD bit to 0 (selecting the output of an interrupt). Since this is the initial setting, explicitly making this setting is not generally required.
Page 304 V850E2/PG4-L Section 8 Reset Controller 8.4.3 Overview of POF/LVI Registers Table 8-10 List of POF/LVI Registers Register Name Symbol Address Power-on flag control registers Power-on flag register FFFF FC00 Power-on flag clear register POFC FFFF FC04 Power-on flag set register POFS FFFF FC08 LVI control registers...
Page 305 V850E2/PG4-L Section 8 Reset Controller 8.4.4 Details of POF / LVI Control Registers POF - Power-on Flag Register This register is used to confirm the state of the power-supply voltage for the internal regulator (VDD). When the voltage has fallen below the detection voltage, the POF bit is set to 1 (i.e.
Page 306 V850E2/PG4-L Section 8 Reset Controller POFS - Power-on Flag Set Register This register is used to set the POF bit in the POF register to 1. Access This register can be written in 8-bit units. When read, the value returned is 00 Address FFFF FC08 Initial value...
Page 307 V850E2/PG4-L Section 8 Reset Controller Table 8-14 LVICNT Register Contents Bit Position Bit Name Function LVIMD This bit specifies the output signal in response to the LVI detecting an abnormal voltage. 0: The output is an interrupt signal (INTLVI). 1: The output is a reset signal (LVIRES). LVICNT1, These bits enables/disables voltage detection by the LVICNT0...
Page 308 V850E2/PG4-L Section 9 Safety Functions Section 9 Safety Functions This section describes an overview of the safety functions. The safety functions are as follows. • Peripheral bus access error detection • Memory access protection • Self-diagnostic BIST • ECC 9.1 Peripheral Bus Access Error Detection This product incorporates a detector for errors in peripheral bus access.
Page 309 V850E2/PG4-L Section 9 Safety Functions 9.3 Registers Related to the Peripheral I/O Bus Registers related to the peripheral I/O bus are described in this section. 9.3.1 Overview of Registers Related to the Peripheral I/O Bus Table 9-1 List of Registers Related to the Peripheral I/O Bus Register Name Symbol Address...
Page 310 V850E2/PG4-L Section 9 Safety Functions 9.3.2 Details of Registers Related to the Peripheral I/O Bus APC - Peripheral I/O Bus PSELG Control Register This register is used to specify several forms of checking for errors in access over the peripheral I/O bus. Access This register can be read/written in 8-bit units.
Page 311 V850E2/PG4-L Section 9 Safety Functions APES - Peripheral I/O Bus PSELG Error Status Register This register contains error flags generated during the peripheral I/O bus access. Access This register can be read in 8-bit units. Address FF45 4004 Initial value This register is initialized by a reset from any source or by writing to the APEC register.
Page 312 V850E2/PG4-L Section 9 Safety Functions APEC - Peripheral I/O Bus PSELG Error Status Clear Register This register is used to clear the several error flags which may be generated by access over the peripheral I/O bus. Access This register can be written in 8-bit units. When read, the value returned is 00 Address FF45 4008...
Page 313 V850E2/PG4-L Section 9 Safety Functions APAM - Peripheral I/O Bus PSELG Error Address Store Register This register holds the address where access over the peripheral I/O bus led to any of the several errors. In cases where multiple errors are generated, this register holds the address of the most recent error.
Page 314 V850E2/PG4-L Section 9 Safety Functions MATS - Peripheral I/O Bus Maximum Access Time Set Register This register is used to prevent blocking of access to the peripheral I/O bus by specifying the maximum bus access time (timeout time). Access over the peripheral I/O bus is forcibly ended when the time taken exceeds the time specified here.
Page 315 V850E2/PG4-L Section 9 Safety Functions 9.4 Overview of Self-Diagnostic BIST This section contains a general description of the self-diagnostic BIST. Caution The registers listed below are beyond the scope of self-diagnostic BIST. Accordingly, except in the case of BSEQ0STRHBT and BSEQ0CTL, software must run self-diagnosis for these registers (by reading from and writing to the register or setting and clearing its bits).
Page 316 V850E2/PG4-L Section 9 Safety Functions 9.4.2 Output of a Toggled Signal during Execution of Self- Diagnostic BIST A Toggled signal can be output while self-diagnostic BIST is executed. This function can be used, for example, to clear the counter of the external watch dog timer.
Page 317 V850E2/PG4-L Section 9 Safety Functions Caution • When FOP23 = 0, an oscillation stabilization time is inserted after an LVI reset or CLM reset. • The value of FOP23 determines the function of the P8_0/TGLOUT pin. When FOP23 = 0 and HWBISTEN is set for skipping of Self-Diagnostic BIST, the pin continues to operate as TGLOUT after release from the reset state.
Page 318 V850E2/PG4-L Section 9 Safety Functions 9.5 Self-Diagnostic BIST Related Registers This section contains a general description of the registers related to Self- diagnostic BIST. 9.5.1 Overview of Registers Related to Self-Diagnostic BIST Table 9-9 List of Registers Related to Self-Diagnostic BIST Register Name Symbol Address...
Page 319 V850E2/PG4-L Section 9 Safety Functions 9.5.2 Details of Registers Related to Self-Diagnostic BIST TGLOUTOE—TGLOUT Output Control Register This register controls the output from the P8_0/TGLOUT pin. Output from the P8_0/TGLOUT pin is controlled by the setting of the TGLOUTOE0 bit. Port/control mode or TGLOUT mode is selected by the value.
Page 320 V850E2/PG4-L Section 9 Safety Functions Caution After executing the instruction to write to this register, the completion of actual writing takes time. Ensure an interval of at least 6 cycles of the PLL input clock between consecutive rounds of writing to this register. Example: When heapclk is running at 80 MHz, ensure an interval of at least 60 cycles of heapclk.
Page 321 V850E2/PG4-L Section 9 Safety Functions BSEQ0CTL - Self-Diagnostic BIST Control Register This register is used to specify whether to skip or execute Self-diagnostic BIST. The register is not a target for Self-Diagnostic BIST and has a majority circuit. Since this register is write-protected, it is only accessible by following the designated sequence (regarding the designated sequence for the BSEQ0CTL register, refer to Section 8.2.10, Protection for Registers of the Reset Controller).
Page 322 V850E2/PG4-L Section 9 Safety Functions Majority method When writing to the address of a register having the majority structure, the same value is written to three majority registers. When reading, the value read is that for which at least two of the three registers have the same value. If the value in a register is inverted due to a malfunction, reading from the corresponding address corrects it.
Page 323 V850E2/PG4-L Section 9 Safety Functions BSEQ0TCRPCMD - BIST Protection Command Register This register is a command register for the write-protected BIST registers. Access This register can be written in 32-bit units. Address FF83 B000 Initial value Undefined Table 9-13 BSEQ0TCRPCMD Register Contents Bit Position Bit Name Function...
Page 324 V850E2/PG4-L Section 9 Safety Functions BSEQ0STRHBT - Self-Diagnostic BIST Status Register This register indicates the state of self-diagnostic BIST. Access This register can be read in 32-bit units. Address FF83 B008 Initial value 0000 FF00 This register is initialized by a reset from any source. BCE MPE CPE HWBS HWBS...
Page 325 V850E2/PG4-L Section 9 Safety Functions Table 9-15 Contents of the BSEQ0STRHBT Registe (2/2) Bit Position Bit Name Function 7 to 0 HWBS[7:0] The state of self-diagnostic BIST by the master's BIST sequencer 0: The sequence of self-diagnostic BIST by the master ended abnormally, did not end, or has not started.
Page 326 V850E2/PG4-L Section 9 Safety Functions BSEQ0STCHBT - Self-Diagnostic BIST Status Clear Trigger Register This register is used to clear error source flags in the BSEQ0STRHBT register. This register has a designated sequence, so only access in that sequence will be effective for writing. For details, see Section 9.5.3, Procedure for Setting the BSEQ0STCHBT Register.
Page 327 V850E2/PG4-L Section 9 Safety Functions SGAEPCTL - SGA Error Pulse Control Register This register is used to select the timer for dynamic-mode operation (for details, see Section 10.3.3, Operations for Error Output). Access This register can be read/written in 8-bit units. Address FF83 F020 Initial value...
Page 328 V850E2/PG4-L Section 9 Safety Functions (10) LRAMSTBYCTL – On-Chip RAM Resumption–Standby Control Register This register prohibits access to and protects the on-chip RAM. This register can be set so that the data in on-chip RAM are retained after a reset. This register is initialized when the power supply is turned on or the power supply voltage for the internal regulator (VDD) falls below the detection voltage indicated for the POF.
Page 329 V850E2/PG4-L Section 9 Safety Functions 9.5.3 Procedure for Setting the BSEQ0STCHBT Register The BSEQ0STCHBT register is write-protected, and is thus only writable by following the designated sequence below. Step 1: Write the designated value (000000A5 ) to the protection- command register (BSEQ0TCRPCMD). Step 2: Write the desired setting to the target write-protected register (BSEQ0STCHBT).
Page 330 V850E2/PG4-L Section 9 Safety Functions 9.6 ECC Related Registers This section describes the ECC related registers. 9.6.1 Overview of ECC Related Registers Table 9-19 Contents of the ECC Related Registers Register Name Symbol Address Code flash ECC Code flash ECC error flag register CECCER FF43 2000 Code flash ECC error flag clear register...
Page 331 V850E2/PG4-L Section 9 Safety Functions 9.6.2 Details of ECC Related Registers CECCER - Code Flash ECC Error Flag Register The corresponding bit in this register is set when an ECC error is generated. Access This register can be read in 8-bit units. Address FF43 2000 Initial value...
Page 332 V850E2/PG4-L Section 9 Safety Functions CECCERC - Code Flash ECC Error Flag Clear Register This register is used to clear values set in the CECCER register. Specifically, writing 1 to an effective bit in this register clears the corresponding bit in the CECCER register.
Page 333 V850E2/PG4-L Section 9 Safety Functions CECADR - Code Flash ECC Error Correction Address Register If ECC correction occurs, this register holds the corresponding address. If the CECCER.CECCER0ECFLG is 0, the stored address where the error was encountered is not changed until clearing of the CECCER0ECFLG. Access This register can be read in 32-bit units.
Page 334 V850E2/PG4-L Section 9 Safety Functions CEDADR - Code Flash ECC Error Detection Address Register When an ECC error is encountered, this register holds the corresponding address. If CECCER.CECCER0EDFLG is 0, the stored address where the error was encountered is not changed until clearing of CECCER0EDFLG. Access This register can be read in 32-bit units.
Page 335 V850E2/PG4-L Section 9 Safety Functions LECCER - On-chip RAM ECC Error Flag Register This register indicates the occurrence of ECC correctable and uncorrectable errors in the on-chip RAM. Access This register can be read in 8-bit units. Address FF46 8000 Initial value This register is initialized by a reset from any source.
Page 336 V850E2/PG4-L Section 9 Safety Functions LECCERC - On-chip RAM ECC Error Flag Clear Register This register is used to clear values set in the LECCER register. Specifically, writing 1 to an effective bit in this register clears the corresponding bit in the LECCER register.
Page 337 V850E2/PG4-L Section 9 Safety Functions LECADR - On-chip RAM Error Correction Address Register When an ECC error is encountered in access to on-chip RAM, this register holds the corresponding address. If LECCER.LECCER0ECFLG is 0, the stored address where the error was encountered is not changed until clearing of LECCER0ECFLG.
Page 338 V850E2/PG4-L Section 9 Safety Functions LEDADR - On-chip RAM ECC Error Detection Address Register When an ECC error is encountered in access to on-chip RAM, this register holds the corresponding address. If LECCER.LECCER0EDFLG is 0, the stored address where the error was encountered is not changed until clearing of LECCER0EDFLG.
Page 339 V850E2/PG4-L Section 9 Safety Functions E6A0CTL - CAN0 ECC0 Control Register When an ECC error is generated in the CAN RAM, the corresponding bit in this register is set to 1 or the current setting is cleared. Writing 1 to a bit in this register clears the bit.
Page 340 V850E2/PG4-L Section 9 Safety Functions (10) E6A2CTL - CAN1 ECC0 Control Register When an ECC error is generated in the CAN RAM, the corresponding bit in this register is set to 1 or the current setting is cleared. Writing 1 to a bit in this register clears the bit.
Page 341 V850E2/PG4-L Section 9 Safety Functions 9.7 Self-Diagnosis Method for a Compare Unit Follow the procedure below to execute self-diagnosis of a comparison unit during operations. The behavior is not guaranteed in case of departure from the procedure described. Procedure 1 1.
Page 342 V850E2/PG4-L Section 9 Safety Functions 9.8 Resources Required for Initialization 9.8.1 On-chip RAM Initial values in on-chip RAM are undefined, so reading it without initialization raises the possibility of an ECC error. Accordingly, we recommend initializing the whole on-chip RAM (with any desired values). Caution After an uninitialized address is written to, if the same address is read following the write, an ECC error may occur.
Page 343 V850E2/PG4-L Section 9 Safety Functions Table 9-31 List of Registers to be Initialized (System Registers) Number of System Group Name Bank Name Register Name Function CPU group Base bank EIPC This register preserves the state on acceptance of an EI level exception.
Page 344 V850E2/PG4-L Section 9 Safety Functions Table 9-32 List of Registers to be Initialized (CPU core Protection Related Registers) Address Name Function FFFF5110 VPNECR Peripheral device protection NT state violation cause register FFFF5110 VPNECRL Peripheral device protection NT state violation cause register L FFFF5110 VPNECRLL Peripheral device protection NT state violation cause register LL...
Page 345 V850E2/PG4-L Section 9 Safety Functions Table 9-33 List of Registers to be Initialized (Registers Related to the Timing Supervisor) Address Name Function FFFF5024 TSCCNT0 Count value of timing supervision counter n register 0 FFFF5028 TSCCMP0 Comparison value of timing supervision counter n register 0 FFFF502C TSCRLD0 Reload value of timing supervision counter n register 0...
Page 346 V850E2/PG4-L Section 10 Safety Guardian (SGA) Section 10 Safety Guardian (SGA) This section gives an overview of the SGA. 10.1 SGA Features Number of This product has a single SGA. instances Table 10-1 Instances of SGA Instances Names SGA (common area), SGAM, SGAC Meaning of m in Throughout this section, the SGAM and SGAC are collectively referred to by names...
Page 347 V850E2/PG4-L Section 10 Safety Guardian (SGA) Clock supply All SGA provide one clock input. Table 10-3 SGA Clock Supply SGA Area SGA Clock Connected to SGA, SGAM, PCLK Clock controller SGAC Interrupts The SGA can generate the following interrupt requests. Table 10-4 SGA Interrupt Requests SGA Signal...
Page 348 V850E2/PG4-L Section 10 Safety Guardian (SGA) Table 10-5 SGA Error Input Signals (2/2) SGA Signal Function Connected to SGATERRIN37 Reserved Reserved SGATERRIN38 Unintentional enabling of production test mode TEST_ENABLE SGATERRIN39 CPU mode error: This error is generated on detection CPU_MODE_ERR of an unintentional change to the CPU operating mode.
Page 349 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.2 SGA Functional Overview The safety guardian (SGA) collects all the internal error signals coming from the different error sources and monitoring circuits. These errors are for instance generated by the clock monitor, ECC circuit, compare unit, and other monitoring units.
Page 350 V850E2/PG4-L Section 10 Safety Guardian (SGA) The following block diagram shows the main components of the SGA. SGA master PCLK Peripheral bus SGATERROUTZ SGATTIN SGAM_base SGATERRINxx SGATERRINxx SGA_base SGATERRLB SGARES SGATI SG_CMP_ERR SGA checker PCLK Peripheral bus SGATTIN SGAC_base SGATERRINxx SGA_base SGATERRLB SG_CMP_ERR...
Page 351 V850E2/PG4-L Section 10 Safety Guardian (SGA) The SGA is divided into the indirect safety guardian (ISG) and direct safety guardian (DSG). • ISG is used for static configuration of the error sources. • DSG consists of combinatorial logic only. Therefore, it is robust against clock faults and able to indicate an error towards SGATERROUTZ even in case of clock faults.
Page 352 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.3 Functional Description 10.3.1 SGA Operating States The SGA operation can be sub-divided into four main phases. • Reset: Hardware initialization of the device. • Start-up test: Execution/Evaluation of self-diagnostic BIST and software self-test •...
Page 353 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.3.2 SGA Configuration Overview The SGA supports the following functions. • Error set/clear register – The error set/clear register is used to enter or release the active or inactive error state. Where active (error set) means that the error output SGATERROUTZ is low independent from the error inputs SGATERRINxx.
Page 354 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.3.3 Operations for Error Output The error output SGATERROUZ is connected to the ERROROUT pin. The error output can be configured for two different modes of operation, non- dynamic or dynamic. Table 10-7 Operating Modes for Error Output Error Status SGAmESSTR y.SGAmSSE0...
Page 355 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.3.4 Loop-Back Function The SGA supports a loop-back function which is used to check the error path from the SGA to the ERROROUT pin. The SGATERRLB is connected to the ERROROUT pin and the level of the output is reflected to the SGAmSSE131 bit, shown in Table 10-14, SGAmESSTR1 Register Contents.
Page 356 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.3.5 Pseudo Error Generation The SGA supports a pseudo error injection function to “emulate” an error for test or debug purposes. The operation of the SGA during injection of pseudo errors is identical to the occurrence of real errors. This means that all configurations for error masks, interrupt, or internal reset apply in the same way.
Page 357 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.3.6 Error Status The error status is indicated by the SGAmESSTR0 and SGAmESSTR1 registers. The error status is only cleared after external reset by RESET. In case of an internal reset, the status is kept and the error source can be evaluated afterwards by reading the SGAmESSTR0 and SGAmESSTR1 registers.
Page 358 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.3.7 Writing to Protected Registers Write protected registers are protected from inadvertent write access due to erroneous program execution, etc. An overview of the related registers is shown in Table 10-10, Overview of SGA Registers. Protection Unlock Sequence Write access to a write protected register is only possible within a special protection unlock sequence.
Page 359 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.4 Registers This section contains a description of all registers of the SGA. 10.4.1 Overview of SGA Registers The SGA is controlled and operated by the following registers. Table 10-8 Overview of SGA Master Registers Write Protected by Special Register Name...
Page 360 V850E2/PG4-L Section 10 Safety Guardian (SGA) 10.4.2 SGA Registers Details SGAmESET SGAm Error Set Trigger Register This register is used to set error output signals to the low (active) level. The given error output is immediately set to the active level after a value is written to this register.
Page 361 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAmECLR - SGAm Error Clear Trigger Register This register is used to deactivate error output (by placing the signal at the high level). If no further errors are pending, the setting is immediately effective for the signal on the error pin.
Page 362 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAmESSTR0 - SGAm Error Source Status Register 0 This register shows the status of each error source. The status is indicated regardless of mask settings. Access This register can be read in 32-bit units. Address <SGAm_base>...
Page 363 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAmESSTR1 - SGAm Error Source Status Register 1 This register shows the status of each error source. The status is indicated regardless of mask settings. Access This register can be read in 32-bit units. Address <SGAm_base>...
Page 364 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAmPCMD0 - SGAm (Master/Checker) Protection Command Register This register is the protection command register for the SGAm (master/ checker) register. For a list of protected registers, refer to Table 10-10, Overview of SGA Registers. For details on the register write protection sequence, refer to Section 10.3.7, Writing to Protected Registers.
Page 365 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAEPCFG - SGA Error Pulse Configuration Register This register is used to specify the operating mode for the error output signal. Access This register can be read/written in 32-bit units. Writing to this register is protected by a sequence of instructions.
Page 366 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAICFG1 - SGA Interrupt Configuration Register 1 This register is used to set generation of the SGATI interrupt. Specifically, the generation of interrupts in response to errors (SGATERRINxx) is selectable. Access This register can be read/written in 32-bit units. Writing to this register is protected by a sequence of instructions.
Page 367 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAIRCFG0 - SGA Internal Reset Configuration Register 0 This register is used to set the generation of internal resets in response to internal errors. Access This register can be read/written in 32-bit units. Writing to this register is protected by a sequence of instructions.
Page 368 V850E2/PG4-L Section 10 Safety Guardian (SGA) SGAIRCFG1 - SGA Internal Reset Configuration Register 1 This register is used to set the generation of internal resets in response to internal errors. Access This register can be read/written in 32-bit units. Writing to this register is protected by a sequence of instructions.
Page 369 V850E2/PG4-L Section 10 Safety Guardian (SGA) (10) SGAEMK0 - SGA Error Mask Register 0 This register is used to mask individual error sources (SGATERRINxx) for the error output signal SGATERROUTZ. Access This register can be read/written in 32-bit units. Writing to this register is protected by a sequence of instructions.
Page 370 V850E2/PG4-L Section 10 Safety Guardian (SGA) (11) SGAEMK1 - SGA Error Mask Register 1 This register is used to mask individual error sources (SGATERRINxx) for the error output signal SGATERROUTZ. Access This register can be read/written in 32-bit units. Writing to this register is protected by a sequence of instructions.
Page 371 V850E2/PG4-L Section 10 Safety Guardian (SGA) (12) SGAESSTC0 - SGA Error Source Status Clear Register 0 This register is used to clear the individual error source status of the SGAESSTR0 register. The error status of both SGAM and SGAC is cleared simultaneously.
Page 372 V850E2/PG4-L Section 10 Safety Guardian (SGA) (13) SGAESSTC1 - SGA Error Source Status Clear Register 1 This register is used to clear the individual error source status of the SGAESSTR1 register. The error status of both SGAM and SGAC is cleared simultaneously.
Page 373 V850E2/PG4-L Section 10 Safety Guardian (SGA) (14) SGAPCMD1 - SGA Protection Command Register This register is the protection command register for the SGA register. For a list of protected registers, refer to Table 10-10, Overview of SGA Registers. For details about the register write protection sequence, refer to Section 10.3.7, Writing to Protected Registers.
Page 374 V850E2/PG4-L Section 10 Safety Guardian (SGA) (15) SGAPS - SGA Protection Status Register This register is used to verify whether the write protected register has been written successfully or not. For details, refer to Section 10.3.7, Writing to Protected Registers. Access This register can be read in 32-bit units.
Page 375 V850E2/PG4-L Section 10 Safety Guardian (SGA) (16) SGAPE0 - SGA Pseudo Error Register 0 This register is used to generate a pseudo error for test purposes. The SGA operation in response to the generation of a pseudo error is identical to that in response to a real error signal on SGATERRINxx.
Page 376 V850E2/PG4-L Section 10 Safety Guardian (SGA) (17) SGAPE1 - SGA Pseudo Error Register 1 This register is used to generate a pseudo error for test purposes. The SGA operation in response to the generation of a pseudo error is identical to that in response to a real error signal on SGATERRINxx.
Page 377 V850E2/PG4-L Section 10 Safety Guardian (SGA) (18) SGAEPCTL - SGA Error Pulse Output Control Register This register is used to select the timer for the output of error signals while the SGA is in dynamic mode. Access This register can be read/written in 8-bit units. Address FF83 F020 Initial value...
Page 378 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) Section 11 Data CRC Function A (DCRA) This section contains a generic description of the data CRC function A (DCRA). 11.1 DCRA Features Instances This product has the following number of instances of the data CRC function A. Table 11-1 Instances of DCRA Data CRC Function A...
Page 379 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) 11.2 Functional Overview Features The data CRC function A can be used to verify or generate CRC protected summary data streams of arbitrary length and different bit widths. • 32-bit Ethernet CRC (04C11DB7 + 1) XOR of the result for the generated CRC code and FFFFFFFF Calculation result (DCRAnCOUT)
Page 380 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) The following figure shows the block diagram of the data CRC function A. PBUS DCRAnCIN (8/16/32 bits) 16-bit CCITT 32-bit Ethernet CRC code generator CRC code generator DCRAnCTL. Selector DCRAnPOL DCRAnCOUT EXOR PBUS Figure 11-1 Block Diagram of Data CRC Function A...
Page 381 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) 11.3 Functional Description The data CRC function A generates a CRC (cyclic redundancy check) of an arbitrary data block length. The data is forwarded to the data CRC function in 8-, 16-, or 32-bit units. The CRC polynomial can either be selected for 32-bit Ethernet or 16-bit CCITT.
Page 382 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) 11.4 Registers This section contains a description of all registers of the DCRA. 11.4.1 DCRA Registers Overview The DCRA is controlled and operated by the following registers. Table 11-4 DCRA Registers Overview Register Name Symbol Address...
Page 383 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) 11.4.2 DCRA Registers Details DCRAnCIN ― CRC Input Register This register holds the input data for the CRC calculation. The effective bit width used for CRC calculation must be set by DCRAnCTL.DCRAnISZ[1:0]. When data is written to this register, the CRC code is generated.
Page 384 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) DCRAnCOUT ― CRC Data Register This register stores the result of the CRC code generated by the 32-bit Ethernet or 16-bit CCITT polynomial. Access This register can be read/written in 32-bit units. Address <DCRAn_base0>...
Page 385 V850E2/PG4-L Section 11 Data CRC Function A (DCRA) DCRAnCTL ― CRC Control Register This register controls the CRC generation process. Access This register can be read/written in 8-bit units. Address <DCRAn_base1> + 20 Initial value This register is initialized by any reset sources. DCRAn DCRAnISZ[1:0] Table 11-7...
Page 386 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) Section 12 Window Watchdog Timer A (WDTA) This section contains a generic description of the window watchdog timer A (WDTA). 12.1 WDTA Features Instances This product has one instance of the window watchdog timer A. Table 12-1 Instances of WDTA Window Watchdog Timer A...
Page 387 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) Interrupts and The interrupts and reset outputs of the WDTAn are listed in the table below. reset outputs Table 12-4 WDTA Interrupts and Reset Outputs WDTAn Signal Function Connected to WDTA0TRES WDTA0 error reset Reset controller: WDTA0RES Safety guardian: SGATERRIN3 WDTA0TNMI...
Page 388 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) 12.3 Functional Description The WDTA generates a reset or a non-maskable interrupt if the 16-bit counter overflows or if any other error condition is fulfilled. For a description of all error conditions, refer to Section 12.3.3, Error Detection. The counter is cleared and restarted every time a WDTA trigger occurs in the window-open period.
Page 389 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) WDTA start timing The WDTA start timing and the changes to the WDTA settings are illustrated in the following figure. FFFF H Overflow value Counter value 0000 H Reset First WDTAnMD release trigger write Figure 12-2...
Page 390 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) 12.3.3 Error Detection The conditions for error detection are: • Overflow time is exceeded (counter overflow) • Wrong activation code is written to the trigger register • Writing to the trigger register outside the open window. •...
Page 391 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) The following figure shows the reset or NMI request generation when the counter overflows. FFFF H Overflow value Counter value WDTAnTRES or WDTAnTNMI Reset Error WDTAnMD First System Reset release detection write trigger reset release...
Page 392 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) 12.3.4 75% Interrupt Output When the counter reaches 75% of the overflow value, the interrupt request WDTAnTIT is generated. The WDTAnMD.WDTAnWIE register enables/disables this function. The following figure shows the 75% interrupt request generation with the following conditions: •...
Page 393 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) 12.3.5 Window Function When the window-open period is set to less than 100%, an error is detected if the trigger occurs outside the open window. The definition of the window-open period differs before and after the first trigger.
Page 394 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) 12.4 Registers This section contains a description of all registers of the WDTA. 12.4.1 WDTA Registers Overview The WDTA is controlled and operated by the following registers. Table 12-6 WDTA Register Overview Register Name Symbol Address...
Page 395 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) 12.4.2 WDTA Registers Details WDTA Enable Register (WDTAnWDTE) This register is the WDTA start control and trigger register. WDTA trigger Writing AC to this register restarts the counter. Refer to Section 12.3.2, WDTA Trigger, for details.
Page 396 V850E2/PG4-L Section 12 Window Watchdog Timer A (WDTA) WDTA Mode Register (WDTAnMD) This register specifies the overflow time, the 75% interrupt output mode, the error mode, and the window-open period. It can be updated only once after reset release and before the first trigger. The updated value is effective after the next WDTA trigger.
Page 397 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Section 13 Timer Array Unit B (TAUB) This section contains a generic description of the Timer Array Unit B (TAUB). The first section describes all V850E2/PG4-L specific properties, such as instances, register base addresses, input/output signal names, etc.The subsequent sections describe the features that apply to all implementations.
Page 398 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Interrupts and The Timer Array Unit B can generate the following interrupt and DMA request. Table 13-4 TAUBn Interrupt and DMA Requests TAUBn Signals Function Connected to TAUB0: INTTAUB0I0 Channel0 interrupt Interrupt controller INTTAUB0I0 DMA controller trigger 27 INTTAUB0I1 Channel1 interrupt...
Page 399 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) I/O signals The I/O signals of the Timer Array Unit B are listed in the table below. Table 13-6 TAUBn I/O Signal TAUB Signal Function Connected to TAUB0TTIN0 to Channel 0 to 15 input Port TAUB0I0 to TAUB0I15 TAUB0TTIN15 TAUB0TTOUT0 to...
Page 400 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.2 Functional Overview Features summary TAUB has the following functions: • 16 channels • 16-bit counter and 16-bit data register per channel • Independent channel operation • Synchronous channel operation (master and slave operations) •...
Page 401 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.2.1 Terms In this section, the following terms are used. • Independent/synchronous channel operation Independent or synchronous channel operation describes the dependency of channels on each other: – If a channel operates independent of all other channels, this is called independent channel operation.
Page 402 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.3 Functional Description The Timer Array Unit B performs various count or timer operations and outputs a signal which depends on the result of the operation. It contains one prescaler block for count clock generation and 16 channels, each equipped with a 16 bit counter TAUBnCNTm and a 16-bit data register TAUBnCDRm to hold the start or compare value of the counter.
Page 403 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Trigger selector Depending on the selected operating mode, the counter starts automatically when it is enabled (TAUBnTE.TAUBnTEm = 1), or it waits for an external start trigger signal. Any of the following signals can be used as a start trigger. •...
Page 404 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.3.1 Functional List of Timer Operations This timer provides the following functions by operating each channel independently or by combining multiple channels. Table 13-7 Functional List of TAUB Operations Function of Independent Operation Function of Synchronous Operation Independent channel operation functions Synchronous channel operation functions...
Page 405 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.4 General Operating Procedures The following lists the general operation procedures for the TAUBn. After reset release, the operation of each channel is stopped. Clock supply is started and writing to each register is enabled. The control register of TAUBnTTOUTm is also initialized and outputs a low level.
Page 406 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.5 Operation Modes The TAUB contains 12 operating modes. One operating mode can be set for each channel, which is specified using the TAUBnCMORm.TAUBnMD[4:0] bits. Note Some of the registers and bits are fixed and some are user-selectable depending on the operation function.
Page 407 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.6 Concepts of Synchronous Channel Operation In synchronous channel operation, multiple channels depend on each other, or are affected by changes in another channel. Therefore, several rules apply for the use of synchronous channel functions. These rules are detailed in Section 13.6.1, Rules.
Page 408 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The basic concepts of master and slave usage and the count clocks are illustrated in the following figure. TAUBn Channel group 1 (operated by CK0) CH0: Master CH1: Slave A channel with an independent operation CH2: Slave function can also be set between channel groups.
Page 409 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.6.2 Simultaneous Start and Stop of Synchronous Channel Counters Channels that are operated synchronously can be started and stopped simultaneously within the same unit and between the units. Simultaneous start and stop within the same unit •...
Page 410 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.7 Simultaneous Rewrite 13.7.1 Overview Simultaneous rewrite describes the ability to change the compare/start value and the output logic of multiple channels at the same time. The corresponding data registers and control registers (TAUBnCDRm and TAUBnTOLm) can nevertheless be written at any time.
Page 411 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-9 Simultaneous Rewrite and Trigger Timing Function Simultaneous rewrite trigger generating function type 1 PWM output function One-shot pulse output function Delay pulse output function Triangle PWM output function Triangle PWM output function with dead time AD conversion trigger output function type 1 AD conversion trigger output function type 2 Note X: available, Space: not available...
Page 412 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.7.2 How to Control Simultaneous Rewrite The following figure shows the general procedure for simultaneous rewrite. The three main blocks (initial settings, start counter and count operation, and simultaneous rewrite) are explained afterwards. TAUBnRDE.
Page 413 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Initial settings • To enable simultaneous rewrite in channel m, set TAUBnRDE.TAUBnRDEm • To select the type of simultaneous rewrite, set TAUBnRDM.TAUBnRDMm and TAUBnRDS.TAUBnRDSm according to the values listed in Table 13-8, Simultaneous Rewrite Methods and Trigger Timing.
Page 414 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.7.3 Other General Rules of Simultaneous Rewrite The following rules also apply: • TAUBnRDE.TAUBnRDEm, TAUBnRDS.TAUBnRDSm, TAUBnRDM.TAUBnRDMm, and TAUBnRDC.TAUBnRDCm cannot be changed while the counter is in operation (TAUBnTE.TAUBnTEm = 1). • TAUBnTOL.TAUBnTOLm can only be rewritten during operation with PWM output function or triangle PWM output function.
Page 415 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.7.4 Type of Simultaneous Rewrite In the following section, the three simultaneous rewrite methods are explained using timing diagrams. Simultaneous rewrite when the master channel starts/restarts to count (method A) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNT0 INTTAUBnI0 TAUBnCNT1...
Page 416 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Description: 1. When TAUBnTS.TAUBnTSm = 1 is set, the value of TAUBnCDRm is copied to the TAUBnCDRm buffer and the value of TAUBnTOL.TAUBnTOLm is copied to the TAUBnTOL.TAUBnTOLm buffer. 2. The TAUBnCDRm and TAUBnTOL.TAUBnTOLm registers can be written at any time.
Page 417 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite at the peak of a triangular cycle of master channel (method B) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNT0 INTTAUBnI0 TAUBnCNT1 0001 INTTAUBnI1 TAUBnTTOUT1 TAUBnTOL.TAUBnTOL1 TAUBnTOL.TAUBnTOL1 buf TAUBnCDR0 TAUBnCDR0 buf TAUBnCDR1 TAUBnCDR1 buf TAUBnRDT.TAUBnRDTm TAUBnRSF.TAUBnRSFm <2>...
Page 418 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Description: 1. When TAUBTS.TAUBnTSm = 1 is set, the value of TAUBnCDRm is copied to the TAUBnCDRm buffer. 2. The TAUBnCDRm and TAUBnTOL registers can be written at any time. 3. Simultaneous rewrite does not occur because it is disabled (TAUBnRSF.TAUBnRSFm = 0).
Page 419 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite when INTTAUBnIm is generated on an upper channel specified by TAUBnRDC.TAUBnRDCm (method C1) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNT1 INTTAUBnI1 TAUBnCNT2 INTTAUBnI2 TAUBnCNT3 INTTAUBnI3 TAUBnCDR1 TAUBnCDR1 buf TAUBnCDR2 TAUBnCDR2 buf TAUBnCDR3 TAUBnCDR3 buf TAUBnRDT.TAUBnRDTm TAUBnRSF.TAUBnRSFm <2>...
Page 420 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Description: 1. When TAUBnTS.TAUBnTSm is set to 1, TAUBnCDRm value is copied to the TAUBnCDRm buffer. 2. The TAUBnCDRm register is always ready to write. 3. By setting the reload data trigger bit (TAUBnRDT.TAUBnRDTm) to 1, the status flag is set (TAUBnRSF.TAUBnRSFm = 1) to enable simultaneous rewrite.
Page 421 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.8 Channel Output Modes The output of the TAUBnTTOUTm pin can be controlled in two ways, the latter of which can be further split into individual modes. • By software (TAUBnTOE.TAUBnTOEm = 0) When controlled by software, the value written in the output register bit (TAUBnTO.TAUBnTOm) is sent out of the output pin (TAUBnTTOUTm).
Page 422 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The various channel output modes and the channel output control bits are listed in the following table. Table 13-10 Channel Output Modes TAUBn TAUBn TAUBn TAUBn TOE. TOM. TOC. TDE. TAUBn TAUBn TAUBn TAUBn Channel Output Modes...
Page 423 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.8.1 General Procedures for Specifying a Channel Output Mode This section describes the general procedures for specifying a TAUBnTTOUTm channel output mode. The prerequisite is that timer output operation is disabled (TAUBnTOE.TAUBnTOEm = 0). 1.
Page 424 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.8.2 Channel Output Modes Controlled Independently by TAUBn Signals This section lists the channel output modes that are controlled independently by TAUBn signals. The control bits used to specify a mode are listed in Table 13-10, Channel Output Modes.
Page 425 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.8.3 Channel Output Modes Controlled Synchronously by TAUBn Signals This section lists the channel output modes that are controlled synchronously by TAUBn signals. The control bits used to specify a mode are listed in Table 13-10, Channel Output Modes.
Page 426 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Synchronous channel output mode 2 with dead time output In this output mode, a dead time delay is added to TAUBnTTOUTm. The set/ reset conditions are shown in the following figure. Set/reset conditions Duty (INTTAUBnlm for even slave channel)
Page 427 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.9 Start Timing in Each Operating Modes This section describes the timing at which the counter starts after TAUBnTS.TAUBnTSm is set to 1 in each operating mode. In all modes, the value of data register (TAUBnCDRm register) and whether or not an interrupt occurs depends on mode and register settings.
Page 428 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.9.2 Event Mode The value of data register (TAUBnCDRm register) is loaded as soon as TAUBnTS.TAUBnTSm is set to 1. The counter also starts immediately. The value of data register (TAUBnCDRm register) increments with subsequent count clocks.
Page 429 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.10 TAUBnTTOUTm Output and INTTAUBnIm Generation when Counter Starts or Restarts (TAUBnMD0 bit) When the counter starts, it is possible to specify whether an INTTAUBnIm is to be generated using the TAUBnCMORm.TAUBnMD0 bit. The effect of the bit depends on the selected mode, as shown in the following table.
Page 430 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCNTm TAUBnTE.TAUBnTEm INTTAUBnIm TAUBnTTOUTm When TAUBnCMORm.TAUBnMD0 is set to 0, INTTAUBnIm is not generated Count operation start when the counter starts. Figure 13-15 INTTAUBnIm Not Generated When Counter Starts R01UH0336EJ0102 Rev.1.02 Page 430 of 1538 Jul 17, 2014...
Page 431 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.11 TAUBnTTINm Edge Detection Edge detection is based on the operation clock. This means that an edge can only be detected at the next rising edge of the operation clock. This can lead to a maximum delay of one operation clock cycle.
Page 432 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.12 Independent Channel Operation Functions The following sections list the independent channel operation functions provided by the TAUB. For a general overview of independent channel operation, see Section 13.3, Functional Description. 13.13 Independent Channel Interrupt Functions This section describes functions that generate interrupts at regular intervals or with a specified delay.
Page 433 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.13.1 Interval Timer Function Overview Summary This function is used as a reference timer for generating timer interrupts (INTTAUBnIm) at regular intervals. When an interrupt is generated, the TAUBnTTOUTm signal toggles, resulting in a square wave. Prerequisites •...
Page 434 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Trigger from upper channel Interval timer mode Start trigger from master Simultaneous rewrite INT from master TAUBnTRO. Trigger from INT from upper channe TAUBnTROm upper channel CK3-0 Count clock TAUBnTO.
Page 435 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUB TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] nMD0 Table 13-12 TAUBnCMORm Settings for Interval Timer Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 436 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode Table 13-14 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables independent channel output mode. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 0: Operating mode 1 (Toggle mode if TAUBnTOM.TAUBnTOMm = 0) TAUBnTOL.TAUBnTOLm 0: Positive logic...
Page 437 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for interval timer function Table 13-16 Operating Procedure for Interval Timer Function Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm registers Channel operation is stopped. as described in Table 13-12, TAUBnCMORm Settings for Interval Timer Function, and Table 13- 13, TAUBnCMURm Settings for Interval Timer Function.
Page 438 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams TAUBnCDRm = 0000 , count clock = PCLK/2 PCLK Count clock TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm Count clock cycle Figure 13-19 TAUBnCDRm = 0000 , Count Clock = PCLK/2 •...
Page 439 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operation stop and restart Operation start Operation stop Operation start TAUBnCNTm (Counter) TAUBnCDRm TAUBnTTOUTm INTTAUBnIm a + 1 a + 1 b + 1 b + 1 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm Figure 13-21 Operation Stop and Restart (TAUBnCMORm.TAUBnMD0 = 1) •...
Page 440 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.13.2 TAUBnTTINm Input Interval Timer Function Overview Summary This function is used as a reference timer for generating timer interrupts (INTTAUBnIm) at regular intervals or when a valid TAUBnTTINm input edge is detected.
Page 441 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Trigger from upper channel Interval timer mode Start trigger from master Simultaneous rewrite INT from master Trigger from TAUBnTRO. INT from upper channe upper channe TAUBnTROm CK3-0 Count clock TAUBnTO.
Page 442 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUB TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] nMD0 Table 13-17 TAUBnCMORm Settings for TAUBnTTINm Input Interval Timer Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 443 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode Table 13-19 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables independent channel output mode. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 0: Operating mode = 1 (Toggle mode if TAUBnTOM.TAUBnTOMm = 0) TAUBnTOL.TAUBnTOLm 0: Positive logic...
Page 444 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for TAUBnTTINm input interval timer function Table 13-21 Operating Procedure for TAUBnTTINm Input Interval Timer Function Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm registers Channel operation is stopped. as described in Table 13-17, TAUBnCMORm Settings for TAUBnTTINm Input Interval Timer Function, and Table 13-18, TAUBnCMURm Settings for TAUBnTTINm Input Interval Timer...
Page 445 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagram The timing diagrams in Section 13.13.1, Interval Timer Function. The counter can also be restarted by a valid TAUBnTTINm input edge without using this function. TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm 0000 TAUBnCDRm INTTAUBnIm...
Page 446 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.13.3 One-Pulse Output Function Overview Summary This function generates an interrupt (INTTAUBnIm) when a valid TAUBnTTINm input edge is detected and at a defined interval afterward. TAUBnTTINm input signal pulses that occur within the defined interval are ignored.
Page 447 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram TAUBnTRO. TAUBnTROm Count Clock TAUBn TAUBnTO. TAUBnTTOUTm TAUBnTOm CNTm Trigger from Lower TAUBnTS.TAUBnTSm TAUBnTTINm TAUBn INTm Start&Capture INTTAUBnIm CDRm Trigger Figure 13-26 Block Diagram of One-Pulse Output Function The following settings apply to the general timing diagram.
Page 448 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUB TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] nMD0 Table 13-22 TAUBnCMORm Settings for One-Pulse Output Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 449 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode Table 13-24 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables independent channel output mode controlled by software. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 1: Independent channel output mode TAUBnTOL.TAUBnTOLm...
Page 450 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for one-pulse output function Table 13-26 Operating Procedure for One-Pulse Output Function Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm registers Channel operation is stopped. as described in Table 13-22, TAUBnCMORm Settings for One-Pulse Output Function, and Table 13-23, TAUBnCMURm Settings for One-Pulse Output Function.
Page 451 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.14 Independent Channel Signal Measurement Functions This section describes functions that measure the widths of an individual TAUBnTTINm pulse or the total width of successive TAUBnTTINm pulses. It also describes functions that measure the interval of the signal or that compare the width of a pulse with a reference value.
Page 452 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.14.1 TAUBnTTINm Input Pulse Interval Measurement Function Overview Summary This function captures the count value and uses this value and the overflow bit TAUBnCSRm.TAUBnOVF to measure the interval of the TAUBnTTINm input signal Prerequisites •...
Page 453 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Conditions If the TAUBnCMORm.TAUBnMD0 bit is set to 0, the first interrupt after a start or restart is not generated. For details, see Section 13.10, TAUBnTTOUTm Output and INTTAUBnIm Generation when Counter Starts or Restarts (TAUBnMD0 bit).
Page 454 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • INTTAUBnIm not generated at the beginning of operation (TAUBnCMORm.TAUBnMD0 = 0) • Falling edge detection (TAUBnCMURm.TAUBnTIS[1:0] = 00 • When a valid TAUBnTTINm input is detected after an overflow, TAUBnCDRm is changed and TAUBnCSRm.TAUBnOVF is set to 1 (TAUBnCMORm.TAUBnCOS[1:0]= 00 TAUBnTS.TAUBnTSm...
Page 455 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-28 TAUBnCMORm Settings for TAUBnTTINm Input Pulse Interval Measurement Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 456 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode TAUBnTOE.TAUBnTOEm is set to 0 because the channel output mode is not used with this function. However, this mode can be used in independent channel output mode controlled by software. Simultaneous rewrite The simultaneous rewrite registers (TAUBnRDE, TAUBnRDS, TAUBnRDM, and TAUBnRDC) cannot be used with the TAUBnTTINm input pulse interval...
Page 457 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for TAUBnTTINm input pulse interval measurement function Table 13-31 Operating Procedure for TAUBnTTINm Input Pulse Interval Measurement Function Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm Channel operation is stopped. registers as described in Table 13-28, TAUBnCMORm Settings for TAUBnTTINm Input Pulse Interval Measurement Function, and Table 13-29,...
Page 458 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams: overflow operation TAUBnCMORm.TAUBnCOS[1:0] = 00 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm FFFF TAUBnCNTm 0000 0000 TAUBnCDRm INTTAUBnIm TAUBnCSRm.TAUBnOVF Figure 13-30 TAUBnCMORm.TAUBnCOS[1:0] = 00 , TAUBnCMORm.TAUBnMD0 = 0, TAUBnCMURm.TAUBnTIS[1:0] = 00 • When an overflow occurs, the value of TAUBnCDRm remains unchanged and TAUBnCSRm.TAUBnOVF remains = 0.
Page 459 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCMORm.TAUBnCOS[1:0] = 10 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm FFFF TAUBnCNTm 0000 0000 FFFF TAUBnCDRm INTTAUBnIm TAUBnCSRm.TAUBnOVF Figure 13-32 TAUBnCMORm.TAUBnCOS[1:0] = 10 , TAUBnCMORm.TAUBnMD0 = 0, TAUBnCMURm.TAUBnTIS[1:0] = 00 • When an overflow occurs, TAUBnCDRm is set to FFFF TAUBnCSRm.TAUBnOVF remains = 0.
Page 460 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.14.2 TAUBnTTINm Input Signal Width Measurement Function Overview Summary This function measures the width of a TAUBnTTINm input signal. Prerequisites • The operating mode should be set to capture and one-count mode. See Table 13-33, TAUBnCMORm Settings for TAUBnTTINm Input Signal Width Measurement Function.
Page 461 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Equations TAUBnTTINm input signal width = count clock cycle × [(TAUBnCSRm.TAUBnOVF × (FFFF + 1)) + TAUBnCDRm capture value + 1] Block diagram and general timing diagram Capture and Trigger from upper channel one-count mode Start trigger from master Simultaneous rewrite...
Page 462 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-33 TAUBnCMORm Settings for TAUBnTTINm Input Signal Width Measurement Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 463 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode TAUBnTOE.TAUBnTOEm is set to 0 because the channel output mode is not used with this function. However, this mode can be used in independent channel output mode controlled by software. Simultaneous rewrite The simultaneous rewrite registers (TAUBnRDE, TAUBnRDS, TAUBnRDM, and TAUBnRDC) cannot be used with the TAUBnTTINm input signal width...
Page 464 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for TAUBnTTINm input signal width measurement function Table 13-36 Operating Procedure for TAUBnTTINm Input Signal Width Measurement Function Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm Channel operation is stopped. registers as described in Table 13-33, TAUBnCMORm Settings for TAUBnTTINm Input Signal Width Measurement Function,and Table 13-34,...
Page 465 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams: overflow operation TAUBnCMORm.TAUBnCOS[1:0] = 00 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm FFFF TAUBnCNTm 0000 0000 TAUBnCDRm INTTAUBnIm TAUBnCSRm.TAUBnOVF Figure 13-36 TAUBnCMORm.TAUBnCOS[1:0] = 00 , TAUBnCMORm.TAUBnMD0 = 0, TAUBnCMURm.TAUBnTIS[1:0] = 11 • When an overflow occurs, the value of TAUBnCDRm remains unchanged and TAUBnCSRm.TAUBnOVF remains = 0.
Page 466 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCMORm.TAUBnCOS[1:0] = 10 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm FFFF TAUBnCNTm 0000 0000 FFFF TAUBnCDRm INTTAUBnIm TAUBnCSRm.TAUBnOVF Figure 13-38 TAUBnCMORm.TAUBnCOS[1:0] = 10 , TAUBnCMORm.TAUBnMD0 = 0, TAUBnCMURm.TAUBnTIS[1:0] = 11 • When an overflow occurs, TAUBnCDRm is set to FFFF TAUBnCSRm.TAUBnOVF remains = 0.
Page 467 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCMORm.TAUBnCOS[1:0] = 11 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm FFFF TAUBnCNTm 0000 TAUBnCDRm 0000 FFFF INTTAUBnIm TAUBnCSRm.TAUBnOVF Figure 13-39 TAUBnCMORm.TAUBnCOS[1:0] = 11 , TAUBnCMORm.TAUBnMD0 = 0, TAUBnCMURm.TAUBnTIS[1:0] = 11 • When an overflow occurs, TAUBnCDRm is set to FFFF TAUBnCSRm.TAUBnOVF is set to 1.
Page 468 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.14.3 TAUBnTTINm Input Period Count Detection Function Overview Summary This function measures the cumulative width of a TAUBnTTINm input signal. Prerequisites • The operating mode should be set to capture and gate count mode. (See Table 13-37, TAUBnCMORm Settings for TAUBnTTINm Input Period Count Detection Function.) •...
Page 469 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master TAUBnTRO. Trigger from TAUBnTROm INT from upper channe upper channel CK3-0 Count cl o ck TAUBnTO.
Page 470 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-37 TAUBnCMORm Settings for TAUBnTTINm Input Period Count Detection Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 471 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite Simultaneous rewrite registers (TAUBnRDE, TAUBnRDS, TAUBnRDM, and TAUBnRDC) cannot be used with this function. Therefore, these registers should be set to 0. Table 13-39 Simultaneous Rewrite Settings for TAUBnTTINm Input Period Count Detection Function Bit Name Setting...
Page 472 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams Operation stop and restart TAUBnTS.TAUBnTSm TAUBnTT.TAUBnTTm TAUBnTE.TAUBnTEm TAUBnTTINm FFFF TAUBnCNTm 0000 TAUBnCDRm INTTAUBnIm Figure 13-42 Operation Stop and Restart (TAUBnCMURm.TAUBnTIS[1:0] = 11 • The counter can be stopped by setting TAUBnTT.TAUBnTTm to 1. This sets TAUBnTE.TAUBnTEm to 0.
Page 473 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.14.4 TAUBnTTINm Input Pulse Interval Judgment Function Overview Summary This function outputs the result of a comparison between the count value (TAUBnCNTm) and the value in the channel data register (TAUBnCDRm) when a TAUBnTTINm input pulse occurs. An interrupt signal INTTAUBnIm is generated if the result of the comparison is true.
Page 474 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Judge mode Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master TAUBnTRO. Tri g ger from INT from upper channe TAUBnTROm upper channel CK3-0 Count clock TAUBnTO.
Page 475 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-41 TAUBnCMORm Settings for TAUBnTTINm Input Pulse Interval Judgment Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 476 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite Simultaneous rewrite registers (TAUBnRDE, TAUBnRDS, TAUBnRDM, and TAUBnRDC) cannot be used with this function. Therefore, these registers should be set to 0. Table 13-43 Simultaneous Rewrite Settings for TAUBnTTINm Input Pulse Interval Judgment Function Bit Name Setting...
Page 477 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for TAUBnTTINm input pulse interval judgment function Table 13-44 Operating Procedure for TAUBnTTINm Input Pulse Interval Judgment Function Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm Channel operation is stopped. registers as described in Table 13-41, TAUBnCMORm Settings for TAUBnTTINm Input Pulse Interval Judgment Function, and Table 13-42,...
Page 478 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.14.5 TAUBnTTINm Input Signal Width Judgment Function Overview Summary This function outputs the result of a comparison between the count value (TAUBnCNTm) and the value in the channel data register (TAUBnCDRm) when a valid stop edge of a TAUBnTTINm input signal is detected. An interrupt signal INTTAUBnIm is generated if the result of the comparison is true.
Page 479 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Capture and Trigger from upper channel one-count mode Start trigger from master Simultaneous rewrite INT from master TAUBnTRO. Trigger from INT from upper channe TAUBnTROm upper channel CK3-0 Count clock TAUBnTO.
Page 480 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-45 TAUBnCMORm Settings for TAUBnTTINm Input Signal Width Judgment Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 481 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite Simultaneous rewrite registers (TAUBnRDE, TAUBnRDS, TAUBnRDM, and TAUBnRDC) cannot be used with this function. Therefore, these registers should be set to 0. Table 13-47 Simultaneous Rewrite Settings for TAUBnTTINm Input Signal Width Judgment Function Bit Name Setting...
Page 482 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for TAUBnTTINm input signal width judgment function Table 13-48 Operating Procedure for TAUBnTTINm Input Signal Width Judgment Function Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm Channel operation is stopped. registers as described in Table 13-45, TAUBnCMORm Settings for TAUBnTTINm Input Signal Width Judgment Function, and Table 13-46,...
Page 483 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.15 Independent Channel Simultaneous Rewrite Functions This section describes functions that carry out simultaneous rewrite. • Section 13.15.1, Simultaneous Rewrite Trigger Generation Function Type 1 R01UH0336EJ0102 Rev.1.02 Page 483 of 1538 Jul 17, 2014...
Page 484 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.15.1 Simultaneous Rewrite Trigger Generation Function Type 1 Overview Summary This function generates an interrupt on a specific channel that can be used by lower channels as a simultaneous rewrite trigger. The interrupt is generated at regular intervals.
Page 485 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Equations Simultaneous rewrite trigger generation cycle = count clock cycle x (TAUBnCDRm + 1) To control simultaneous rewrite, the following condition should be satisfied: [PWM] TAUBnCDRm = [(value of TAUBnCDRm of master channel subject to simultaneous rewrite + 1) ×...
Page 486 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • INTTAUBnIm is generated at the beginning of operation. (TAUBnCMORm.TAUBnMD0 = 1) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNT1 INTTAUBnI1 TAUBnCNT2 INTTAUBnI2 TAUBnCDR1 TAUBnCDR1 buf TAUBnCDR2 TAUBnCDR2 buf TAUBnRDT.TAUBnRDTm TAUBnRSF.TAUBnRSFm <6>...
Page 487 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for upper channels TAUBnCMORm for upper channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUB TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] nMD0 Table 13-49 TAUBnCMORm Settings for Simultaneous Rewrite Trigger Generation Function Type 1 Bit Name Setting TAUBnCKS[1:0]...
Page 488 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite for upper channels Table 13-51 Simultaneous Rewrite Settings for Simultaneous Rewrite Trigger Generation Function Type 1 Bit Name Setting TAUBnRDE.TAUBnRDEm 1: Enables simultaneous rewrite. TAUBnRDS.TAUBnRDSm 1: Selects one of upper channels as simultaneous rewrite control channel.
Page 489 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for simultaneous rewrite trigger generation function type 1 Table 13-53 Operating Procedure for Simultaneous Rewrite Trigger Generation Function Type 1 Operation TAUBn Status Set TAUBnCMORm and TAUBnCMURm Channel operation is stopped. registers for the upper channel as described in Table 13-49, TAUBnCMORm Settings for Simultaneous Rewrite Trigger Generation...
Page 490 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.16 Other Independent Channel Functions This section describes a function that generates an interrupt when a certain number of TAUBnTTINm pulses has occurred, a function that divides the frequency of TAUBnTTINm, and a function that measures the duration between the function start and a TAUBnTTINm input signal.
Page 491 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.16.1 External Event Count Function Overview Summary This function is used as an event timer. It generates an interrupt (INTTAUBnIm) when a specific number of TAUBnTTINm input pulses has occurred. Prerequisites • The operation mode must be set to event count mode. (Refer to Table 13- 54, TAUBnCMORm Settings for External Event Count Function.) •...
Page 492 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram TAUBnTO. TAUBnTOm TAUBn TAUBnTRO. TAUBnTTOUTm TAUBnTROm CNTm Trigger from Lower TAUBnTE.TAUBnTEm TAUBnTTINm TAUBn INTm INTTAUBnIm CDRm Figure 13-49 Block Diagram for External Event Count Function The following settings apply to the general timing diagram. •...
Page 493 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUBn TAUBnSTS TAUBnCOS TAUBnMD TAUBnM [1:0] [1:0] [2:0] [1:0] [4:1] Table 13-54 TAUBnCMORm Settings for External Event Count Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 494 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite The simultaneous rewrite registers (TAUBnRDE, TAUBnRDS, TAUBnRDM, and TAUBnRDC) cannot be used with the external event count function. Therefore, these registers should be set to 0. Table 13-56 Simultaneous Rewrite Settings for External Event Count Function Bit Name Setting TAUBnRDE.TAUBnRDEm...
Page 495 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (5)Operating procedure for external event count function Table 13-57Operating Procedure for External Event Count Function Operation Status of TAUBn Set the TAUBnCMORm register and Channel operation is stopped. TAUBnCMURm registers as described in Table 13-54, TAUBnCMORm Settings for External Event Count Function and Table 13- 55, TAUBnCMURm Settings for External...
Page 496 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (6)Specific timing diagrams TAUBnCDRm = 0000 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm 0000 H TAUBnCDRm 0000 H INTTAUBnIm Figure 13-51 TAUBnCDRm = 0000 , TAUBnCMURm.TAUBnTIS[1:0] = 01 • If 0000 = TAUBnCDRm, 0000 is loaded into TAUBnCNTm every time a valid TAUBnTTINm input edge is detected.
Page 497 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Forced restart Operation starts Forced restart TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm 0000 H 0003 H 0004 H TAUBnCDRm INTTAUBnIm 4 events 5 events Figure 13-53 Forced Restart, TAUBnCMURm.TAUBnTIS[1:0] = 01 A forced restart applies a change to TAUBnCDRm immediately. •...
Page 498 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.16.2Clock Divide Function (1)Overview Summary This function is used as a frequency divider. The frequency of the input signal TAUBnTTINm is divided by a factor related to TAUBnCDRm, and the resulting signal is output to TAUBnTTOUTm. Prerequisites •...
Page 499 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (3)Block diagram and general timing diagram TAUBnTRO. TAUBnTROm Count Clock TAUBn TAUBnTO. TAUBnTTOUTm TAUBnTOm CNTm Trigger TAUBnTS.TAUBnTSm from Lower Edge TAUBnTTINm TAUBn Start&Capture INTn INTTAUBnIm CDRm Trigger Figure 13-54 Block Diagram for Clock Divide Function The following settings apply to the general timing diagram: •...
Page 500 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (4)Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnSTS TAUBnCOS TAUBnMD TAUB [1:0] [1:0] nMAS [2:0] [1:0] [4:1] nMD0 Table 13-58 TAUBnCMORm Settings for Clock Divide Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 501 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode Table 13-60 Control Bit Settings for Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Eables independent channel output mode controlled by software. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 0: Operation mode 1 (Toggle mode if TAUBnTOM.TAUBnTOMm = 0)
Page 502 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (5)Operating procedure for clock divide function Table 13-62 Operating Procedure for Clock Divide Function Operation Status of TAUBn Set the TAUBnCMORm register and Channel operation is stopped. TAUBnCMURm registers as described in Table 13-58, TAUBnCMORm Settings for Clock Divide Function and Table 13-59, TAUBnCMURm Settings for Clock Divide...
Page 503 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (6)Specific timing diagrams TAUBnCDRm = 0000 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm 0000 H TAUBnCDRm 0000 H TAUBnTTOUTm INTTAUBnIm Divided by 2 Figure 13-56 TAUBnCDRm = 0000 , TAUBnCMORm.TAUBnMD0 = 1, TAUBnCMURm.TAUBnTIS[1:0] = 01 •...
Page 504 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Forced restart TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm TAUBnCDRm TAUBnTTOUTm INTTAUBnIm Figure 13-58 Forced restart, TAUBnCMORm.TAUBnMD0 = 1, TAUBnCMURm.TAUBnTIS[1:0] = 01 To reset the value of TAUBnTTOUTm: • The counter can be forcibly restarted (without stopping it first) by setting TAUBnTS.TAUBnTSTSm = 1 during operation.
Page 505 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.16.3 TAUBnTTINm Input Position Detection Function (1)Overview Summary This function measures the duration between the function start and a TAUBnTTINm input signal. Prerequisites • The operation mode must be set to count capture mode. Refer to Table 13- 63, TAUBnCMORm Settings for TAUBnTTINm Input Position Detection Function.
Page 506 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram TAUBnTRO. TAUBnTROm Count Clock TAUBn TAUBnTO. TAUBnTTOUTm TAUBnTOm CNTm Trigger from Lower TAUBnTS.TAUBnTSm TAUBnTTINm TAUBn INTm INTTAUBnIm Start&Capture CDRm Trigger Figure 13-59 Block Diagram for TAUBnTTINm Input Position Detection Function The following settings apply to the general timing diagram: •...
Page 507 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings TAUBnCMORm TAUBnCKS TAUBnCCS TAUB TAUBnSTS TAUBnCOS TAUBnMD TAUB [1:0] [1:0] nMAS [2:0] [1:0] [4:1] nMD0 Table 13-63 TAUBnCMORm Settings for TAUBnTTINm Input Position Detection Function Bit Name Setting TAUBnCKS[1:0] 00: Operation clock = CK0 01: Operation clock = CK1 10: Operation clock = CK2 11: Operation clock = CK3...
Page 508 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite The simultaneous rewrite registers (TAUBnRDE, TAUBnRDS, TAUBnRDM, and TAUBnRDC) cannot be used with the TAUBnTTINm input position detection function. Therefore, these registers should be set to 0. Table 13-65 Simultaneous Rewrite Settings for TAUBnTTINm Input Position Detection Function Bit name Setting...
Page 509 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for TAUBnTTINm Input Position Detection Function Table 13-66 Operating Procedure for TAUBnTTINm Input Position Detection Function Operation Status of TAUBn Set the TAUBnCMORm register and Channel operation is stopped. TAUBnCMURm registers as described in Table 13-63, TAUBnCMORm Settings for TAUBnTTINm Input Position Detection Function and Table 13-64, TAUBnCMURm...
Page 510 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams Operation Stop and Restart Operation starts Operation starts Operation stops TAUBnTS.TAUBnTSm TAUBnTT.TAUBnTTm TAUBnTE.TAUBnTEm TAUBnTTINm FFFF H TAUBnCNTm 0000 H TAUBnCDRm INTTAUBnIm Figure 13-61 Operation Stop and Restart, TAUBnCMORm.TAUBnMD0 = 0, TAUBnCMURm.TAUBnTIS[1:0] = 00 •...
Page 511 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.17 Synchronous Channel Operation Functions This section lists all the synchronous channel operation functions provided by the timer array unit A. For a general overview of synchronous channel operation, see Section 13.3, Functional Description. R01UH0336EJ0102 Rev.1.02 Page 511 of 1538 Jul 17, 2014...
Page 512 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.18 Synchronous PWM Signal Functions Triggered at Regular Intervals This section describes functions that generate PWM signals at regular intervals. • Section 13.18.1, PWM Output Function • Section 13.18.2, Delay Pulse Output Function •...
Page 513 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.18.1 PWM Output Function Overview Summary This function generates multiple PWM outputs by using a master and multiple slave channels. It enables the pulse cycle (frequency) and the duty cycle of the TAUBnTTOUTm to be set.
Page 514 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Equations Pulse cycle = (TAUBnCDRm (master) + 1) × count clock cycle Duty cycle [%] = (TAUBnCDRm (slave) / (TAUBnCDRm (master) + 1) × 100 – Duty cycle = 0% TAUBnCDRm (slave) = 0000 –...
Page 515 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • Slave channels: Positive logic (TAUBnTOL.TAUBnTOLm = 0) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm Master Slave TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm a + 1 a + 1...
Page 516 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for master channels TAUBnCMORm for master channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-67 TAUBnCMORm Settings for Master Channels of PWM Output Function Bit Name Setting TAUBnCKS[1:0] 00: Prescaler output CK0...
Page 517 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for master channels The channel output mode is not used with this function. However, this mode can be used with another function or in independent channel output mode controlled by software. Simultaneous rewrite for master channels Both master and slave channels should have the same simultaneous rewrite settings.
Page 518 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channels TAUBnCMORm for slave channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-70 TAUBnCMORm Settings for Slave Channels of PWM Output Function Bit Name Setting TAUBnCKS[1:0] 00: Prescaler output CK0...
Page 519 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for slave channels Table 13-72 Control Bit Settings in Synchronous Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 1: Synchronous channel operation TAUBnTOC.TAUBnTOCm 0: Operating mode 1 TAUBnTOL.TAUBnTOLm...
Page 520 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for PWM output function Table 13-74 Operating Procedure for PWM Output Function Operation TAUBn Status Master channels: Set TAUBnCMORm/ Channel operation is stopped. TAUBnCMURm register and the channel output mode as described in (4) Register settings for master channels.
Page 521 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams Duty cycle = 0% TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm INTTAUBnIm Master a + 1 a + 1 a + 1 Slave TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm Figure 13-64 TAUBnCDRm (Slave) = 0000 Positive Logic (TAUBnTOL.TAUBnTOLm (Slave) = 0)
Page 522 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Duty cycle = 100% TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm INTTAUBnIm Master a + 1 a + 1 a + 1 a + 1 Slave TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm TAUBnCDRm (Slave) ≥ TAUBnCDRm (Master) + 1 Figure 13-65 Positive Logic (TAUBnTOL.TAUBnTOLm (Slave) = 0) •...
Page 523 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operation stop and restart Operation start Operation start Operation stop TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm Master Slave TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm a + 1 a + 1 Figure 13-66 Operation Stop and Restart Positive Logic (TAUBnTOL.TAUBnTOLm (Slave) = 0)
Page 524 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.18.2 Delay Pulse Output Function Overview Summary This function outputs two signals. The pulse width and pulse cycle of the reference signal are defined using the master channel and slave channel 1. Slave channels 2 and 3 output the reference signal with a specified delay.
Page 525 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) – Slave channel 2: When the counter of slave channel 2 reaches 0000 and delay time has elapsed, INTTAUBnIm is generated. The counter is reset to FFFF waits for the next INTTAUBnlm of master channel. Generating INTTAUBnIm (slave channel 2) triggers the counter of slave channel 3.
Page 526 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Master Trigger from upper channel Interval timer mode Simultaneous rewrite Start trigger from master trigger from upper INT from master channels TAUBnTRO. INT from upper channe TAUBnTROm CK3-0 Count clock...
Page 527 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • All channels – INTTAUBnIm is generated at the beginning of operation. (TAUBnCMORm.TAUBnMD0 = 1) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm Master Slave 1 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm...
Page 528 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for master channels TAUBnCMORm for master channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-75 TAUBnCMORm Settings for Master Channels of the Delay Pulse Output Function Bit Name Setting...
Page 529 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Simultaneous rewrite for master channels Both master and slave channels should have the same simultaneous rewrite settings. Table 13-77 Simultaneous Rewrite Settings for Master Channels of Delay Pulse Output Function Bit Name Setting TAUBnRDE.TAUBnRDEm 1: Enables simultaneous rewrite.
Page 530 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channel 1 TAUBnCMORm for slave channel 1 TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-78 TAUBnCMORm Settings for Slave Channel 1 of Delay Pulse Output Function Bit Name Setting...
Page 531 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for slave channel 1 Table 13-80 Control Bit Settings for Slave Channel 1 in Synchronous Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 1: Synchronous channel operation TAUBnTOC.TAUBnTOCm...
Page 532 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channel 2 TAUBnCMORm for slave channel 2 TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-82 TAUBnCMORm Settings for Slave Channel 2 of Delay Pulse Output Function Bit Name Setting...
Page 533 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for slave channel 2 TAUBnTOE.TAUBnTOEm is set to 0 because channel output mode is not used with this function. However, this mode can be used with another function or in independent channel output mode controlled by software.
Page 534 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channel 3 TAUBnCMORm for slave channel 3 TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-85 TAUBnCMORm Settings for Slave Channel 3 of Delay Pulse Output Function Bit Name Setting...
Page 535 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for slave channel 3 Table 13-87 Control Bit Settings in Independent Channel Output Mode 2 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 1: Operating mode 2 TAUBnTOL.TAUBnTOLm...
Page 536 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for delay pulse output function Table 13-89 Operating Procedure for Delay Pulse Output Function (1/2) Operation TAUBn Status Master channels: Set TAUBnCMORm and Channel operation is stopped. TAUBnCMURm registers and the channel output mode as described in (3) Register settings for master channels.
Page 537 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-89 Operating Procedure for Delay Pulse Output Function (2/2) Operation TAUBn Status TAUBnTE.TAUBnTEm (master and slave channels) is set to 1 and the counters of master TAUBnTS.TAUBnTSm of master and slave channel and slave channels 1 and 2 start.
Page 538 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams Duty cycle (slave 3) = 100 % The following values apply to the figure below: • TAUBnCDRm (master) = 000A • TAUBnCDRm (slave 1) = 000B • TAUBnCDRm (slave 2) = 0000 •...
Page 539 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (b)TAUBnTTOUTm (slave 1) = TAUBnTTOUTm (slave 3) The following values apply to the figure below: • TAUBnCDRm (master) = 000A • TAUBnCDRm (slave 1) = 0005 • TAUBnCDRm (slave 2) = 0000 •...
Page 540 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.18.3 AD Conversion Trigger Output Function Type 1 Overview Summary This function is identical to Section 13.18.1, PWM Output Function, except that TAUBnTTOUTm is not output. This is achieved by setting the channel output mode for the slave to independent channel output mode controlled by software.
Page 541 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) General timing diagram The following settings apply to the general timing diagram. • Slave channels: Positive logic (TAUBnTOL.TAUBnTOLm = 0) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm a + 1 a + 1 b + 1 b + 1 Master...
Page 542 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.19 Synchronous PWM Signal Functions Triggered by an External Signal This section describes functions that generate PWM signals and which are triggered by an external signal. • Section 13.19.1, One-Shot Pulse Output Function R01UH0336EJ0102 Rev.1.02 Page 542 of 1538 Jul 17, 2014...
Page 543 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.19.1 One-Shot Pulse Output Function Overview Summary This function outputs a signal pulse with a specific pulse width and delay time (both defined relative to an external input signal pulse) by using a master and a slave channel.
Page 544 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Note 1. If a forced restart of the slave channel is executed during operation, the width of the output signal does not correspond to the value of TAUBnCDRm (slave). Note 2. TAUBnTTINm input signal is sampled at the frequency of a sampling clock set by the TAUBnCMORm.TAUBnCKS[1:0] bits.
Page 545 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Master Trigger from upper channel Start trigger from master Simultaneous rewrite One count mode INT from master trigger from upper TAUBnTRO. channels INT from upper channe TAUBnTROm CK3-0 Count cl o ck...
Page 546 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • Start trigger detection is disabled during counting (TAUBnCMORm.TAUBnMD0 = 0) • Detection of falling edge (TAUBnCMURm.TAUBnTIS[1:0] = 00 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm...
Page 547 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for master channels TAUBnCMORm for master channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-90 TAUBnCMORm Settings for Master Channels of One-Shot Pulse Output Function Bit Name Setting TAUBnCKS[1:0]...
Page 548 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for master channels TAUBnTOE.TAUBnTOEm is set to 0 because channel output mode is not used with this function. However, this mode can be used with another function or in independent channel output mode controlled by software.
Page 549 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channels TAUBnCMORm for slave channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-93 TAUBnCMORm Settings for Slave Channels of One-Shot Pulse Output Function Bit Name Setting TAUBnCKS[1:0]...
Page 550 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Output mode for slave channels Table 13-95 Control Bit Settings in Independent Channel Output Mode 2 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 1: Operating mode 2 TAUBnTOL.TAUBnTOLm 0: Positive logic...
Page 551 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for one-shot pulse output function Table 13-97 Operating Procedure for One-Shot Pulse Output Function Operation TAUBn Status Master channels: Set TAUBnCMORm/ Channel operation is stopped. TAUBnCMURm register and channel output mode as described in (3) Register settings for master channels.
Page 552 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams TAUBnCDRm (master) = 0000 The following settings apply to this diagram: • Start trigger detection disabled during counting (TAUBnCMORm.TAUBnMD0 = 0) • Falling edge detection (TAUBnCMURm.TAUBnTIS[1:0] = 00 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm...
Page 553 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCDRm (slave) = 0000 The following settings apply to this diagram: • Start trigger detection disabled during counting (TAUBnCMORm.TAUBnMD0 = 0) • Falling edge detection (TAUBnCMURm.TAUBnTIS[1:0] = 00 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm 0000 H TAUBnCDRm TAUBnTTOUTm...
Page 554 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCMORm.TAUBnMD0 = 1 The following settings apply to this diagram: • Start trigger detection enabled during counting (TAUBnCMORm.TAUBnMD0 = 1) • Falling edge detection (TAUBnCMURm.TAUBnTIS[1:0] = 00 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm TAUBnCNTm 0000 H TAUBnCDRm TAUBnTTOUTm INTTAUBnIm...
Page 555 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Restarting the master channel while the slave channel is counting The following settings apply to this diagram: • Start trigger detection disabled during counting (TAUBnCMORm.TAUBnMD0 = 0) • Falling edge detection (TAUBnCMURm.TAUBnTIS[1:0] = 00 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnTTINm...
Page 556 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.20 Synchronous Triangle PWM Functions This chapter describes functions that generate a triangle PWM output. • Section 13.20.1, Triangle PWM Output Function • Section 13.20.2, Triangle PWM Output Function with Dead Time •...
Page 557 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.20.1 Triangle PWM Output Function Overview Summary This function generates multiple triangle PWM outputs by using a master and one or more slave channels. It enables the pulse cycle (frequency) and the duty cycle of TAUBnTTOUTm to be set using the master and slave channels respectively.
Page 558 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) • Slave channels: The INTTAUBnIm of master channel triggers the counter of the slave channel: – If the slave counter is counting down, the count direction changes. – If the slave counter is counting up, TAUBnCDRm value is reloaded and the counter starts to count down.
Page 559 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Master Interval timer mode Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master TAUBnTRO. trigger from upper TAUBnTROm INT from upper channe channels CK3-0 Count clock...
Page 560 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • Master channel – INTTAUBnIm is generated at the beginning of operation. (TAUBnCMORm.TAUBnMD0 = 1) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm a + 1 a + 1 b + 1 b + 1...
Page 561 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for master channels TAUBnCMORm for master channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-98 TAUBnCMORm Settings for Master Channels of Triangle PWM Output Function Bit Name Setting TAUBnCKS[1:0]...
Page 562 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for master channels Table 13-100 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 0: Operating mode 1 (Toggle mode when TAUBnTOM.TAUBnTOMm = 0)
Page 563 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channels TAUBnCMORm for slave channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-102 TAUBnCMORm Settings for Slave Channels of Triangle PWM Output Function Bit Name Setting TAUBnCKS[1:0]...
Page 564 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for slave channels Table 13-104 Control Bit Settings in Synchronous Channel Output Mode 2 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 1: Synchronous channel operation TAUBnTOC.TAUBnTOCm 1: Operating mode 2 TAUBnTOL.TAUBnTOLm...
Page 565 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for triangle PWM output function Table 13-106 Operating Procedure for Triangle PWM Output Function Operation TAUBn Status Channel operation is stopped. Master channels: Set TAUBnCMORm/ TAUBnCMURm register and the channel output mode as described in (4) Register settings for master channels.
Page 566 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams Duty cycle = 0% The following settings apply to the general timing diagram. • Master channels: – INTTAUBnIm is generated at the beginning of operation (TAUBnCMORm.TAUBnMD0 = 1). – TAUBnCDRm = a = 5 •...
Page 567 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Duty cycle = 100% The following settings apply to the general timing diagram. • Master channels: – INTTAUBnIm is generated at the beginning of operation (TAUBnCMORm.TAUBnMD0 = 1) – TAUBnCDRm = a = 5 •...
Page 568 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.20.2 Triangle PWM Output Function with Dead Time Overview Summary This function generates multiple triangle PWM outputs with a predefined dead time added by using a master and two or more slave channels. The resulting PWM signals are output via TAUBnTTOUTm of the slave channel 3, enabling the pulse cycle (frequency) and the duty cycle of TAUBnTTOUTm to be set using the master and slave channels.
Page 569 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Description The counter starts by setting the channel trigger bit (TAUBnTS.TAUBnTSm) to 1. This makes TAUBnTE.TAUBnTEm = 1, enabling count operation. The current value of TAUBnCDRm is loaded into TAUBnCNTm and the counter starts to count down from the TAUBnCDRm value.
Page 570 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-107 Operation of TAUBnTTOUTm upon Occurrence of an Interrupt on Slave Channel 2 Count Direction of Slave TAUBnTDL. Channel 2 upon Occurrence TAUBnTTOUTm Set/Reset TAUBnTDLm of Interrupt Timing Down Set after elapse of dead time Reset right after interrupt occurs Down Set right after interrupt occurs...
Page 571 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Block diagram and general timing diagram Master Interval timer mode Trigger from upper channel Simultaneous Start trigger from master rewrite trigger INT from master from upper channels TAUBnTRO. INT from upper channel TAUBnTROm CK3-0 Count clock...
Page 572 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • Master channels: – INTTAUBnIm is generated at the beginning of operation. (TAUBnCMORm.TAUBnMD0 = 1) • Slave channel 2: – INTTAUBnIm is not generated at the beginning of operation. (TAUBnCMORm.TAUBnMD0 = 0) –...
Page 573 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm Master a + 1 a + 1 b + 1 b + 1 Slave 1 Down Down Slave 2 TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0001 TAUBnCDRm INTTAUBnIm Slave 2 (a + 1 - e)*2 (b + 1 - f)*2...
Page 574 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for master channels TAUBnCMORm for master channels TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-108 TAUBnCMORm Settings for Master Channels of Triangle PWM Output Function with Dead Time Bit Name Setting TAUBnCKS[1:0]...
Page 575 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for master channels Table 13-110 Control Bit Settings in Independent Channel Output Mode 1 Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 0: Independent channel output TAUBnTOC.TAUBnTOCm 0: Operating mode 1 (toggle mode when TAUBnTOM.TAUBnTOMm = 0)
Page 576 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channel 2 TAUBnCMORm for slave channel 2 TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-112 TAUBnCMORm Settings for Slave Channel 2 of Triangle PWM Output Function with Dead Time Bit Name Setting...
Page 577 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for slave channel 2 Table 13-114 Control Bit Settings in Synchronous Channel Output Mode 2 with Dead Time Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 1: Synchronous channel operation TAUBnTOC.TAUBnTOCm 1: Operating mode 2...
Page 578 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Register settings for slave channel 3 TAUBnCMORm for slave channel 3 TAUBnCKS TAUBnCCS TAUB TAUBnCOS TAUBn TAUBnSTS[2:0] TAUBnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 13-116 TAUBnCMORm Settings for Slave Channel 3 of Triangle PWM Output Function with Dead Time Bit Name Setting...
Page 579 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Channel output mode for slave channel 3 Table 13-118 Control Bit Settings in Synchronous Channel Output Mode 2 with Dead Time Output Bit Name Setting TAUBnTOE.TAUBnTOEm 1: Enables indepenent channel output mode. TAUBnTOM.TAUBnTOMm 1: Synchronous channel operation TAUBnTOC.TAUBnTOCm...
Page 580 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Operating procedure for triangle PWM output function with dead time Table 13-120 Operating Procedure for Triangle PWM Output Function with Dead Time Operation TAUBn Status Channel operation is stopped. Master channels: Set TAUBnCMORm/ TAUBnCMURm register and the channel output mode as described in (4) Register settings for master channels.
Page 581 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Specific timing diagrams Duty cycle = 0% The following settings apply to the general timing diagram. • Slave channel 2: – Positive logic (TAUBnTDL.TAUBnTDLm = 0) • Slave channel 3: – Negative logic (TAUBnTDL.TAUBnTDLm = 1) TAUBnCNTm (master) CDRm + 1...
Page 582 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Duty cycle = 100% The following settings apply to the general timing diagram. • Slave channel 2: – Positive logic (TAUBnTDL.TAUBnTDLm = 0) • Slave channel 3: – Negative logic (TAUBnTDL.TAUBnTDLm = 1) TAUBnCNTm (master) INTTAUBnIm...
Page 583 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) • If TAUBnCDRm (slave 2) = 0000 , INTTAUBnIm is not generated while the counter of slave channel is counting up. TAUBnTTOUTm remains at the active level because there is no reset signal of TAUBnTTOUTm to be detected.
Page 584 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (c)TAUBnTTOUTm (slave 2) = 0 % and TAUBnTTOUTm (slave 3) > 0 % The following settings apply to the diagram below: • Slave channel 2: – Positive logic (TAUBnTOL.TOLm = 0) • Slave channel 3: –...
Page 585 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) • When the counter of slave channel 2 reaches 0000 , INTTAUBnIm (slave 2) is generated. The counter of slave channel 3 starts to count down. • If another INTTAUBnIm (slave 2) is generated while the counter of slave channel 3 is still counting down, the value of TAUBnCDRm (slave 3) is reloaded and the counter restarts counting down from this value.
Page 586 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (d)TAUBnTTOUTm (slave 2) > 0 % and TAUBnTTOUTm (slave 3) = 100 % The following settings apply to the diagram below: • Slave channel 2: – Positive logic (TAUBnTOL.TOLm = 0 ) •...
Page 587 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) • After the second interrupt, a slave for which TAUBnTDL.TDLm = 1 waits for dead time to elapse before resetting. However, before the dead time has elapsed, another interrupt occurs on slave 2, this time while the counter is counting up.
Page 588 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (e)Inhibited INTTAUBnIm to set TAUBnTTOUTm positive phase period The following settings apply to the diagram below: • Slave channel 2: – Positive logic (TAUBnTOL.TOLm = 0 ) • Slave channel 3: – Negative logic (TAUBnTOL.TOLm = 1) TAUBnCNTm (master) CDRm...
Page 589 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) • The counter of slave channel 3 reaches 0000 and generates an INTTAUBnIm to set the TAUBnTTOUTm of slave channel for which TAUBnTDL.TDLm = 0 (slave channel 2 in this example). • If channel 2 generates an INTTAUBnIm to reset TAUBnTTOUTm simultaneously, this reset signal has priority (assuming TAUBnTOL.TOLm = 0, otherwise the set signal has priority).
Page 590 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) (f)Inhibited INTTAUBnIm to set TAUBnTTOUTm negative phase period The following settings apply to the diagram below: • Slave channel 2: – Positive logic (TAUBnTOL.TOLm = 0 ) • Slave channel 3: – Negative logic (TAUBnTOL.TOLm = 1) TAUBnCNTm (master) INTTAUBnIm...
Page 591 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) • The counter of slave channel 3 reaches 0000 and generates an INTTAUBnIm to set the TAUBnTTOUTm of slave channel for which TAUBnTDL.TDLm = 1 (slave 3 in this example). • If channel 2 generates an INTTAUBnIm to reset TAUBnTTOUTm simultaneously, the set signal has priority (assuming TAUBnTOL.TOLm = 1, otherwise the reset signal has priority).
Page 592 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.20.3 AD Conversion Trigger Output Function Type 2 Overview Summary This function is identical to Section 13.20.1, Triangle PWM Output Function, except that TAUBnTTOUTm is not output. This function is enabled by setting channel output mode for the slave to independent channel output mode controlled by software.
Page 593 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) The following settings apply to the general timing diagram. • Master channel – INTTAUBnIm is generated at the beginning of operation. (TAUBnCMORm.TAUBnMD0 = 0) TAUBnTS.TAUBnTSm TAUBnTE.TAUBnTEm TAUBnCNTm 0000 TAUBnCDRm TAUBnTTOUTm INTTAUBnIm a + 1 a + 1 b + 1 b + 1...
Page 594 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.21 Registers This section contains a description of all the registers of the 16-bit Timer Array Unit B. 13.21.1 Overview of TAUBn Registers TAUBn is controlled and operated by the registers listed below. One register with one channel is indicated by “m”, which stands for 0 to 15.
Page 595 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.21.2 Details of TAUBn Prescaler Registers TAUBnTPS - TAUBn prescaler clock select register This register specifies clocks CK0, CK1, CK2, and CK3 for all channels of the PCLK prescaler. Access Readable/writable in 16-bit units. Address <TAUBn_base0>...
Page 596 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-122 Description of TAUBnTPS Register (2/4) Bit Position Bit Name Function 11 to 8 TAUBnPRS2 Specifies prescaler output CK2 clock. [3:0] TAUBnPRS2[3:0] Prescaler Output CK2 Clock 0000 PCLK/2 0001 PCLK/2 0010 PCLK/2 0011 PCLK/2...
Page 597 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-122 Description of TAUBnTPS Register (3/4) Bit Position Bit Name Function 7 to 4 TAUBnPRS1 Specifies prescaler output CK1 clock. [3:0] TAUBnPRS1[3:0] Prescaler Output CK1 Clock 0000 PCLK/2 0001 PCLK/2 0010 PCLK/2 0011 PCLK/2...
Page 598 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-122 Description of TAUBnTPS Register (4/4) Bit Position Bit Name Function 3 to 0 TAUBnPRS0 Specifies prescaler output CK0 clock. [3:0] TAUBnPRS0[3:0] Prescaler Output CK0 Clock 0000 PCLK/2 0001 PCLK/2 0010 PCLK/2 0011 PCLK/2...
Page 599 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.21.3 Details of TAUBn Control Registers TAUBnCDRm - TAUBn channel data register m This register functions either as a compare register or as a capture register, depending on the operating mode specified in TAUBnCMORm.TAUBnMD[4:1]. Access Readable/writable in 16-bit units.
Page 600 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCNTm - TAUBn channel counter register m This is a channel m counter register. Access Readable in 16-bit units. Address <TAUBn_base1> + 80 + m × 4 Initial value 0000 or FFFF An initial value depends on an operating mode.
Page 601 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-125 TAUBnCNTm Read Values after Re-Enabling Counter TAUBnCNTm Value Count Method Mode Name (Up/Down) After Reset After Stop Trigger After One Count Interval timer mode Count down FFFF Stop value Judge mode Count down FFFF Stop value...
Page 602 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCMORm - TAUBn channel mode OS register m This register controls channel m operation. Access Readable/writable in 16-bit units. Writable when the counter is stopped (TAUBnTE.TAUBnTEm = 0). Address <TAUBn_base0> + 200 + m ×...
Page 603 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-126 Description of TAUBnCMORm Register (2/4) Bit Position Bit Name Function 10 to 8 TAUBnSTS Selects an external start trigger. [2:0] TAUBn TAUBn TAUBn STS2 STS1 STS0 Functional Description Software trigger Valid edge of TAUBnTTINm input signal, which is specified by TAUBnCMURm.TAUBnTIS[1:0].
Page 604 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-126 Description of TAUBnCMORm Register (3/4) Bit Position Bit Name Function 7, 6 TAUBnCOS Specifies the timing for updating capture register TAUBnCDRm and overflow flag [1:0] TAUBnCSRm.TAUBnOVF of channel m. These bits are valid only when channel m is in capture mode. TAUBn TAUBn COS1...
Page 605 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) Table 13-126 Description of TAUBnCMORm Register (4/4) Bit Position Bit Name Function 4 to 0 TAUBnMD Specifies an operating mode. [4:0] TAUBn TAUBn TAUBn TAUBn TAUBn Functional Description Interval timer mode Judge mode Capture mode Event count mode One-count mode...
Page 606 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCMURm - TAUBn channel mode user register m This register specifies a type of valid edge detection used for TAUBnTTINm input. Access Readable/writable in 8-bit units. Address <TAUBn_base1> + C0 + m × 4 Initial value This register is initialized by any reset source.
Page 607 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCSRm - TAUBn channel status register m This register indicates the count direction and overflow status of channel m counter. Access Readable in 8-bit units. Address <TAUBn_base1> + 140 + m × 4 Initial value This register is initialized by any reset source.
Page 608 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnCSCm - TAUBn channel status clear trigger register m This is a trigger register for clearing the overflow flag TAUBnCSRm.TAUBnOVF of channel m. Access Writable in 8-bit units. This value is always read as 00 Address <TAUBn_base1>...
Page 609 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnTE - TAUBn channel enable status register This register enables/disables a counter operation. Access Readable in 16-bit units. Address <TAUBn_base1> + 1C0 Initial value 0000 This register is initialized by any reset source. TAUB TAUB TAUB...
Page 610 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.21.4 Details of TAUBn Output Registers TAUBnTOE - TAUBn channel output enable register This register enables/disables the independent channel output mode controlled by software. Access Readable/writable in 16-bit units. Writable only while the counter is stopped (TAUBnTE.TAUBnTEm = 0).
Page 611 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnTOC - TAUBn channel output configuration register This register specifies the output mode of each channel in combination with TAUBnTOMm. Access Readable/writable in 16-bit units. Writable only while the counter is stopped (TAUBnTE.TAUBnTEm = 0).
Page 612 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnTDE - TAUBn channel dead time output enable register This register enables/disables the dead time operation of every channel. Access Readable/writable in 16-bit units. Writable only while the counter is stopped (TAUBnTE.TAUBnTEm bit = 0). Address <TAUBn_base0>...
Page 613 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnTDL - TAUBn channel dead time output level register This register selects a phase in which dead time is added. Access Readable/writable in 16-bit units. Writable only while the counter is stopped (TAUBnTE.TAUBnTEm bit = 0) Writable only while the counter is stopped (TAUBnTE.TAUBnTEm = 0).
Page 614 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.21.5 Details of TAUBn Channel Output Level Registers TAUBnTO - TAUBn channel output register This register specifies and reads a TAUBnTTOUTm level. Access Readable/writable in 16-bit units. Address <TAUBn_base1> + 58 Initial value 0000 This register is initialized by any reset source.
Page 615 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) 13.21.6 Details of TAUBn Simultaneous Rewrite Registers TAUBnRDE - TAUBn channel reload data enable register This register enables/disables simultaneous rewrite of TAUBnCDRm/ TAUBnTOLm data register. Access Readable/writable in 16-bit units. Writable only while the counter is stopped (TAUBnTE.TAUBnTEm = 0).
Page 616 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnRDM - TAUBn channel reload data mode register This register selects the timing for generating a simultaneous rewrite control signal. Access Readable/writable in 16-bit units. Writable only while the counter is stopped (TAUBnTE.TAUBnTEm = 0).
Page 617 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnRDT - TAUBn channel reload data trigger register This register triggers a simultaneous rewrite pending state. Access Writable in 16-bit units. This value is always read as 0000 Address <TAUBn_base1> + 44 Initial value 0000 This register is initialized by any reset source.
Page 618 V850E2/PG4-L Section 13 Timer Array Unit B (TAUB) TAUBnRSF - TAUBn channel reload status register This flag register indicates simultaneous rewrite status. Access Readable in 16-bit units. Address <TAUBn_base1> + 48 Initial value 0000 This register is initialized by any reset source. TAUB TAUB TAUB...
Page 619 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Section 14 Timer Array Unit J (TAUJ) This section provides general description of the timer array unit J (TAUJ). The first part of this section describes all this product specific properties, such as instances, register base addresses, input/output signal names, etc.
Page 620 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Clock supply The timer array unit J provides one clock input. Table 14-3 TAUJn Clock Supply TAUJn Clock Connected to TAUJ0 PCLK Clock controller Interrupts and The time array unit J can generate the following interrupt requests and DMA requests.
Page 621 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.2 Functional Overview Features summary The TAUJ has the following functions. • 4 channels • 32-bit counter and 32-bit data register per channel • Independent channel operation • Synchronous channel operation (master and slave operations) •...
Page 622 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) The following figure shows the main components of the TAUJ. Prescaler block PCLK 15-bit counter (PCLK/2-PCLK/2 BRS7-0 Selector Selector Selector Selector CK3_pre 8-bit counter PRS03-00 PRS13-10 PRS23-20 PRS33-30 Simultaneous rewrite trigger from master Start trigger from master INT from master INT from upper channel...
Page 623 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.2.1 Terms In this section, the following terms are used. • Independent/synchronous channel operation Independent or synchronous channel operation describes the dependency of channels on each other. – If a channel operates independently of all other channels, this is called independent channel operation.
Page 624 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.3 Functional Description The timer array unit J is used to perform various count or timer operations and to output a signal which depends on the result of the operation. It contains one prescaler block for count clock generation and 4 channels, each equipped with a 32-bit counter TAUJnCNTm and a 32-bit data register TAUJnCDRm to hold the count start value or compare value.
Page 625 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnTO controller The output control of every channel enables the generation of various output signals such as PWM signals. 14.3.1 Timer Operation Functions This timer provides the following functions by operating individual channels independently or a combination of channels.
Page 626 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.4 General Operating Procedure The following lists the general operation procedure for TAUJn. After a reset release, the operation of each channel is stopped. When the clock supply is started, writing to each register is enabled. The control register of TAUJnTTOUTm is also initialized to output a low level.
Page 627 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.5 Operating Modes The TAUJ contains seven operating modes. One operating mode can be set for each channel. It is specified using the TAUJnCMORm.TAUJnMD[4:0] bits. Note Depending on the operation functions, some of the registers and bits have fixed values and the other can be set by the user.
Page 628 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.6 Concepts of Synchronous Channel Operation In synchronous channel operation, multiple channels depend on each other, or are affected by changes in other channels. Therefore, several rules apply to the use of synchronous channel functions. These rules are detailed in Section 14.6.1, Rules.
Page 629 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJn CH0: Master Channel group 1 (operated by CK0) CH1: Slave CH2: Master Channel group 2 (operated by CK2) CH3: Slave The count clock can be set separately for each channel group. TAUJn CH0: Master Channel group 1 (operated by CK0)
Page 630 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.6.2 Simultaneous Start and Stop of Synchronous Channel Counters Channels that are operated synchronously can be started and stopped simultaneously, both within a TAUJ unit and between TAUJ units. Simultaneous start and stop within a TAUJ unit •...
Page 631 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.7 Simultaneous Rewrite 14.7.1 Overview Simultaneous rewrite describes the ability to change the compare/start value and the output logic of multiple channels at the same time. The corresponding data and control registers (TAUJnCDRm and TAUJnTOLm) can be written at any time.
Page 632 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.7.2 How to Control Simultaneous Rewrite The following figure shows the general procedure for simultaneous rewrite. The three main blocks (Initial settings, Start counter & count operation, and Simultaneous rewrite) are explained afterwards. Initial settings TAUJnTS.TAUJnTS settings Update the buffer of data register...
Page 633 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Initial settings • To enable simultaneous rewrite in channel m, set TAUJnRDE.TAUJnRDEm = 1 Start counter and count operation • To start all the TAUJnCNTm counters in the channel group, set the corresponding TAUJnTS.TAUJnTSm bits to 1.
Page 634 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.7.4 Simultaneous Rewrite Procedure Simultaneous rewrite is executed when the master channel starts or restarts counting. The simultaneous rewrite procedure is described in the following figure. TAUJnTS.TSm TAUJnTE.TEm TAUJnCNT0 INTTAUJnI0 TAUJnCNT1 INTTAUJnI1 TAUJnTTOUT1 TAUJnTOL.TOL1 TAUJnTOL.TOL1 buf...
Page 635 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Description: 1. When TAUJnTS.TAUJnTSm = 1 is set, the value of TAUJnCDRm is copied to the TAUJnCDRm buffer and the value of TAUJnTOL.TAUJnTOLm is copied to the TAUJnTOL.TAUJnTOLm buffer. 2. The TAUJnCDRm and TAUJnTOL.TAUJnTOLm registers can be written at any time.
Page 636 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.8 Channel Output Modes The output of the TAUJnTTOUTm pin can be controlled in two ways, the latter of which can be further split into individual modes. • Control by software (TAUJnTOE.TAUJnTOEm = 0) When controlled by software, the value written in the output register bit (TAUJnTO.TAUJnTOm) is output through the output pin (TAUJnTTOUTm).
Page 637 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Output logic Positive logic or inverted logic of the output is specified by control bit TAUJnTOL.TAUJnTOLm. The value of the TAUJnTOL.TAUJnTOLm bit should be set before the counter is started. It can be changed during operation only with PWM output function. If TAUJnTOL.TAUJnTOLm is changed after the start of counter operation, an invalid TAUJnTTOUTm signal is output.
Page 638 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.8.1 General Procedure for Specifying a Channel Output Mode This section describes the general procedures for specifying a TAUJnTTOUTm channel output mode. The prerequisite is that a timer output operation is disabled (TAUJnTOE.TAUJnTOEm = 0). 1.
Page 639 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.8.2 Channel Output Modes Controlled Independently by TAUJn Signals This section lists the channel output modes that are controlled independently by TAUJn signals. The control bits used to specify a mode are listed in Table 14-8, Channel Output Modes.
Page 640 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.8.3 Channel Output Modes Controlled Synchronously by TAUJn Signals This section lists the channel output modes that are controlled synchronously by TAUJn signals. The control bits used to specify a mode are listed in Table 14-8, Channel Output Modes.
Page 641 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.9 Start Timing of Operating Modes This section describes the counter operation start timing after TAUJnTS.TAUJnTSm is set to 1. The value of the data register (TAUJnCDRm register) and whether or not an interrupt occurs depend on mode and register settings.
Page 642 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.9.2 Other Operating Modes In other operating modes, the counter operation is triggered only by detection of a valid TAUJnTTINm edge. The value of data register is also loaded when the counter starts. The count clock cycles, which are unrelated to counter operation start, determine the frequency with which all operations take place.
Page 643 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.10 TAUJnTTOUTm Output and INTTAUJnIm Generation When Counter Starts or Restarts When the counter starts, it is possible to specify whether an INTTAUJnIm is generated using the TAUJnCMORm.TAUJnMD0 bit. The effect of the bit depends on the selected mode, as shown in the following table.
Page 644 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.11 TAUJnTTINm Edge Detection The TAUJnTTINm edge is detected at the rising edge of a sampling clock. A delay of one sampling clock cycle or less may occur. The following figure shows when edge detection takes place. PCLK Sampling clock TAUJnTTINm...
Page 645 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.12 Independent Channel Operation Functions The following sections list the independent channel operation functions provided by the timer array unit J. For a general overview of independent channel operation, see Section 14.3, Functional Description. 14.12.1 Interval Timer Function Overview Summary...
Page 646 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Block diagram and general timing diagram Interval Trigger from upper timer mode Start trigger from master Simultaneous rewrite INT from master TAUJnTRO. Trigger from INT from upper TAUJnTROm upper CK3-0 Count clock TAUJnTO.
Page 647 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings TAUJnCMORm TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-10 TAUJnCMORm Settings for Interval Timer Function Bit Name Setting TAUJnCKS[1:0] Selects the sampling clock 00: Prescaler output CK0 01: Prescaler output CK1 10: Prescaler output CK2 11: Prescaler output CK3...
Page 648 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Channel output mode Table 14-12 Control Bit Settings for Independent Channel Output Mode 1 Bit Name Setting TAUJnTOE.TAUJnTOEm 1: Enables independent channel output mode TAUJnTO.TAUJnTOm 0: Low level 1: High level TAUJnTOM.TAUJnTOMm 0: Independent channel output TAUJnTOC.TAUJnTOCm 0: Operating mode 1 (Toggle mode if...
Page 649 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Operating procedure for Interval Timer Function Table 14-14 Operating Procedure for Interval Timer Function Operation TAUJn Status Set the TAUJnCMORm and TAUJnCMURm Channel operation is stopped. registers as described in Table 14-10, TAUJnCMORm Settings for Interval Timer Function, and Table 14-11, TAUJnCMURm Settings for Interval Timer Function.
Page 650 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Specific timing diagrams TAUJnCDRm = 0000 0000 , count clock = PCLK/2 PCLK Count clock TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm 0000 0000 TAUJnTTOUTm INTTAUJnIm Count clock cycle Figure 14-14 TAUJnCDRm = 0000 0000 , Count Clock = PCLK/2 •...
Page 651 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Operation stop and restart Operation start Operation stop Operation start TAUJnCNTm (Counter) TAUJnCDRm TAUJnTTOUTm INTTAUJnIm TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm Figure 14-16 Operation Stop and Restart (TAUJnCMORm.TAUJnMD0 = 1) • The counter can be stopped by setting TAUJnTT.TAUJnTTm to 1, which in turn sets TAUJnTE.TAUJnTEm to 0.
Page 652 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.12.2 TAUJnTTINm Input Interval Timer Function Overview Summary This function is used as a reference timer for generating timer interrupts (INTTAUJnIm) at regular intervals or when a valid TAUJnTTINm input edge is detected.
Page 653 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) The following settings apply to the general timing diagram. • INTTAUJnIm is generated at the beginning of operation. (TAUJnCMORm.TAUJnMD0 = 1) • Rising edge detection (TAUJnCMURm.TAUJnTIS[1:0] = 01 TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnTTINm TAUJnCNTm 0000 0000 TAUJnCDRm INTTAUJnIm...
Page 654 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings TAUJnCMORm TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-15 TAUJnCMORm Settings for TAUJnTTINm Input Interval Timer Function Bit Name Setting TAUJnCKS[1:0] Selects the sampling clock 00: Prescaler output CK0 01: Prescaler output CK1 10: Prescaler output CK2...
Page 655 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Channel output mode Table 14-17 Control Bit Settings for Independent Channel Output Mode 1 Bit Name Setting TAUJnTOE.TAUJnTOEm 1: Enables Independent Channel Output Mode TAUJnTO.TAUJnTOm 0: Low level 1: High level TAUJnTOM.TAUJnTOMm 0: Independent channel output TAUJnTOC.TAUJnTOCm 0: Operating mode 1 (Toggle mode if...
Page 656 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Operating procedure for TAUJnTTINm Input Interval Timer Function Table 14-19 Operating Procedure for TAUJnTTINm Input Interval Timer Function Operation TAUJn Status Set the TAUJnCMORm and TAUJnCMURm Channel operation is stopped. registers as described in Table 14-15, TAUJnCMORm Settings for TAUJnTTINm Input Interval Timer Function, and Table 14-16, TAUJnCMURm Settings for TAUJnTTINm Input...
Page 657 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Specific timing diagrams Although the timing diagrams in Section 14.12.1, Interval Timer Function, also apply, but it is possible to use valid TAUJnTTINm input edge, by excluding this function, to restart the counter. TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnTTINm...
Page 658 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.12.3 TAUJnTTINm Input Pulse Interval Measurement Function Overview Summary This function captures the count value and uses this value and the overflow bit TAUJnCSRm.TAUJnOVF to measure the interval of the TAUJnTTINm input signals.
Page 659 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Note When TAUJnCMORm.TAUJnCOS[1] = 1, the value of TAUJnCNTm is not loaded into TAUJnCDRm when the first valid TAUJnTTINm input edge occurs after an overflow. However, an interrupt is generated. Equations TAUJnTTINm input pulse interval = Count clock cycle x [(TAUJnCSRm.TAUJnOVF ×...
Page 660 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) The following settings apply to the general timing diagram: • INTTAUJnIm is not generated at the beginning of operation. (TAUJnCMORm.TAUJnMD0 = 0) • Falling edge detection (TAUJnCMURm.TAUJnTIS[1:0] = 00 • When a valid TAUJnTTINm input is detected after an overflow, TAUJnCDRm is changed and TAUJnCSRm.TAUJnOVF is set to 1 (TAUJnCMORm.TAUJnCOS[1:0] = 00 TAUJnTS.TAUJnTSm...
Page 661 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings TAUJnCMORm TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-21 TAUJnCMORm Settings for TAUJnTTINm Input Pulse Interval Measurement Function Bit Name Setting TAUJnCKS[1:0] Selects the sampling clock 00: Prescaler output CK0 01: Prescaler output CK1 10: Prescaler output CK2...
Page 662 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Channel output mode TAUJnTOE.TAUJnTOEm is set to 0 because the channel output mode is not used with this function. However, this mode can be used in independent channel output mode controlled by software. Simultaneous rewrite The simultaneous rewrite registers (TAUJnRDE and TAUJnRDM) cannot be used with the TAUJnTTINm Input Pulse Interval Measurement Function.
Page 663 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Operating procedure for TAUJnTTINm Input Pulse Interval Measurement Function Table 14-24 Operating Procedure for TAUJnTTINm Input Pulse Interval Measurement Function Operation TAUJn Status Set the TAUJnCMORm and Channel operation is stopped. TAUJnCMURm registers as described in Table 14-21, TAUJnCMORm Settings for TAUJnTTINm Input Pulse Interval Measurement Function, and Table 14-22,...
Page 664 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Specific timing diagrams: Overflow operation TAUJnCMORm.TAUJnCOS[1:0] = 00 TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnTTINm FFFF FFFF TAUJnCNTm 0000 0000 TAUJnCDRm 0000 0000 INTTAUJnIm TAUJnCSRm.TAUJnOVF Figure 14-23 TAUJnCMORm.TAUJnCOS[1:0] = 00 , TAUJnCMORm.TAUJnMD0 = 0, TAUJnCMURm.TAUJnTIS[1:0] = 00 •...
Page 665 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnCMORm.TAUJnCOS[1:0] = 10 TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnTTINm FFFF FFFF TAUJnCNTm 0000 0000 TAUJnCDRm FFFF FFFF 0000 0000 INTTAUJnIm TAUJnCSRm.TAUJnOVF Figure 14-25 TAUJnCMORm.TAUJnCOS[1:0] = 10 , TAUJnCMORm.TAUJnMD0 = 0, TAUJnCMURm.TAUJnTIS[1:0] = 00 • When an overflow occurs, TAUJnCDRm is set to FFFF FFFF TAUJnCSRm.TAUJnOVF remains 0.
Page 666 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) • When an overflow occurs, TAUJnCDRm is set to FFFF FFFF , and TAUJnCSRm.TAUJnOVF is set to 1. • Upon detection of the next valid TAUJnTTINm input edge, TAUJnCNTm is reset to 0, but TAUJnCDRm and TAUJnCSRm.TAUJnOVF remain unchanged.
Page 667 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.12.4 TAUJnTTINm Input Signal Width Measurement Function Overview Summary This function measures the width of a TAUJnTTINm input signal. Prerequisites • The operating mode should be set to Capture & One-Count Mode. (See Table 14-26, TAUJnCMORm Settings for TAUJnTTINm Input Signal Width Measurement Function.) •...
Page 668 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Equations TAUJnTTINm input signal width = Count clock cycle × [(TAUJnCSRm.TAUJnOVF × (FFFF FFFF + 1)) + TAUJnCDRm capture value + 1] Block diagram and general timing diagram Capture and Trigger from upper channel one-count mode Start trigger from master Simultaneous rewrite...
Page 669 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings TAUJnCMORm TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-26 TAUJnCMORm Settings for TAUJnTTINm Input Signal Width Measurement Function Bit Name Setting TAUJnCKS[1:0] Selects the sampling clock 00: Prescaler output CK0 01: Prescaler output CK1 10: Prescaler output CK2...
Page 670 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Channel output mode TAUJnTOE.TAUJnTOEm is set to 0 because the channel output mode is not used with this function. However, this mode can be used in independent channel output mode controlled by software. Simultaneous rewrite The simultaneous rewrite registers (TAUJnRDE and TAUJnRDM) cannot be used with the TAUJnTTINm Input Signal Width Measurement Function.
Page 671 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Operating procedure for TAUJnTTINm Input Signal Width Measurement Function Table 14-29 Operating Procedure for TAUJnTTINm Input Signal Width Measurement Function Operation TAUJn Status Set the TAUJnCMORm and Channel operation is stopped. TAUJnCMURm registers as described in Table 14-26, TAUJnCMORm Settings for TAUJnTTINm Input Signal Width Measurement Function, and Table 14-27,...
Page 672 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Specific timing diagrams: Overflow operation TAUJnCMORm.TAUJnCOS[1:0] = 00 TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnTTINm FFFF FFFF TAUJnCNTm 0000 0000 TAUJnCDRm 0000 0000 INTTAUJnIm TAUJnCSRm.TAUJnOVF Figure 14-29 TAUJnCMORm.TAUJnCOS[1:0] = 00 , TAUJnCMORm.TAUJnMD0 = 0, TAUJnCMURm.TAUJnTIS[1:0] = 11 •...
Page 673 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnCMORm.TAUJnCOS[1:0] = 10 TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnTTINm FFFF FFFF TAUJnCNTm 0000 0000 TAUJnCDRm 0000 0000 FFFF FFFF INTTAUJnIm TAUJnCSRm.TAUJnOVF Figure 14-31 TAUJnCMORm.TAUJnCOS[1:0] = 10 , TAUJnCMORm.TAUJnMD0 = 0, TAUJnCMURm.TAUJnTIS[1:0] = 11 • When an overflow occurs, TAUJnCDRm is set to FFFF FFFF TAUJnCSRm.TAUJnOVF remains 0.
Page 674 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) • When an overflow occurs, TAUJnCDRm is set to FFFF FFFF , and TAUJnCSRm.TAUJnOVF is set to 1. • Upon detection of the next valid TAUJnTTINm input edge, TAUJnCNTm is reset to 0, but TAUJnCDRm and TAUJnCSRm.TAUJnOVF remain unchanged.
Page 675 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.12.5 TAUJnTTINm Input Period Count Detection Function Overview Summary This function measures the cumulative width of a TAUJnTTINm input signal. Prerequisites • The operating mode should be set to capture & gate count mode. (See Table 14-30, TAUJnCMORm Settings for TAUJnTTINm Input Period Count Detection Function.) •...
Page 676 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Block diagram and general timing diagram Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master TAUJnTRO. Trigger from upper channel INT from upper channel TAUJnTROm CK3-0 Count clock TAUJnTO.
Page 677 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings TAUJnCMORm TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-30 TAUJnCMORm Settings for TAUJnTTINm Input Period Count Detection Function Bit Name Setting TAUJnCKS[1:0] Selects a sampling clock 00: Prescaler output CK0 01: Prescaler output CK1 10: Prescaler output CK2...
Page 678 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-32 Simultaneous Rewrite Settings for TAUJnTTINm Input Period Count Detection Function Bit Name Setting TAUJnRDE.TAUJnRDEm 0: Disables simultaneous rewrite TAUJnRDM.TAUJnRDMm 0: When disabling simultaneous rewrite (TAUJnRDE.TAUJnRDEm = 0), set these bits to 0 Operating procedure for TAUJnTTINm Input Period Count Detection Function Table 14-33...
Page 679 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Specific timing diagrams Operation stop and restart TAUJnTS.TAUJnTSm TAUJnTT.TAUJnTTm TAUJnTE.TAUJnTEm TAUJnTTINm FFFF FFFF TAUJnCNTm 0000 0000 TAUJnCDRm INTTAUJnIm Figure 14-35 Operation Stop and Restart (TAUJnCMURm.TAUJnTIS[1:0] = 11 • The counter can be stopped by setting TAUJnTT.TAUJnTTm to 1. This sets TAUJnTE.TAUJnTEm to 0.
Page 680 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.12.6 TAUJnTTINm Input Position Detection Function Overview Summary This function measures a time period from count start timing until a TAUJnTTINm input signal. Prerequisites • The operating mode should be set to count capture mode. (See Table 14- 34, TAUJnCMORm Settings for TAUJnTTINm Input Position Detection Function.) •...
Page 681 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Block diagram and general timing diagram Trigger from upper channel Start trigger from master Simultaneous rewrite INT from master TAUJnTRO. Trigger from upper channel INT from upper channel TAUJnTROm CK3-0 Count clock TAUJnTO.
Page 682 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings TAUJnCMORm TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-34 TAUJnCMORm Settings for TAUJnTTINm Input Position Detection Function Bit Name Setting TAUJnCKS[1:0] Selects a sampling clock 00: Prescaler output CK0 01: Prescaler output CK1 10: Prescaler output CK2...
Page 683 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-36 Simultaneous Rewrite Settings for TAUJnTTINm Input Position Detection Function Bit Name Setting TAUJnRDE.TAUJnRDEm 0:Disables simultaneous rewrite TAUJnRDM.TAUJnRDMm 0: When disabling simultaneous rewrite (TAUJnRDE.TAUJnRDEm = 0), set these bits to 0 Operating procedure for TAUJnTTINm Input Position Detection Function Table 14-37 Operating Procedure for TAUJnTTINm Input Position Detection Function...
Page 684 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Specific timing diagrams Operation stop and restart Operation start Operation start Operation stop TAUJnTS.TAUJnTSm TAUJnTT.TAUJnTTm TAUJnTE.TAUJnTEm TAUJnTTINm FFFF FFFF TAUJnCNTm 0000 0000 TAUJnCDRm INTTAUJnIm Figure 14-38 Operation Stop and Restart (TAUJnCMORm.TAUJnMD0 = 0, TAUJnCMURm.TAUJnTIS[1:0] = 00 •...
Page 685 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.13 Synchronous Channel Functions This section describes about the PWM output function which generates PWM signals at a regular interval. For the overview of the synchronous channel operation, see Section 14.3, Functional Description. R01UH0336EJ0102 Rev.1.02 Page 685 of 1538 Jul 17, 2014...
Page 686 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.13.1 PWM Output Functions Overview Summary This function generates multiple PWM outputs by using a master and multiple slave channels. It enables the pulse cycle (frequency) and the duty of the TAUJnTTOUTm to be set. The pulse cycle is set in the master channel. The duty is set in the slave channel.
Page 687 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Equation Pulse cycle = (TAUJnCDRm (master) + 1) × count clock cycle Duty cycle [%] = (TAUJnCDRm (slave) / (TAUJnCDRm (master) + 1) × 100 – Duty cycle = 0 % TAUJnCDRm (slave) = 0000 0000 –...
Page 688 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) The following settings apply to the general timing diagram. • Slave channel: Positive logic (TAUJnTOL.TAUJnTOLm = 0) TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm TAUJnTTOUTm INTTAUJnIm Master Slave TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm TAUJnTTOUTm INTTAUJnIm...
Page 689 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings for master channels TAUJnCMORm for master channels TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-38 TAUJnCMORm Settings for Master Channels of PWM Output Function Bit Name Setting TAUJnCKS[1:0] Selects a sampling clock...
Page 690 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Channel output mode for master channels The channel output mode is not used with this function. However, this mode can be used with another function or in independent channel output mode controlled by software. Simultaneous rewrite for master channels Both master and slave channels should have the same simultaneous rewrite settings.
Page 691 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Register settings for slave channels TAUJnCMORm for slave channels TAUJnCKS TAUJnCCS TAUJ TAUJnCOS TAUJn TAUJnSTS[2:0] TAUJnMD[4:1] [1:0] [1:0] nMAS [1:0] Table 14-41 TAUJnCMORm Settings for Slave Channels of PWM Output Function Bit Name Setting TAUJnCKS[1:0] Selects a sampling clock...
Page 692 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Channel output mode for slave channels Table 14-43 Control Bit Settings in Synchronous Channel Output Mode 1 Bit Name Setting TAUJnTOE.TAUJnTOEm 1: Enables independent channel output mode TAUJnTO.TAUJnTOm 0: Low level 1: High level TAUJnTOM.TAUJnTOMm 1: Synchronous channel operation TAUJnTOC.TAUJnTOCm...
Page 693 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Operating procedure for PWM Output Function Table 14-45 Operating Procedure for PWM Output Function Operation TAUJn Status Master channels: Set the TAUJnCMORm/ Channel operation is stopped. TAUJnCMURm register and channel output mode as described in section 14.13.1 (4), Register settings for master channels.
Page 694 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Specific timing diagrams Duty cycle = 0% TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm INTTAUJnIm Master Slave TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm 0000 0000 TAUJnTTOUTm INTTAUJnIm Figure 14-41 TAUJnCDRm (Slave) = 0000 0000 Positive Logic (TAUJnTOL.TAUJnTOLm (Slave) = 0) •...
Page 695 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Duty cycle = 100% TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm INTTAUJnIm Master Slave TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm TAUJnTTOUTm INTTAUJnIm TAUJnCDRm (Slave) ≥TAUJnCDRm (Master) + 1, Positive Logic Figure 14-42 (TAUJnTOL.TAUJnTOLm (Slave) = 0) •...
Page 696 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Operation stop and restart Operation start Operation stop Operation start TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm TAUJnTTOUTm INTTAUJnIm Master Slave TAUJnTS.TAUJnTSm TAUJnTE.TAUJnTEm TAUJnCNTm 0000 0000 TAUJnCDRm TAUJnTTOUTm INTTAUJnIm Figure 14-43 Operation Stop and Restart, Positive Logic (TAUJnTOL.TAUJnTOLm (Slave) = 0) •...
Page 697 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.14 Registers This section describes all the registers of the 32-bit TAUJ. 14.14.1 Overview of TAUJn Registers The TAUJn is controlled and operated by the registers in the following table. Table 14-46 Overview of TAUJn Registers Register Name Abbreviation...
Page 698 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.14.2 Details of TAUJn Prescaler Registers TAUJnTPS - TAUJn prescaler clock select register This register specifies clocks CK0, CK1, CK2, and CK3_PRE for all channels of the PCLK prescalers. CK3 is generated by dividing CK3_PRE by the factor specified in TAUJnBRS.
Page 699 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-47 Description of TAUJnTPS Register (2/3) Bit Position Bit Name Function 11 to 8 TAUJnPRS2 Specifies prescaler output CK2. [3:0] TAUJnPRS2[3:0] Prescaler Output CK2 0000 PCLK/2 0001 PCLK/2 0010 PCLK/2 0011 PCLK/2 0100 PCLK/2...
Page 700 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-47 Description of TAUJnTPS Register (3/3) Bit Position Bit Name Function 3 to 0 TAUJnPRS0 Specifies prescaler output CK0. [3:0] TAUJnPRS0[3:0] Prescaler Output CK0 0000 PCLK/2 0001 PCLK/2 0010 PCLK/2 0011 PCLK/2 0100 PCLK/2...
Page 701 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnBRS - TAUJn prescaler baud rate setting register This register specifies the division factor of prescaler output CK3. CK3 is generated by dividing CK3_PRE by the factor specified in this register plus one. The PCLK prescaler for CK3_PRE is specified in TAUJnTPS.PRS3[3:0].
Page 702 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.14.3 Details of TAUJn Control Registers TAUJnCDRm - TAUJn channel data register m This register functions either as a compare register or as a capture register, depending on the operating mode specified in TAUJnCMORm.TAUJnMD[4:1]. Access Readable/writable in 32-bit units.
Page 703 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnCNTm - TAUJn channel counter register m This is a channel m counter register. Access Readable in 32-bit units. Address <TAUJn_base > + 10 + m × 4 Initial value 0000 0000 or FFFF FFFF The initial value depends on the operating mode.
Page 704 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-51 TAUJnCNTm Read Values after Counter Is Re-enabled TAUJnCNTm Value After Changing Operating Count Method After Stop Mode after Mode Name (Up/Down) Trigger After One Count Reset Interval timer mode Count-down FFFF FFFF Stop value Capture mode...
Page 705 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnCMORm - TAUJn channel mode OS register m This register controls channel m operation. Access Readable/writable in 16-bit units. Writable only when the counter is stopped (TAUJnTE.TAUJnTEm = 0). Address <TAUJn_base0> + 80 + m ×...
Page 706 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-52 Description of TAUJnCMORm Register (2/4) Bit Position Bit Name Function 10 to 8 TAUJnSTS Selects an external start trigger. [2:0] TAUJn TAUJn TAUJn STS2 STS1 STS0 Functional Description Software trigger Valid edge of TAUJnTTINm input signal, which is specified by TAUJnCMURm.TAUJnTIS[1:0].
Page 707 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-52 Description of TAUJnCMORm Register (3/4) Bit Position Bit Name Function 7, 6 TAUJnCOS Specifies the timing for updating capture register TAUJnCDRm and overflow flag [1:0] TAUJnCSRm.TAUJnOVF of channel m. These bits are valid only when channel m is in capture mode. TAUJn TAUJn COS1...
Page 708 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) Table 14-52 Description of TAUJnCMORm Register (4/4) Bit Position Bit Name Function 4 to 0 TAUJnMD Specifies operating mode. [4:0] TAUJn TAUJn TAUJn TAUJn TAUJn Functional description Interval timer mode Setting prohibited Capture mode Setting prohibited One-count mode...
Page 709 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnCMURm - TAUJn channel mode user register m This register specifies a type of valid edge detection used for TAUJnTTINm input. Access Readable/writable in 8-bit units. Address <TAUJn_base > + 20 + m × 4 Initial value Any reset source triggers initialization.
Page 710 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnCSRm - TAUJn channel status register m This register indicates the overflow status of channel m. Access Readable in 8-bit units. Address <TAUJn_base > + 30 + m × 4 Initial value Any reset source triggers initialization.
Page 711 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnCSCm - TAUJn channel status clear trigger register m This register is a trigger register for clearing the overflow flag TAUJnCSRm.TAUJnOVF of channel m. Access Writable in 8-bit units. The read value is always 00 Address <TAUJn_base >...
Page 712 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnTE - TAUJn channel enable status register This register enables/disables a counter operation. Access Readable in 8-bit units. Address <TAUJn_base > + 50 Initial value Any reset source triggers initialization. TAUJnTE TAUJnTE TAUJnTE TAUJnTE Table 14-57...
Page 713 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.14.4 Details of TAUJn Output Registers TAUJnTOE - TAUJn channel output enable register This register enables/disables independent channel output mode controlled by software. Access Readable/writable in 8-bit units. Writable only while the counter is stopped (TAUJnTE.TAUJnTEm = 0).
Page 714 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnTOC - TAUJn channel output configuration register This register specifies output mode of each channel in combination with TAUJnTOMm. Access Readable/writable in 8-bit units. Writable only while the counter is stopped (TAUJnTE.TAUJnTEm = 0). Address <TAUJn_base0>...
Page 715 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.14.5 Details of TAUJn Channel Output Level Registers TAUJnTO - TAUJn channel output register This register specifies and reads a TAUJnTTOUTm level. Access Readable/writable in 8-bit units. Address <TAUJn_base > + 5C Initial value Any reset source triggers initialization.
Page 716 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) 14.14.6 Details of TAUJn Reload Data Registers TAUJnRDE - TAUJn channel reload data enable register This register enables/disables simultaneous rewrite of the data register TAUJnCDRm/TAUJnTOLm. Access Readable/writable in 8-bit units. Writable only while the counter is stopped (TAUJnTE.TAUJnTEm = 0).
Page 717 V850E2/PG4-L Section 14 Timer Array Unit J (TAUJ) TAUJnRDT - TAUJn channel reload data trigger register This register triggers a simultaneous rewrite pending state. Access Writable in 8-bit units. The read value is always 00 Address <TAUJn_base > + 68 Initial value Any reset source triggers initialization.
Page 718 V850E2/PG4-L Section 15 TSG2 (TSG20) Section 15 TSG2 (TSG20) 15.1 Functions of TSG2n Channels This product provides 1 instance of TSG2n. Table 15-1 TSG2 Channels TSG2 Number of instance Name TSG20 Meaning of n Throughout this section, the TSG2 channels are identified by suffix n (n = 0). For example, n is used as in TSG2n control register (TSnCTL0).
Page 719 V850E2/PG4-L Section 15 TSG2 (TSG20) Interrupt The TSG2 interrupt requests are listed in Table 15-5. requests Table 15-5 List of TSG2 Interrupt Requests TSG2n Interrupt Request Function Connected to INTTSG2nI00 TSnCMP0 compare match interrupt Interrupt controller INTTSG2nI01 TSnCMP1 compare match interrupt Interrupt controller INTTSG2nI02 TSnCMP2 compare match interrupt...
Page 720 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.2 Functional Overview The TSG2n is a 16-bit timer counter with various motor control functions. • Count clock resolution: Minimum 12.5 ns (count clock = 80 MHz) • Operating mode corresponding to various motor control methods •...
Page 721 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.3 Configuration TSnDTCM TSnTS Write protection TSnTT PCLK TSnTE TSnDTC0 Counter control TSnCKS TSnDTC1 TSnMD1-0 TSnDTC0BF TSnCMP0 TSnCMP0BF TSnDTC1BF TSnCNT TSnCMPI-12 TSnCMP1-12BF TSnSBC TSnPAT0-1W TSnPAT0-1WBF TSG2nO1 Dead time control U phase control TSG2nO2 Timer output control and pattern TSG2nPTSI2-0 output control...
Page 722 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.4 Registers This section contains a description of all registers of the TSG2n. 15.4.1 TSG2n Registers Overview The TSG2n is controlled and operated based on the settings of the following registers listed in Table 15-6. Table 15-6 TSG2n Registers (1/2) Register Name...
Page 723 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-6 TSG2n Registers (2/2) Register Name Symbol Address TSG2n pattern register 0 TSnPAT0W <TSG2n_base1> + 064 TSG2n pattern register 1 TSnPAT1W <TSG2n_base1> + 068 TSG2n dead time setting register 0 TSnDTC0W <TSG2n_base1> + 06C TSG2n dead time setting register 1 TSnDTC1W <TSG2n_base1>...
Page 724 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.4.2 TSG2n Register Details TSG2n Control Register 0 (TSnCTL0) This register specifies the pulse width for the diagnostic output and operating mode of the TSG2n. Access This register can be read/written in 8-bit units. Address <TSG2n_base0>...
Page 725 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n Control Register 1 (TSnCTL1) This register controls the flags of TSG2n. Access This register can be read/written in 16-bit units. Address <TSG2n_base0> + 20C Initial value 0000 This register is initialized by a reset from any source. TSnPTC TBA2 TBA1...
Page 726 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-8 TSnCTL1 Register Contents (1/2) Bit Position Bit Name Function TSnTBA2 Enables or disables detection of the simultaneous active states of the TSG2nO5 and TSG2nO6 pins. 0: Disables detection of simultaneous active states of the TSG2nO5 and TSG2nO6 pins.
Page 727 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-8 TSnCTL1 Register Contents (2/2) Bit Position Bit Name Function TSnPEC Enables or disables detection of the pattern error (TSnSTR2.TSnPEF) of the TSG2nPTSI2 to TSG2nPTSI0 pins. 0: Disables detection of the pattern error of the TSG2nPTSI2 to TSG2nPTSI0 pins.
Page 728 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n Control Register 3 (TSnCTL3) This register selects the rewrite method of the compare registers. Access This register can be read/written in 8-bit units. Address <TSG2n_base1> + 004 Initial value This register is initialized by a reset from any source. Table 15-9 TSnCTL3 Register Contents Bit Position...
Page 729 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n Control Register 4 (TSnCTL4) This register enables or disables generation of a peak interrupt and a valley interrupt, and the reload timing. Access This register can be read/written in 32-bit units. Address <TSG2n 1> + 07C _base Initial value 00000000...
Page 730 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-10 TSnCTL4 Register Contents (2/2) Bit Position Bit Name Function 4 to 0 TSnRCC Specifies the skipping rate of the interrupts (INTTSG2nIPEK and [04:00] INTTSG2nIVLY) and reload. Skipping TSnRCC04 TSnRCC03 TSnRCC02 TSnRCC01 TSnRCC00 Rate None 1/30 1/31...
Page 731 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n Control Register 5 (TSnCTL5) This register controls A/D conversion trigger output (TSnADTRG0). Access This register can be read/written in 16-bit units. Address < > + 008 TSG2n_base1 Initial value 0000 This register is initialized by a reset from any source. TSnACC [01:00] AT09...
Page 732 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-11 TSnCTL5 Register Contents (2/3) Bit Position Bit Name Function TSnAT07 Specifies generation of A/D conversion trigger (TSnADTRG0) at the match timing of the 16-bit counter value during defragmentation with the TSnDCMP2 value. 0: Disables generation of the A/D conversion trigger at the match timing of the 16-bit counter value during defragmentation with the TSnDCMP2 value.
Page 733 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-11 TSnCTL5 Register Contents (3/3) Bit Position Bit Name Function TSnAT00 Specifies generation of A/D conversion trigger (TSnADTRG0) at the timing (valley interrupt) when the 16-bit counter switches from decrementing to incrementing. 0: Disables generation of the A/D conversion trigger at the timing of a valley interrupt (INTTSG2nIVLY) after being skipped.
Page 734 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n Control Register 6 (TSnCTL6) This register controls the A/D conversion trigger output (TSnADTRG1). Access This register can be read/written in 16-bit units. Address < 1> + 00C TSG2n_base Initial value 0000 This register is initialized by a reset from any source. TSnACC [11:10] AT19...
Page 735 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-12 TSnCTL6 Register Contents (2/2) Bit Position Bit Name Function TSnAT17 Specifies generation of A/D conversion trigger (TSnADTRG1) at the match timing of the 16-bit counter value during defragmentation and the TSnDCMP2 value. 0: Disables generation of the A/D conversion trigger at the match timing of the 16-bit counter value during defragmentation with the TSnDCMP2 value.
Page 736 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n I/O Control Register 0 (TSnIOC0) This register controls the timer output pins (TSG2nO1 to TSG2nO6). Access This register can be read/written in 8-bit units. Address < 0> + 200 TSG2n_base Initial value This register is initialized by a reset from any source. TOE6 TOE5 TOE4...
Page 737 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n I/O Control Register 1 (TSnIOC1) This register controls the timer output pins (TSG2nO1 to TSG2nO6). Access This register can be read/written in 8-bit units. Address < > + 204 TSG2n_base0 Initial value This register is initialized by a reset from any source. Table 15-14 TSnIOC1 Register Contents (1/2) Bit Position...
Page 738 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-14 TSnIOC1 Register Contents (2/2) Bit Position Bit Name Function TSnTGS Selects the A/D conversion trigger diagnostic output (TSG2nO7) signal. 0: Selects A/D conversion trigger output. 1: Selects diagnostic output. TSnTOS Selects the timer counter increment/decrement status output (TSG2nO0) signal.
Page 739 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2n I/O Control Register 2 (TSnIOC2) This register controls the timer output pins (TSG2nO1 to TSG2nO6). Access This register can be read/written in 16-bit units. Address < > + 000 TSG2n_base1 Initial value 0000 This register is initialized by a reset from any source. Table 15-15 TSnIOC2 Register Contents Bit Position...
Page 740 V850E2/PG4-L Section 15 TSG2 (TSG20) (10) TSG2n I/O Control Register 3 (TSnIOC3) This register controls timer output pins (TSG2nO1 to TSG2nO6). Access This register can be read/written in 32-bit units. Address < 1> + 074 TSG2n_base Initial value 00000000 This register is initialized by a reset from any source. TOL6 TOL5 TOL4...
Page 741 V850E2/PG4-L Section 15 TSG2 (TSG20) (11) TSG2n Status Register 0 (TSnSTR0) This register controls the flags. Access This register can be read/written in 8-bit units. Address < > + 010 TSG2n_base1 Initial value This register is initialized by a reset from any source. Table 15-17 TSnSTR0 Register Contents Bit Position...
Page 742 V850E2/PG4-L Section 15 TSG2 (TSG20) (12) TSG2n Status Register 1 (TSnSTR1) This register controls the flags. Access This register can only be read in 8-bit units. Address < 1> + 014 TSG2n_base Initial value This register is initialized by a reset from any source. TSnOPF[2:0] Table 15-18 TSnSTR1 Register Contents...
Page 743 V850E2/PG4-L Section 15 TSG2 (TSG20) (13) TSG2n Status Register 2 (TSnSTR2) This register controls the flags. Access This register can only be read in 16-bit units. Address < 1> + 018 TSG2n_base Initial value 0000 This register is initialized by a reset from any source. TBF2 TBF1 TBF0...
Page 744 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-19 TSnSTR2 Register Contents (2/2) Bit Position Bit Name Function TSnPPF Indicates detection of the difference between the input patterns (TSG2nPTSI0 to TSG2nPTSI2) and the output patterns (TSG2nO1 to TSG2nO6) after they are compared. 0: No phase difference detected between the input patterns (TSG2nPTSI0 to TSG2nPTSI2) and the output patterns (TSG2nO1 to TSG2nO6).
Page 745 V850E2/PG4-L Section 15 TSG2 (TSG20) (14) TSG2n Status Clear Trigger Register (TSnSTC) This register controls the flags. Access This register can only be written in 16-bit units. Address < 1> + 01C TSG2n_base Initial value 0000 This register is initialized by a reset from any source. TBR2 TBR1 TBR0...
Page 746 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-20 TSnSTC Register Contents (2/2) Bit Position Bit Name Function TSnNDR This is a trigger bit that clears TSnSTR2.TSnNDF. 0: Does not clear TSnNDF. 1: Clears TSnNDF. • When TSnNDR writing and TSnSTR2.TSnNDF setting occur simultaneously, TSnSTR2.TSnNDF setting has a priority, and the flag is not cleared.
Page 747 V850E2/PG4-L Section 15 TSG2 (TSG20) (15) TSG2n Option Register 0 (TSnOPT0) This register sets the optional functions. Access This register can be read/written in 8-bit units. Address < 1> + 020 TSG2n_base Initial value This register is initialized by a reset from any source. Table 15-21 TSnOPT0 Register Contents (1/2) Bit Position...
Page 748 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-21 TSnOPT0 Register Contents (2/2) Bit Position Bit Name Function TSnPSC Selects the pattern output order when the semi-automatic cruise function is enabled. 0: Switches the timer output (TSG2nO1 to TSG2nO6) in the normal rotation. 1: Switches the timer output (TSG2nO1 to TSG2nO6) in the reverse rotation.
Page 749 V850E2/PG4-L Section 15 TSG2 (TSG20) (16) TSG2n Option Register 1 (TSnOPT1) This register sets the optional functions. Access This register can be read/written in 8-bit units. Address < > + 024 TSG2n_base1 Initial value This register is initialized by a reset from any source. TSnSPC[2:0] Table 15-22 TSnOPT1 Register Contents...
Page 750 V850E2/PG4-L Section 15 TSG2 (TSG20) (17) TSG2n Trigger Register 0 (TSnTRG0) This register controls the start of the timer. Access This register can only be written in 8-bit units. Address < 1> + 030 TSG2n_base Initial value This register is initialized by a reset from any source. Table 15-23 TSnTRG0 Register Contents Bit Position...
Page 751 V850E2/PG4-L Section 15 TSG2 (TSG20) (18) TSG2n Trigger Register 1 (TSnTRG1) This register controls the stop of the timer. Access This register can only be written in 8-bit units. Address < > + 034 TSG2n_base1 Initial value This register is initialized by a reset from any source. Table 15-24 TSnTRG1 Register Contents Bit Position...
Page 752 V850E2/PG4-L Section 15 TSG2 (TSG20) (19) TSG2n Counter Read Buffer Register (TSnCNT) From this register the counter value can be read. Access This register can only be read in 16-bit units. Address < 1> + 028 TSG2n_base Initial value 0000 This register is initialized by a reset from any source.
Page 753 V850E2/PG4-L Section 15 TSG2 (TSG20) (20) TSG2n Sub-Counter Read Buffer Register (TSnSBC) From this register the sub-counter value can be read. Access This register can only be read in 16-bit units. Address < 1> + 02C TSG2n_base Initial value 0000 This register is initialized by a reset from any source.
Page 754 V850E2/PG4-L Section 15 TSG2 (TSG20) (21) TSG2n Compare Register 0 (TSnCMP0) This register specifies the PWM period. Access This register can be read/written in 32-bit units. Address < > + 058 TSG2n_base1 Initial value 00000000 This register is initialized by a reset from any source. 16-bit compare register Table 15-27 TSnCMP0 Register Setting...
Page 755 V850E2/PG4-L Section 15 TSG2 (TSG20) (22) TSG2n Compare Register 1, 2 (TSnCMP1W) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < > + 040 TSG2n_base1 Initial value 00000000 This register is initialized by a reset from any source. TSnCMP2 (16-bit compare register) TSnCMP1 (16-bit compare register) Table 15-28...
Page 756 V850E2/PG4-L Section 15 TSG2 (TSG20) (23) TSG2n Compare Register 3, 4 (TSnCMP3W) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < > + 04C TSG2n_base1 Initial value 00000000 This register is initialized by a reset from any source. TSnCMP4 (16-bit compare register) TSnCMP3 (16-bit compare register) Table 15-29...
Page 757 V850E2/PG4-L Section 15 TSG2 (TSG20) (24) TSG2n Compare Register 5, 6 (TSnCMP5W) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < > + 044 TSG2n_base1 Initial value 00000000 This register is initialized by a reset from any source. TSnCMP6 (16-bit compare register) TSnCMP5 (16-bit compare register) Table 15-30...
Page 758 V850E2/PG4-L Section 15 TSG2 (TSG20) (25) TSG2n Compare Register 7, 8 (TSnCMP7W) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < > + 050 TSG2n_base1 Initial value 00000000 This register is initialized by a reset from any source. TSnCMP8 (16-bit compare register) TSnCMP7 (16-bit compare register) Table 15-31...
Page 759 V850E2/PG4-L Section 15 TSG2 (TSG20) (26) TSG2n Compare Register 9, 10 (TSnCMP9W) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < > + 048 TSG2n_base1 Initial value 00000000 This register is initialized by a reset from any source. TSnCMP10 (16-bit compare register) TSnCMP9 (16-bit compare register) Table 15-32...
Page 760 V850E2/PG4-L Section 15 TSG2 (TSG20) (27) TSG2n Compare Register 11, 12 (TSnCMP11W) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < > + 054 TSG2n_base1 Initial value 00000000 This register is initialized by a reset from any source. TSnCMP12 (16-bit compare register) TSnCMP11 (16-bit compare register) Table 15-33...
Page 761 V850E2/PG4-L Section 15 TSG2 (TSG20) (28) TSG2n Compare Register 1 to 12 (TSnCMP1 to TSnCMP12) This register specifies the compare value. Access This register can be read/written in 16-bit units. Address TSnCMP1 < > + 080 TSG2n_base1 TSnCMP2 < > + 084 TSG2n_base1 TSnCMP3 <...
Page 762 V850E2/PG4-L Section 15 TSG2 (TSG20) (29) TSG2n Diagnostic Output Compare Register 0, 1 (TSnDCMP0W) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < 1> + 05C TSG2n_base Initial value 00000000 This register is initialized by a reset from any source. TSnDCMP1 (16-bit compare register) TSnDCMP0 (16-bit compare register) Setting of this register is used to control the diagnostic output or A/D...
Page 763 V850E2/PG4-L Section 15 TSG2 (TSG20) (30) TSG2n Diagnostic Output Compare Register 2 (TSnDCMP2) This register specifies the compare value. Access This register can be read/written in 32-bit units. Address < 1> + 060 TSG2n_base Initial value 00000000 This register is initialized by a reset from any source. TSnDCMP2 (16-bit compare register) Setting of this register is used to control the diagnostic output or A/D conversion trigger timing in all the modes.
Page 764 V850E2/PG4-L Section 15 TSG2 (TSG20) (31) TSG2n Pattern Register 0 (TSnPAT0W) This register specifies the output pattern. Access This register can be read/written in 32-bit units. Address < 1> + 064 TSG2n_base Initial value 00000000 This register is initialized by a reset from any source. PAT5T PAT5T PAT4T...
Page 765 V850E2/PG4-L Section 15 TSG2 (TSG20) (32) TSG2n Pattern Register 1 (TSnPAT1W) This register specifies the output pattern. Access This register can be read/written in 32-bit units. Address < 1> + 068 TSG2n_base Initial value 00000000 This register is initialized by a reset from any source. PAT5B PAT5B PAT4B...
Page 766 V850E2/PG4-L Section 15 TSG2 (TSG20) (33) TSG2n Dead Time Setting Register 0 (TSnDTC0W) This register sets the dead time value (the period from inverse phase inactivation to positive phase activation). Access This register can be read/written in 32-bit units. Address <...
Page 767 V850E2/PG4-L Section 15 TSG2 (TSG20) (34) TSG2n Dead Time Setting Register 1 (TSnDTC1W) This register sets the dead time (the period from positive phase inactivation to inverse phase activation). Access This register can be read/written in 32-bit units. Address < 1>...
Page 768 V850E2/PG4-L Section 15 TSG2 (TSG20) (35) TSG2n HT-PWM U Phase Compare Register (TSnCMPU) This register sets the compare value for U phase in HT-PWM mode. Access This register can be read/written in 16-bit units. Address < 1> + 0B0 TSG2n_base Initial value 0000 This register is initialized by a reset from any source.
Page 769 V850E2/PG4-L Section 15 TSG2 (TSG20) (37) TSG2n HT-PWM W Phase Compare Register (TSnCMPW) This register sets the compare value for W phase in HT-PWM mode. Access This register can be read/written in 16-bit units. Address < 1> + 0B8 TSG2n_base Initial value 0000 This register is initialized by a reset from any source.
Page 770 V850E2/PG4-L Section 15 TSG2 (TSG20) (38) TSG2n SP-PWM U Phase Active Width Setting Register (TSnUPW) This register sets the active width for U phase in SP-PWM mode. Access This register can be read/written in 16-bit units. Address < 1> + 0BC TSG2n_base Initial value 0000...
Page 771 V850E2/PG4-L Section 15 TSG2 (TSG20) (40) TSG2n SP-PWM W Phase Active Width Setting Register (TSnWPW) This register sets the active width for W phase in SP-PWM mode. Access This register can be read/written in 16-bit units. Address < 1> + 0C4 TSG2n_base Initial value 0000...
Page 772 V850E2/PG4-L Section 15 TSG2 (TSG20) (41) TSG2n Dead Time Protection Register (TSnDTPR) This register controls protection of the write access to the dead time register. Access This bit can be read/written in 16-bit units. Address < 0> + 210 TSG2n_base Initial value 0000 This register is initialized by a reset from any source.
Page 773 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.5 Basic Operation 15.5.1 Basic Operation of 16-Bit Counter The basic operation of the 16-bit counter is described. For details, see Section 15.11, Operating Modes. Counting start The 16-bit counter of TSG2n starts counting from the initial value 0000 in all modes except for HT-PWM mode.
Page 774 V850E2/PG4-L Section 15 TSG2 (TSG20) Interrupt In the TSG2n, the following interrupts are generated. operation • INTTSG2nI00: A period interrupt by a match of the 16-bit counter value with the TSnDTC0 value in HT-PWM mode. A compare match interrupt of the 16- bit counter value with the TSnCMP0 buffer register in any mode other than HT-PWM mode.
Page 775 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.5.2 Functions of Compare Registers The functions of the compare registers in each operating mode are shown in Table 15-37. Table 15-37 Compare Register Functions in Each Mode (1/4) Operating Mode TSnCMP0 TSnCMP1W TSnCMP3W TSnCMP5W PWM mode Setting PWM period TSnCMP1:...
Page 776 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-37 Compare Register Functions in Each Mode (2/4) TSnCMP1 to Operating Mode TSnCMP7W TSnCMP9W TSnCMP11W TSnCMP12 PWM mode TSnCMP7: TSnCMP9: TSnCMP11: See TSNCMP1W to Setting TSG2nO4 Setting TSG2nO5 Setting TSG2nO6 TSnCMP11W. clear timing clear timing clear timing TSnCMP8: TSnCMP10:...
Page 777 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-37 Compare Register Functions in Each Mode (3/4) Operating Mode TSnDCMP0W TSnDCMP2W TSnCMPU TSnCMPV PWM mode Setting diagnostic Setting diagnostic output or A/D output or A/D conversion trigger conversion trigger timing timing HT-PWM mode Setting diagnostic Setting diagnostic The TSnCMPU set...
Page 778 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.5.3 Compare Register Rewrite Operation The following compare registers are rewritten by reload (TSnCTL3.TSnRMC = 0) or anytime rewrite (TSnCTL3.TSnRMC = 1). • TSnCMP0 • TSnCMP1 to TSnCMP12 (TSnCMP1W, TSnCMP3W, TSnCMP5W, TSnCMP7W, TSnCMP9W, TSnCMP11W) • TSnPAT0W, TSnPAT1W •...
Page 779 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-38 Example of DMA Transfer Order of Registers to be Reloaded DMA Transfer Order Address Register Name (Example) <TSG2n_base1> + 040 TSnCMP1W <TSG2n_base1> + 044 TSnCMP5W <TSG2n_base1> + 048 TSnCMP9W <TSG2n_base1> + 04C TSnCMP3W <TSG2n_base1>...
Page 780 V850E2/PG4-L Section 15 TSG2 (TSG20) Example of Operation in Anytime Rewrite Mode In this mode, the values written to the compare registers (TSnCMP1 to TSnCMP12) are transferred to the internal buffer registers immediately, and are compared with the counter value. The values are transferred to the internal compare buffer registers one clock cycle (PCLK) after being written to the compare registers (TSnCMP1 to TSnCMP12).
Page 781 V850E2/PG4-L Section 15 TSG2 (TSG20) Data Reflection on PWM at Anytime Rewrite in HT-PWM Mode In HT-PWM mode, the following output control is performed depending on the anytime rewrite timing of the compare registers. • If anytime rewrite is performed after the inverse phase is cleared while the 16-bit counter is counting up (the 16-bit sub-counter is counting up), the positive phase is set if the rewritten value is TSnCMPm <...
Page 782 V850E2/PG4-L Section 15 TSG2 (TSG20) Example of Operation in Reload Mode (Simultaneous Rewrite Function) The rewritten values of the registers to be reloaded (TSnCMP0 to TSnCMP12, TSnCTL2, TSnCTL3, TSnIOC3, TSnPAT0W, TSnPAT1W, TSnDTC0W, TSnDTC1W, TSnDCMP0W, and TSnDCMP2) can be transferred to the corresponding buffer registers simultaneously at the reload timing.
Page 783 V850E2/PG4-L Section 15 TSG2 (TSG20) 16-bit counter Reload by writing Reload rewrite timing to TSnCMP1. TSnCMP0 TSnCMP0 buffer TSnCMP1 TSnCMP1 buffer TSnCMP2 TSnCMP2 buffer TSnCMP3 TSnCMP3 buffer TSnCMP4 TSnCMP4 buffer TSnCMP5 TSnCMP5 buffer TSnCMP6 TSnCMP6 buffer Updated simultaneously at reload timing. INTTSG2nIPEK INTTSG2nIVLY Reload request flag...
Page 784 V850E2/PG4-L Section 15 TSG2 (TSG20) Reload Rewrite Setting Example in Each Mode Reloading conditions and setting examples are shown in Table 15-41 and Table 15-42. Table 15-41 List of Reload Settings (when TSnCTL3.TSnRIA = 0) TSnCTL4. TSnCTL4. TSnCTL4. TSnCTL4. TSnCTL4. TSnRCC4 to Mode TSnPRE...
Page 785 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.5.4 List of Outputs in Each Mode Timer Output in Each Mode The list of timer outputs (TSG2nO0 to TSG2nO7 pins) in each mode is shown in Table 15-43. Table 15-43 List of Timer Outputs in Each Mode (1/3) Operating Mode TSG2nO0 Pin TSG2nO1 Pin...
Page 786 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-43 List of Timer Outputs in Each Mode (3/3) Operating Mode TSG2nO6 Pin TSG2nO7 Pin PWM mode Outputs a PWM signal by Outputs a diagnostic signal compare match of or A/D conversion trigger. TSnCMP11W (TSnCMP11 and TSnCMP12) HT-PWM mode Outputs an inverse phase...
Page 787 V850E2/PG4-L Section 15 TSG2 (TSG20) TSG2nO7 Pin Output Control The TSG2nO7 pin can output a pulse of A/D conversion trigger (TSnIOC1.TSnTGS = 0) or diagnostic output (TSnIOC1.TSnTGS = 1). When outputting a pulse of A/D conversion trigger, the TSG2nO7 pin is activated at the rising edge of the TSnADTRG0 signal, and inactivated at the rising edge of the TSnADTRG1 signal.
Page 788 V850E2/PG4-L Section 15 TSG2 (TSG20) The TSG2nO7 pin during diagnostic output outputs the active level with the output width specified by TSnCTL0.TSnDWD at the match timing of the TSnDCMP0 to TSnDCMP2 values with the 16-bit counter value. If another match of the TSnDCMP0 to TSnDCMP2 values with the 16-bit counter value occurs consecutively within the output width specified by TSnDWD causing their active level widths to be overlapped, the TSG2nO7 pin outputs a pulse within 16 clock cycles (PCLK).
Page 789 V850E2/PG4-L Section 15 TSG2 (TSG20) Interrupts in Each Mode A list of interrupts (INTTSG2nI00 to INTTSG2nI12, INTTSG2nIPEK, INTTSG2nIVLY, INTTSG2nIER, and INTTSG2nIWN) in each mode is shown in Table 15-44. Table 15-44 List of Interrupts in Each Mode (1/5) Operating Mode INTTSG2nI00 INTTSG2nI01 INTTSG2nI02...
Page 790 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-44 List of Interrupts in Each Mode (3/5) Operating Mode INTTSG2nI08 INTTSG2nI09 INTTSG2nI10 INTTSG2nI11 PWM mode TSnCMP8 compare TSnCMP9 compare TSnCMP10 TSnCMP11 match interrupt match interrupt compare match compare match interrupt interrupt — — HT-PWM mode TSnCMP9 compare TSnCMP10...
Page 791 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.6 Match Interrupt The TSG2n can generate interrupts such as a compare match interrupt (INTTSG2nIm), a peak interrupt (INTTSG2nIPEK), and a valley interrupt (INTTSG2nIVLY). For an error interrupt and warning interrupt (INTTSG2nIER and INTTSG2nIWN), see Section 15.10, Error/Warning Interrupt. A period interrupt (INTTSG2nI00) is generated for each timer period.
Page 792 V850E2/PG4-L Section 15 TSG2 (TSG20) x = p + d0 16-bit counter d0(TSnDTC0) 0000 p (for period setting) TSnCMP0 I (U phase duty) TSnCMP1/TSnCMP2 j (V phase duty) TSnCMP5/TSnCMP6 TSnCMP9/TSnCMP10 k (W phase duty) TSnDTC0 TSnDTC1 INTTSG2nI01 INTTSG2nI02 INTTSG2nI05 INTTSG2nI06 INTTSG2nI09 INTTSG2nI10 INTTSG2nIPEK...
Page 793 V850E2/PG4-L Section 15 TSG2 (TSG20) 16-bit counter 0000 TSnCMP0 TSnCMP1 TSnCMP2 TSnCMP3 TSnCMP4 INTTSG2nI00 INTTSG2nI01 INTTSG2nI02 INTTSG2nI03 INTTSG2nI04 INTTSG2nIPEK (peak interrupt) INTTSG2nIVLY "L" (valley interrupt) Figure 15-8 Interrupt Generation Example (2/2) (Example of PWM Mode) R01UH0336EJ0102 Rev.1.02 Page 793 of 1538 Jul 17, 2014...
Page 794 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7 Flags Table 15-45 List of Flags Flag Name Symbol Register Operating Mode Up count flag TSnCUF TSnSTR0 HT-PWM mode TSnSUF TSnSTR0 Positive phase and inverse phase simultaneous active TSnTBF0 to TSnSTR2 All operating state detection flag TSnTBF2 modes Reload request flag...
Page 795 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.1 Up Count Flag (TSnCUF and TSnSUF) Name Up count flag (TSnSTR0.TSnCUF and TSnSUF) Description There are following two up count flags. TSnCUF is an up/down count flag of the 16-bit counter. TSnSUF is an up/down count flag of the 16-bit sub-counter. For both TSnCUF and TSnSUF, 0 means increment, and 1 means decrement.
Page 796 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnCMP0 + TSnDTC0 TSnCMP0 + TSnDTC0 + TSnDTC1 16-bit sub-counter 16-bit counter 0000 TSnDTC0 TSnCUF TSnSUF, TSG2nO0 pin TSG2nO0 pin Outputs up/down counting state TSnTOS = 1 TSnTOS = 0 Outputs the up/down counting state of the 16-bit sub-counter to the TSG2nO0 pin.
Page 797 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.2 Positive Phase and Inverse Phase Simultaneous Active State Detection Flag (TSnTBF0 to TSnTBF2) Name Positive phase and inverse phase simultaneous active state detection flag (TSnSTR2.TSnTBF0 to TSnTBF2 flags) Description When any of TSnCTL1.TSnTBA2 to TSnTBA0 is 1, TSnTBF0 to TSnTBF2 can detect the simultaneous active state of the positive phase and inverse phase of TSG2n.
Page 798 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.3 Reload Request Flag (TSnRSF) Name Reload request flag (TSnSTR0.TSnRSF) Description TSnRSF is set to 1 when a reload request is generated (when a value is written to TSnCMP1 (TSnCMP1W, TSnCMPU, TSnCPW)), and cleared to 0 when the value is transferred to all the buffer registers.
Page 799 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.4 Noise Detection Flag (TSnNDF) Name Noise detection flag (TSnSTR2.TSnNDF) Description TSnNDF can detect that two or more pins of TSG2nPTSI2 to TSG2nPTSI0 have changed simultaneously (a noise is generated). TSnNDF is set to 1 when two or more pins of TSG2nPTSI2 to TSG2nPTSI0 have changed simultaneously (a noise is generated), and a warning interrupt (INTTSG2nIWN) is generated.
Page 800 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.5 Pattern Order Detection Flag (TSnTSF) Name Pattern order detection flag (TSnSTR1.TSnTSF) Description TSnTSF can detect the order of patterns input to the TSG2nPTSI2 to TSG2nPTSI0 pins. TSnTSF is set depending on the values input to the TSG2nPTSI2 to TSG2nPTSI0 pins as shown in the table below.
Page 801 V850E2/PG4-L Section 15 TSG2 (TSG20) Detection of Input Pattern Order Immediately after TSG2n starts operation, the rotation direction cannot be determined. Therefore, TSnTSF cannot detect the change (normal or reverse rotation) in the patterns input to the TSG2nPTSI2 to TSG2nPTSI0 pins. To enable detection of change immediately after the beginning of operation, TSnPSC should be set before operation starts (when TSnTE = 0, the TSnPSC value is reflected).
Page 802 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.6 Pattern Error Detection Flag (TSnPEF) Name Pattern error detection flag (TSnSTR2.TSnPEF) Description TSnPEF can detect that 000 or 111 is input to the TSG2nPTSI2 to TSG2nPTSI0 pins. TSnPEF is set to 1 when the levels of the TSG2nPTSI2 to TSG2nPTSI0 pins are 111 or 000, and a warning interrupt (INTTSG2nIWN) is generated.
Page 803 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.7 Pattern Reversal Detection Flag (TSnPRF) Name Pattern reversal detection flag (TSnSTR2.TSnPRF) Description TSnPRF can detect that the pattern change order of the TSG2nPTSI2 to TSG2nPTSI0 pins have been reversed. TSnPRF is set to 1 when the pattern order detection flag (TSnTSF) changes, and a warning interrupt (INTTSG2nIWN) is generated.
Page 804 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.8 TSG2nPTSI2 to TSG2nPTSI0 Pin Abnormal Toggle Detection Flag (TSnPTF) Name TSG2nPTSI2 to TSG2nPTSI0 pin abnormal toggle detection flag (TSnSTR2.TSnPTF) Description TSnPTF can detect that the values of the TSG2nPTSI2 to TSG2nPTSI0 pins change three or more times during the TSnOPCI0 or TSnOPCI1 signal trigger. TSnPTF is set to 1 when the third trigger of TSnOPCI0 or TSnOPCI1 signal occurs simultaneously with the change in TSG2nPTSI2 to TSG2nPTSI0, and a warning interrupt (INTTSG2nIWN) is generated.
Page 805 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.9 TSnOPCI0 and TSnOPCI1 Signal Simultaneous Trigger Detection Flag (TSnTDF) Name TSnOPCI0 and TSnOPCI1 signal simultaneous trigger detection flag (TSnSTR2.TSnTDF) Description TSnTDF can detect that TSnOPCI0 and TSnOPCI1 signals are generated simultaneously. TSnTDF is set to 1 when the TSnOPCI0 and TSnOPCI1 signals are generated simultaneously, and a warning interrupt (INTTSG2nIWN) is generated.
Page 806 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.10 Pattern Phase Difference Detection Flag (TSnPPF) Name Pattern phase difference detection flag (TSnSTR2.TSnPPF) Description TSnPPF can detect the phase difference between the input pattern (TSG2nPTSI2 to TSG2nPTSI0 pins) and the output pattern (TSnSTR1.TSnOPF2 to TSnOPF0 flags). TSnPPF is set to 1 when the pattern phase difference is detected when the TSnOPCI0 and TSnOPCI1 signal triggers are input, and a warning interrupt (INTTSG2nIWN) is generated.
Page 807 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.11 Timer Output Pattern Flag (TSnOPF2 to TSnOPF0) Name Timer output pattern flag (TSnSTR1.TSnOPF2 to TSnOPF0) Description TSnOPF2 to TSnOPF0 flags indicate the timer output patterns. For details, see Section 15.11.4, 120-DC Mode, and Section 15.11.5, Software Output Control Function.
Page 808 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.7.12 Pattern Switch Detection Signal (TSnPTE) Name Pattern switch detection signal (TSnPTE signal) Description The TSnPTE signal toggles when the input pattern (TSG2nPTSI2 to TSG2nPTSI0 pins) changes. The toggle pattern is determined by the TSnPSC bit (TSnOPT0.TSnPSS = 1). TSnPSC = 0 TSG2nPTSI2 to TSG2nPTSI0 Pins after Change Current...
Page 809 V850E2/PG4-L Section 15 TSG2 (TSG20) Example of operation TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnPTE signal Figure 15-24 Example of Pattern Switch Detection Signal Operation Operating mode The TSnPTE signal can be used in all operating modes. Caution The TSnPTE signal is valid only when TSnIOC1.TSnPTS = 1 and TSnSTR0.TSnTE = 1.
Page 810 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.8 Interrupt Skipping Function Operation related to the interrupt skipping function is described below. • Peak interrupts (INTTSG2nIPEK) and valley interrupts (INTTSG2nIVLY) can be skipped. • TSnCTL4.TSnPIE enables outputting of the INTTSG2nIPEK interrupt and specifies whether to skip the interrupts. •...
Page 811 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.8.1 Operation of Interrupt Skipping Function Interrupt Skipping Operation when TSnPIE = 1 and TSnVIE = 1 in TSnCTL4 (Peak and Valley Interrupt Generation in HT-PWM Mode) 16-bit counter TSnRCC04-TSnRCC00 bit = 00H (No skipping) INTTSG2nIPEK Interrupt INTTSG2nIVLY Interrupt TSnRCC04-TSnRCC00 bit = 01H...
Page 812 V850E2/PG4-L Section 15 TSG2 (TSG20) Interrupt Skipping Operation when TSnPIE = 1 and TSnVIE = 0 in TSnCTL4 Register (only Peak Interrupt Generation in HT-PWM Mode) 16-bit counter TSnRCC04 to TSnRCC00 bits = 00 (no skipping) INTTSG2nIPEK interrupt INTTSG2nIVLY interrupt TSnRCC04 to TSnRCC00 bits = 01 (one mask) INTTSG2nIPEK interrupt...
Page 813 V850E2/PG4-L Section 15 TSG2 (TSG20) 16-bit counter INTTSG2nIPEK "L" interrupt INTTSG2nIVLY interrupt TSnRCC04 to TSnRCC00 TSnRCC04 to TSnRCC00 buffers Interrupt skipping counter Interrupt interval Start Normal Normal Reload timing Figure 15-25 When TSnRMC = 0, TSnRIA = 1 in TSnCTL3 (with Reload Skipping) Note 1.
Page 814 V850E2/PG4-L Section 15 TSG2 (TSG20) 16-bit counter INTTSG2nIPEK "L" interrupt INTTSG2nIVLY interrupt TSnRCC04 to TSnRCC00 TSnRCC04 to TSnRCC00 buffers Interrupt skipping counter Interrupt interval Start Normal The interrupt interval is the same as the normal interval because the set value is changed immediately after a valley interrupt is generated.
Page 815 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.8.2 Example of Operation when Peak Interrupt is Generated (in PWM Mode) Operation related to the interrupt skipping function in PWM mode is described below. • Valley interrupts (INTTSG2nIPEK) can be skipped. In PWM mode, it is generated by compare match of TSnCMP0 buffer register and 16-bit counter.
Page 816 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.9 A/D Conversion Trigger Function A/D conversion trigger operation is described below. TSnDCMP0W and TSnDCMP2 are used as compare registers of the A/D conversion trigger function. TSnCTL5.TSnAT09 to TSnAT00 [ 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 9 0 8 ] Valley of 16-bit sub-counter TSnACC01 and Peak of 16-bit sub-counter...
Page 817 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.9.1 Operation of A/D Conversion Trigger TSG2n has a function to generate A/D conversion start triggers (TSnADTRG0 and TSnADTRG1 signals) by selecting any of ten trigger sources as required. The trigger sources are selected by TSnAT09 to TSnAT00 in TSnCTL5 and TSnAT19 to TSnAT10 in TSnCTL6.
Page 818 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnACC01, TSnACC00, and TSnAT09 to TSnAT00, and TSnACC11, TSnACC10, and TSnAT19 to TSnAT10 can be rewritten during timer operation. If A/D conversion trigger setting bits are rewritten during operation, the rewritten values are reflected on the A/D conversion trigger output status immediately.
Page 819 V850E2/PG4-L Section 15 TSG2 (TSG20) 16-bit counter "L" INTTSG2nIPEK interrupt INTTSG2nIVLY interrupt When TSnAT09 to TSnAT00 bits = 00000011B, both INTTSG2nIVLY and INTTSG2nIPEK interrupts cause a trigger pulse to be generated, but a peak interrupt is not generated since TSnPIE bit is 0. TSnADTRG0 signal Figure 15-31 When TSnPIE = 0, TSnVIE = 1, and TSnRCC04 to TSnRCC00 = 02...
Page 820 V850E2/PG4-L Section 15 TSG2 (TSG20) A/D Conversion Trigger Skipping Function Example of operation of the A/D conversion trigger skipping function is shown in Figure 15-70. 16-bit counter INTTSG2nIPEK interrupt INTTSG2nIVLY interrupt TSnDCMP0 compare match TSnDCMP1 compare match (When TSnAT09 to TSnAT00 bits = 0000100101 B , TSnACC01, and TSnACC00 bits = 01 B ) TSnADTRG0 signal (When TSnAT09 to TSnAT00 bits = 0000100101 B , TSnACC01, and TSnACC00 bits = 10 B ) TSnADTRG0 signal...
Page 821 V850E2/PG4-L Section 15 TSG2 (TSG20) When TSnDTC0 = TSnDTC1 = 0000 , TSnACC01 and TSnACC00 bits = 10 , and TSnAT09 to TSnAT00 bits = 0100000000 in TSnCTL5 16-bit counter Valley of 16-bit sub-counter A/D conversion trigger skipping counter TSnADTRG0 signal Note: * Immediately after counting starts, a valley timing of the 16-bit sub-counter is not generated, and thus the A/D conversion trigger skipping counter is not incremented.
Page 822 V850E2/PG4-L Section 15 TSG2 (TSG20) Notes on A/D Conversion Trigger • If the same value is written to TSnDCMP0 and TSnDCMP1 or TSnDCMP2, and the same condition (when the 16-bit counter increments or decrements) is set as the valid A/D conversion trigger, A/D conversion trigger skipping counter is incremented by one and one trigger pulse is output upon a match of the 16-bit counter with these registers.
Page 823 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.10 Error/Warning Interrupt 15.10.1 Error Interrupt Function If the simultaneous active state of the positive phase and inverse phase is detected after the error interrupt function is enabled (TSnIOC1.TSnEOC = 1), TSnSTR2.TSnTBF is set, and an error interrupt (INTTSG2nIER) of TSG2n is generated.
Page 824 V850E2/PG4-L Section 15 TSG2 (TSG20) PWM Mode and 120-DC Mode In PWM mode, if TSnCMP1 and TSnCMP2, and TSnCMP3 and TSnCMP4 are set so that the TSG2nO1 and TSG2nO2 pins output the active level simultaneously, an error interrupt (INTTSG2nIER) is generated. With the same setting, if TSnCMP5, TSnCMP6, TSnCMP7, TSnCMP8, TSnCMP9, TSnCMP10, TSnCMP11, and TSnCMP12 are set so that the TSG2nO3 and TSG2nO4, and TSG2nO5 and TSG2nO6 pins output the active level...
Page 825 V850E2/PG4-L Section 15 TSG2 (TSG20) When the active level of output is switched by operating TSnIOC2.TSnOL1 and TSnOL2, an error interrupt is generated as shown in Figure 15-74. When TSnOL1 = 0, When TSnOL1 = 1, When TSnOL1 = 0, When TSnOL1 = 1, TSnOL2 = 0 TSnOL2 = 0...
Page 826 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.10.2 Warning Interrupt Function TSG2n has a warning interrupt (INTTSG2nIWN). Warning interrupt (INTTSG2nIWN) is generated when any of the following conditions is detected. For details, see Section 15.7, Flags. • When simultaneous change in two or more pins of TSG2nPTSI2 to TSG2nPTSI0 is detected See Section 15.7.4, Noise Detection Flag (TSnNDF).
Page 827 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.11 Operating Modes Table 15-47 List of Modes TSnCTL0 Register TSnMD1 TSnMD0 Timer Modes PWM mode HT-PWM mode (HT-PWM) Shifted-pulse - pulse width modulation mode (SP- PWM) 120-DC mode R01UH0336EJ0102 Rev.1.02 Page 827 of 1538 Jul 17, 2014...
Page 828 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.11.1 PWM Mode Overview A PWM signal is output at the TSG2nO1 to TSG2nO6 pins according to set timing/clear timing of TSnCMP1 to TSnCMP12 registers with the PWM period set in the TSnCMP0 register. Prerequisites •...
Page 829 V850E2/PG4-L Section 15 TSG2 (TSG20) (a) When TSnCMP0 and TSnCMP1 to TSnCMP12 are Not Rewritten during Timer Operation START Initial setting · Setting of PWM mode (TSnCTL0.TSnMD1 and TSnMD0 = 00 · Setting of compare register (TSnCMP0 to TSnCMP12 registers) ·...
Page 830 V850E2/PG4-L Section 15 TSG2 (TSG20) (b) When TSnCMP0 and TSnCMP1 to TSnCMP12 are Rewritten during Timer Operation START Initial setting · Setting of PWM mode (TSnCTL0.TSnMD1 and TSnMD0 = 00 · Setting of compare registers (TSnCMP0 to TSnCMP12 registers) · Setting of PWM output ·...
Page 831 V850E2/PG4-L Section 15 TSG2 (TSG20) List of Operations in PWM Mode Table 15-48 Counter Functions in PWM Mode Operation Setting Conditions TSnTRG0.TSnTS = 0 → 1, or a simultaneous start trigger 16-bit Start counter Clear Compare match of TSnCMP0 buffer register and 16-bit counter TSnTRG1.TSnTT = 0 →...
Page 832 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-53 Example of Setting each Timer Output Condition in PWM Mode Output Duty Item Output Period Output Condition Setting Condition TSG2nOm (TSnCMP0 + 1) × Output an inactive level TSnCMPm = TSnCMP (m + 1) (m = 1 to 6) output count clock...
Page 833 V850E2/PG4-L Section 15 TSG2 (TSG20) When only TSnCMP2 is rewritten and TSG2nO1 is output (TSnIOC0.TSnTOE1 = 1, TSnIOC2.TSnOL1 = 0) FFFF 16-bit counter 0000 TSnTS TSnCMP0,TSnCMP1 TSnCMP0, TSnCMP1 0000 buffer registers TSnCMP2 TSnCMP2 0000 buffer register TSG2nO1 pin TSnRSF Reload timing Figure 15-41 Example of Basic Operation Timing of PWM Mode (1/2) Note 1.
Page 834 V850E2/PG4-L Section 15 TSG2 (TSG20) When TSnCMP0-TSnCMP2 are rewritten, and TSG2nO1 is output (TSnIOC0.TSnTOE1 = 1, TSnIOC2.TSnOL1 = 0) FFFF 16-bit counter 0000 TSnTS TSnCMP0 TSnCMP0 0000 buffer register TSnCMP2 TSnCMP2 0000 buffer register TSnCMP1 TSnCMP1 0000 buffer register TSG2nO1 pin TSnRSF Reload Reload...
Page 835 V850E2/PG4-L Section 15 TSG2 (TSG20) Interrupt/Reload Skipping Function in PWM Mode By setting TSnCTL4.TSnPRE and TSnPIE to 1 and setting the TSnRCC04 to TSnRCC00 and TSnCTL3.TSnRIA, the reload and interrupt skipping function can be used. By setting TSnPRE to 1 and setting the TSnRCC04 to TSnRCC00, the interrupt skipping function can be used.
Page 836 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnCMP3 = TSnCMP0 TSnCMP4 16-bit counter TSnCMP1 TSnCMP2 TSG2nO1 pin TSG2nO2 pin TSnDTC0 TSnDTC1 TSnDTC0 TSnDTC1 TSnDTC0 TSnDTC1 TSnDTC0 TSnDTC1 Figure 15-42 Example of Dead Time Control between TSG2nO1 and TSG2nO2 Outputs (1/2) At (1), the dead time counter starts counting at the falling edge of the TSG2nO2 output.
Page 837 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnCMP0 TSnCMP3 TSnCMP1 TSnCMP3 16-bit counter TSnCMP1 TSnCMP1 TSnCMP2 TSnCMP1 TSnCMP4 TSnCMP2 TSnCMP3 TSnCMP2 TSnCMP4 TSnCMP2 TSnCMP4 TSG2nO1 pin TSG2nO2 pin INTTSG2nIER interrupt TSnDTC0 TSnDTC1 Figure 15-42 Example of Dead Time Control between TSG2nO1 and TSG2nO2 Outputs (2/2) During (1), the dead time counter starts counting at the falling edge of the TSG2nO1 output.
Page 838 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnCMP3 TSnCMP3 TSnCMP3 TSnCMP1 TSnCMP1 16-bit counter TSnCMP1 TSnCMP3 TSnCMP4 TSnCMP2 TSnCMP2 TSnCMP2 TSnCMP2 TSnCMP1 TSG2nO1 pin TSG2nO2 pin INTTSG2nIER interrupt TSnDTC1 TSnDTC0 TSnDTC1 TSnTBF 0 write 0 write (clear) (clear) Figure 15-43 Example of 100% Duty Output at Dead Time Control When the TSG2nO2 pin is set to duty cycle of 100% (TSnCMP3 ≥TSnCMP0 + 1), the output of the TSG2nO1 pin is fixed to a low level.
Page 839 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.11.2 HT-PWM Mode (High accuracy Triangular - Pulse Width Modulation Mode) Overview In this mode, the 16-bit counter (up/down count by ±2 bits, practically 15 bits) and the 16-bit compare registers (LSB is used to control additional pulse) are used to generate a 6-phase PWM signal.
Page 840 V850E2/PG4-L Section 15 TSG2 (TSG20) Block Diagram and Basic Timing Chart 16-bit counter Load 16-bit sub-counter (up/down and ± 2 counts) (up/down and ± 2 counts) Sel1 TSnDTC0 register Sel0 TSnCMP0 buffer register TSnTOS bit TSnCMP0 − TSnDTC1 INTTSG2nIVLY 16'h0000 INTTSG2nIPEK TSG2nO0 TSG2nO1 (U phase)
Page 841 V850E2/PG4-L Section 15 TSG2 (TSG20) START Initial setting · Setting of HT-PWM mode (TSnCTL0.TSnMD1 and TSnMD0 = 01 · Setting of compare registers (TSnCMP0, TSnCMPU, TSnCMPV, and TSnCMPW registers) · Setting of dead time setting registers (TSnDTC0 and TSnDTC1 registers) Timer operation enabled (TSnTRG0.TSnTS = 1) Transfer values of TSnCMP0, TSnCMP1, TSnCMP2, TSnCMP5, TSnCMP6, TSnCMP9, TSnCMP10, TSnDTC0,...
Page 842 V850E2/PG4-L Section 15 TSG2 (TSG20) List of HT-PWM Mode Operations Table 15-55 Counter Function in HT-PWM Mode Operation Setting Condition TSnTRG0.TSnTS = 0 → 1 (up count from TSnDTC0) 16-bit Start counter Up count Compare match of TSnDTC0 buffer register and 16-bit counter Down count Compare match of TSnCMP0 + TSnDTC0 and 16-bit counter Clear TSnTRG1.TSnTT = 0 →...
Page 843 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-57 Timer Output Function in HT-PWM Mode Function TSG2nO0 Active level output during up count, inactive level output at down count of the 16-bit counter/sub-counter TSG2nO1 PWM output with dead time by compare match of TSnCMP1 buffer register and 16-bit counter (down count) and compare match of TSnCMP2 buffer register and 16-bit counter (up count) TSG2nO2...
Page 844 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-60 Example of Setting Each Timer Output Condition in HT-PWM Mode Output Duty Item Output Period Output Condition Setting Condition TSnCMP0  count clock TSG2nO0 Toggle output Output an active level during up count, and an inactive level during down count TSnCMP0 ...
Page 845 V850E2/PG4-L Section 15 TSG2 (TSG20) Various Settings of HT-PWM Mode Mode Setting HT-PWM can be used when TSnCTL0.TSnMD1 and TSnMD0 is set to 01 Setting timer output The output pins TSG2nO1 to TSG2nO6 are controlled by setting TSnIOC0, TSnIOC2, and TSnIOC3. The output pin TSG2nO0 indicates the up/down count status of the 16-bit counter or the 16-bit sub-counter.
Page 846 V850E2/PG4-L Section 15 TSG2 (TSG20) Setting A/D To set A/D conversion trigger 0 (TSnADTRG0 signal), use TSnCTL5.TSnAT09 conversion trigger to TSnAT00. output With TSnAT09 to TSnAT00, A/D conversion trigger output is enabled or disabled at the match of 16-bit counter (during up count) with TSnDCMP2 to TSnDCMP0, the match of the 16-bit counter (during down count) with TSnDCMP2 to TSnDCMP0, the 16-bit counter peak interrupt (INTTSG2nIPEK), the 16-bit counter valley interrupt (INTTSG2nIVLY), the 16-...
Page 847 V850E2/PG4-L Section 15 TSG2 (TSG20) Carrier period Set the carrier period with TSnCMP0 according to the following expression: TSnCMP0 = Carrier period/count clock period (PCLK) Satisfy the following requirements when setting the TSnCMP0 register regarding the dead time: • TSnCMP0 + TSnDTC0 + TSnDTC1 ≤ FFFE •...
Page 848 V850E2/PG4-L Section 15 TSG2 (TSG20) 16-Bit Counter Operation in HT-PWM Mode The 16-bit counter is initialized to 0000 and the value of TSnDTC0 is loaded immediately after starting the TSG2n timer operation (TSnTRG0.TSnTS = 1). Afterwards, counting is done by +2. After 16-bit counter reaches the value of TSnCMP0 + TSnDTC0, counting is done by -2.
Page 849 V850E2/PG4-L Section 15 TSG2 (TSG20) The 16-bit sub-counter is initialized to 0000 and the value of TSnDTC0 is loaded immediately after starting the TSG2n timer operation (TSnTRG0.TSnTS = 1). Afterwards, counting by -2 is done until 0000 reached and counting by +2 begins. Next, the value of the 16-bit counter is loaded into the 16-bit sub-counter at a change timing of the 16-bit counter into the down count.
Page 850 V850E2/PG4-L Section 15 TSG2 (TSG20) Basic Operation of HT-PWM Mode Example of Timer Output Immediately after the Start of the TSG2n Timer Operation Figure 15-51 shows the timing chart when TSnCMP0 = 000E , TSnDTC0 = 0002 , TSnDTC1 = 0004 and TSnCMPU = 0000 -0014 (excerpt).
Page 851 V850E2/PG4-L Section 15 TSG2 (TSG20) Example of Timer Output during TSG2n Timer Operation The figure below shows the timing chart when TSnCMP0 = 000E , TSnDTC0 = 0002 , TSnDTC1 = 0004 , and TSnCMPU is set to 0000 -0014 (excerpt).
Page 852 V850E2/PG4-L Section 15 TSG2 (TSG20) Additional Pulse Control in HT-PWM Mode The HT-PWM mode can generate an additional pulse by setting 1 to the LSB of the duty setting registers (TSnCMPU, TSnCMPV, and TSnCMPW). This allows more precise control of the pulse duty than standard pulse control. The following sections describe two examples of pulse output of TSG2nO1: additional pulse control is used in one example and additional pulse control is not used in another.
Page 853 V850E2/PG4-L Section 15 TSG2 (TSG20) Example of Pulse Output when Additional Pulse Control Is Not Used The arrows and numerical values in Figure 15-52 show the width of the duty cycle of the TSG2nO1 output in one period. When the additional pulse control is not used, the width of the TSG2nO1 output can be set within a range from the width of 12 clock cycles to the width of 0 clock cycles in two-clock-cycle step.
Page 854 V850E2/PG4-L Section 15 TSG2 (TSG20) Dead Time Control in HT-PWM Mode Duty setting registers are TSnCMP1, TSnCMP2, TSnCMP5, TSnCMP6, TSnCMP9, and TSnCMP10 and registers for setting the period are TSnCMP0, TSnDTC0, and TSnDTC1 in HT-PWM mode. The 6-phase PWM waveform of a variable duty is output by using these registers.
Page 855 V850E2/PG4-L Section 15 TSG2 (TSG20) Notes Concerning Dead Time Control in HT-PWM Mode TSnDTC0 and TSnDTC1 Rewriting It is possible to rewrite the dead time setting in TSnDTC0 and TSnDTC1 registers during timer operation. Caution 1. Rewrite TSnDTC0 and TSnDTC1 when the reload function is used (TSnRMC = 0).
Page 856 V850E2/PG4-L Section 15 TSG2 (TSG20) Software Output Control Function in HT-PWM Mode TSnOPT0.TSnSOC, TSnIDC, and TSnOPT1.TSnSPC2-TSnSPC0 are used in HT-PWM mode for software control of timer output control. As shown in Figure 15-54, with TSnSTE = 0, the output control is switched immediately when TSnSOC is set to 1.
Page 857 V850E2/PG4-L Section 15 TSG2 (TSG20) Procedure for Software Output Control START Set the output pattern to TSnOPT1. TSnSPC2-TSnSPC0. Set TSnSOC to 1 simultaneously. Change the setting of TSnSPC2-TSnSPC0 Repeat as required. and switch the output pattern. TSnSTR0.TSnRSF = 0? Set TSnSOC to 0. Write to TSnCMPV and TSnCMPW.
Page 858 V850E2/PG4-L Section 15 TSG2 (TSG20) The procedure for software output control is described below. (1) Set the output pattern to the TSnOPT1.TSnSPC2-TSnSPC0. To enable software output control, set TSnOPT0.TSnSOC to 1 simultaneously. (2) Change the output pattern setting of the TSnSPC2-TSnSPC0 to change the timer output.
Page 859 V850E2/PG4-L Section 15 TSG2 (TSG20) (10) Asymmetric Triangular Wave Control in HT-PWM Mode In HT-PWM mode, it is possible to control output by an asymmetric triangular waveform by setting the different timings for setting and clearing the U, V, and W phases.
Page 860 V850E2/PG4-L Section 15 TSG2 (TSG20) Timer Output TSnCMP0+ TS nDTC0 +TSnDTC1 TSnCMP0 +TSnDTC0 TSnCMP0 TSnCMP6 TSnCMP1 TSnDTC0 + TSnDTC1 TSnCMP1-2 , 5 -6, 9-10 TSnCMP0 TSnCMP9 TSnCMP10 TSnSBC TSnCMP5 TSnCNT TSnCMP2 TSnDTC0 +TSnDTC1 TSnDTC0 0000H TSnDTC0 TSG2nO1 U phase TSG2nO2 TSnDTC1 TSnDTC0 TSG2nO3...
Page 861 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.11.3 SP-PWM Mode (Shifted-pulse - Pulse Width Modulation Mode) Overview In this mode, a 6-phase PWM can be generated using the 16-bit counter and the 16-bit compare registers. Prerequisites • The PWM signal cycle is set in TSnCMP0. •...
Page 862 V850E2/PG4-L Section 15 TSG2 (TSG20) Basic Timing Chart PWM period = (TSnCMP0 + 1) count clock TSnCMP0 TSnCMP1 TSnCMP9 TSnCMP5 TSnCNT TSnCMP10 TSnCMP6 TSnCMP2 TSnDTC0 0000H TSG2nO1 U phase TSnDTC1 TSG2nO2 TSnDTC0 TSG2nO3 V phase TSnDTC 1 TSG2nO4 TSnDTC0 TSG2nO5 W phase TSnDTC1 TSG2nO6...
Page 863 V850E2/PG4-L Section 15 TSG2 (TSG20) START Initial setting · Set SP-PWM mode (TSnCTL0.TSnMD1 and TSnMD0 = 10 · Set compare registers (TSnCMPm (m = 0, 1, 2, 5, 6, 9, 10)) · Set PWM output · Set dead time setting registers (TSnDTC0, TSnDTC1) Enable timer operation (TSnTRG0.TSnTS = 1) Transfer the values of TSnCMPm (m = 0, 1, 2, 5, 6, 9, 10),...
Page 864 V850E2/PG4-L Section 15 TSG2 (TSG20) List of SP-PWM Mode Operations Table 15-61 Counter Functions in SP-PWM Mode Operation Setting Condition TSnTRG0.TSnTS = 0 → 1 16-bit counter Start Clear Compare match of TSnCMP0 buffer register with 16-bit counter TSnTRG1.TSnTT = 0 → 1 Stop Table 15-62 Compare Registers and Dead Time Setting Register Functions in SP-...
Page 865 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-64 Interrupt Requests in SP-PWM Mode Interrupt Function INTTSG2nIVLY INTTSG2nIPEK Peak interrupt (generated at the same timing as INTTSG2nI00) INTTSG2nIWN Warning Table 15-65 Compare Match Timing in SP-PWM Mode Compare Match Timing TSnCMP0 When 16-bit counter changes from TSnCMP0 to 0000 TSnCMPm (m = 1, 2, 5, 6, 9, 10) After match of 16-bit counter and TSnCMPm is detected (m = 1, 2, 5, 6, 9, 10)
Page 866 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-66 Example of Setting Each Timer Output Condition in SP-PWM Mode (2/2) Output Duty Item Output Period Output Condition Setting Condition TSG2nO2, PWM output (TSnCMP0 + 1) × count Output an inactive level TSnCMPm = TSG2nO4, clock throughout one period...
Page 867 V850E2/PG4-L Section 15 TSG2 (TSG20) Various Settings of SP-PWM Mode Mode Setting SP-PWM mode is entered by setting TSnCTL0.TSnMD1-TSnMD0 to 10 Setting timer output The output pins TSG2nO1-TSG2nO6 are controlled by setting TSnIOC0, TSnIOC2, and TSnIOC3. The TSG2nO7 pin provides output pulse as diagnostic output or analog to digital conversion trigger.
Page 868 V850E2/PG4-L Section 15 TSG2 (TSG20) Setting dead time The dead time can be set with TSnDTC0 and TSnDTC1. The dead time is calculated by the following expressions: PCLK × TSnDTC0 PCLK × TSnDTC1 TSnDTC0 can set the time between a change of TSG2nO2, TSG2nO4, and TSG2nO6 to the inactive state and a change of TSG2nO1, TSG2nO3, and TSG2nO5 to the active state, respectively.
Page 869 V850E2/PG4-L Section 15 TSG2 (TSG20) Dead Time Control in SP-PWM mode Duty setting registers are TSnCMPm (m = 1, 2, 5, 6, 9, 10), TSnUPW, TSnVPW, and TSnWPW and register for setting the period is TSnCMP0. The 6-phase PWM waveform of a variable duty is output by using these registers. To achieve the dead time control, there are six 10-bit down counters that operate synchronously with the count clock of the 16-bit counter and two dead time setting registers (TSnDTC0 and TSnDTC1).
Page 870 V850E2/PG4-L Section 15 TSG2 (TSG20) Software Output Control Function in SP-PWM Mode TSnOPT0.TSnSOC, TSnIDC, and TSnOPT1.TSnSPC2 to TSnSPC0 are used to control timer output by software. As shown in Figure 15-59, the output control is switched immediately when TSnSOC is set to 1. If the dead time is set, the period of the dead time is guaranteed.
Page 871 V850E2/PG4-L Section 15 TSG2 (TSG20) Procedure on Software Output Control Processing START Set rotation direction with TSnOPT0.TSnIDC Set pattern for output to TSnOPT1.TSnSPC2 to TSnSPC0 and set TSnSOC to 1 Change TSnSPC2 to Repeat as necessary. TSnSPC0 setting to switch output pattern TSnSTR0.
Page 872 V850E2/PG4-L Section 15 TSG2 (TSG20) (6) After software output control is released, set the compare registers if necessary. Move to the following procedure if no setting is required. In addition, change the registers with the reload function if necessary. (7) Write TSnUPW (TSnCMP1) to start reloading. (8) Reload is executed and software output control is released.
Page 873 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.11.4 120-DC Mode Overview In this mode, PWM output period set to TSnCMP0 and timer output (TSG2nO1 to TSG2nO6) according to the duty cycle set to TSnCMP1 to TSnCMP12 are controlled with three types of pattern inputs (software output control method, pattern switch method, and trigger switch method) to perform 120-DC control.
Page 874 V850E2/PG4-L Section 15 TSG2 (TSG20) START Initial setting Setting of 120-DC mode (TSnCTL0.TSnMD1 and TSnMD0 bits = 11B) Setting of compare registers (TSnCMP0 to TSnCMP12) Setting of output pattern (TSnPAT0W and TSnPAT1W) Setting of dead time setting registers (TSnDTC0 and TSnDTC1) Setting of rotation direction (TSnOPT0.TSnIDC bit) Timer operation enabled (TSnTRG0.TSnTS bit = 1).
Page 875 V850E2/PG4-L Section 15 TSG2 (TSG20) List of Operations in 120-DC Mode Table 15-67 Counter Functions in 120-DC Mode Operation Setting Condition TSnTRG0.TSnTS = 0 → 1 16-bit counter Start Clear Match of TSnCMP0 value and 16-bit counter value, or output pattern switch timing TSnTRG1.TSnTT = 0 →...
Page 876 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-71 Interrupt Requests in 120-DC Mode Interrupt Function INTTSG2nIm (m = 00 to 12) Compare match of TSnCMPm buffer register and 16-bit counter (m = 0 to 12) INTTSG2nIER Error INTTSG2nIVLY INTTSG2nIPEK Peak interrupt (generated at the same timing as INTTSG2nI00) INTTSG2nIWN Warning interrupt Table 15-72...
Page 877 V850E2/PG4-L Section 15 TSG2 (TSG20) Various Settings of 120-DC Mode Mode setting 120-DC mode can be used by setting TSnCTL0.TSnMD1 and TSnMD0 are set to 11 Setting timer output The output pins TSG2nO1 to TSG2nO6 are controlled by setting TSnIOC0, TSnIOC2, and TSnIOC3.
Page 878 V850E2/PG4-L Section 15 TSG2 (TSG20) Setting dead time The dead time can be set with TSnDTC0 and TSnDTC1. The dead time is calculated by the following expressions: PCLK × TSnDTC0 PCLK × TSnDTC1 TSnDTC0 can set the time between a change of TSG2nO2, TSG2nO4, and TSG2nO6 to the inactive state and a change of TSG2nO1, TSG2nO3, and TSG2nO5 to the active state, respectively.
Page 879 V850E2/PG4-L Section 15 TSG2 (TSG20) Control Methods in 120-DC Mode Control methods in 120-DC mode are listed below. Control Method Function Software output control Switches the output pattern according to the method TSnOPT1.TSnSPC2 to TSnSPC0 setting made by software. Pattern switch method Directly switches the output pattern by the pattern input signal of TSG2nPTSI0 to TSG2nPTSI2.
Page 880 V850E2/PG4-L Section 15 TSG2 (TSG20) Setting pattern Setting TSnOPT0.TSnSTE to 1 and TSnPOT to 0 selects the pattern switch switch method method. The TSG2nO1 to TSG2nO6 pin output is changed at the change timing of the TSG2nPTSI2 to TSG2nPTSI0 pins. The output order at the beginning of operation is set with TSnOPT0.TSnIDC.
Page 881 V850E2/PG4-L Section 15 TSG2 (TSG20) Setting trigger Setting TSnOPT0.TSnSTE and TSnPOT to 1 selects the trigger switch switch method method. The output pins TSG2nO1 to TSG2nO6 are changed at a rising edge of an external input (TSnOPCI1 and TSnOPCI0 signals). For pattern output order, see Section 15.11.4 (5), Operation in 120-DC Mode.
Page 882 V850E2/PG4-L Section 15 TSG2 (TSG20) Timer Output in 120-DC Mode In 120-DC mode, the PWM output is controlled with TSnPAT0W, TSnPAT1W, and TSnCMP1 to TSnCMP12. TSnPAT0W, TSnCMP1, TSnCMP2, TSnCMP5, TSnCMP6, TSnCMP9, and TSnCMP10 are set to control the output of TSG2nO1, TSG2nO3, and TSG2nO5 pins.
Page 883 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-75 TSnPAT1W Set Value and Output Control PATmB Value Output Control Fixed to low PWM output set with TSnCMP3 PWM output set with TSnCMP4 PWM output set with TSnCMP7 PWM output set with TSnCMP8 PWM output set with TSnCMP11 PWM output set with TSnCMP12 Fixed to high...
Page 884 V850E2/PG4-L Section 15 TSG2 (TSG20) Operation in 120-DC Mode Figure 15-65 to Figure 15-68 show examples of operation in 120-DC mode. The TSG2nO1 to TSG2nO6 pins detect the input level change of the TSG2nPTSI2 to TSG2nPTSI0 pins, then change the output pattern. The 16-bit counter produces sawtooth waveform, and TSnCMP0 to TSnCMP12 output PWM signal.
Page 885 V850E2/PG4-L Section 15 TSG2 (TSG20) Time Input Input Input Input Input Input Input pattern 1 pattern 2 pattern 3 pattern 4 pattern 5 pattern 6 pattern 1 TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin “L” TSnTSF flag Pattern switch trigger 16-bit counter PAT3T PAT4T PAT5T...
Page 886 V850E2/PG4-L Section 15 TSG2 (TSG20) Time Input Input Input Input Input Input Input pattern 1 pattern 2 pattern 3 pattern 4 pattern 5 pattern 6 pattern 1 TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnTSF flag “H” Pattern switch trigger 16-bit counter PAT1T PAT2T PAT3T...
Page 887 V850E2/PG4-L Section 15 TSG2 (TSG20) Time Input Input Input Input Input Input Input pattern 1 pattern 2 pattern 3 pattern 4 pattern 5 pattern 6 pattern 1 TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin TSnTSF flag “H” Pattern switch trigger 16-bit counter PAT4T PAT5T PAT0T...
Page 888 V850E2/PG4-L Section 15 TSG2 (TSG20) List of Output Patterns in 120-DC Mode In 120-DC mode, the output pattern is determined according to the rotation direction and TSnOPT0.TSnIDC. TSnOPT0 TSnPOT TSnPSS Rotation Direction TSnTSF TSnPSC Normal rotation: TSnOPT0.TSnSOC = 0, TSnPSC = 0,TSnPOT = 1, TSnPSS = 1, TSnIDC = 0 The order of pattern switching TSnOPT1.TSnSPC2 to TSnSPC0*/TSnSTR1.TSnOPF2 to TSnOPF0...
Page 889 V850E2/PG4-L Section 15 TSG2 (TSG20) Reverse rotation: TSnOPT0.TSnSOC = 0, TSnPSC = 1, TSnPOT = 1, TSnPSS = 1, TSnIDC = 0 The order of pattern switching TSnOPT1.TSnSPC2 to TSnSPC0*/TSnSTR1.TSnOPF2 to TSnOPF0 Output Pin TSG2nO1 PAT1T PAT0T PAT5T PAT4T PAT3T PAT2T TSG2nO2 PAT1B...
Page 890 V850E2/PG4-L Section 15 TSG2 (TSG20) Operation Start Timing in 120-DC Mode In 120-DC mode, when trigger switch control (TSnOPT0.TSnPOT = 1) is used, pattern set with TSnOPT1.TSnSPC2 to TSnSPC0, rotation direction, and TSnOPT0.TSnIDC can be output. However, when pattern switch control (TSnPOT = 0) is used, the pattern of the TSG2nPTSI2 to TSG2nPTSI0 pins can be detected but rotation direction (TSnSTR1.TSnTSF) cannot be determined.
Page 891 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnOPT0.TSnSOC = 0, TSnPSC = 1, TSnPOT = 0, TSnIDC = 1 Time TSG2nPTSI2 pin TSG2nPTSI1 pin "L" TSG2nPTSI0 pin TSnSTR0.TSnT E PAT0T PAT1T "L" TSG2nO1 pin PAT0B PAT1B TSG2nO2 pin PAT4T PAT5T TSG2nO3 pin PAT5B PAT4B TSG2nO4 pin...
Page 892 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnOPT0.TSnSOC = 0, TSnPSC = 1, TSnPOT = 0, TSnIDC = 1 Time TSG2nPTSI2 pin TSG2nPTSI1 pin TSG2nPTSI0 pin "H" TSnSTR0.TSnTE PAT0T PAT1T TSG2nO1 pin "L" PAT0B PAT1B TSG2nO2 pin PAT4T PAT5T TSG2nO3 pin PAT4B PAT5B "L"...
Page 893 V850E2/PG4-L Section 15 TSG2 (TSG20) Output Switch Timing in 120-DC Mode As shown in Figure 15-73 to Figure 15-76, in 120-DC mode, the external switch timing for output pattern (TSnOPCI0 and TSnOPCI1 signals, and TSG2nPTSI2 to TSG2nPTSI0 pins) is input irrespective of the 16-bit counter operation.
Page 894 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnCMP0 TSnCMP0 TSnCMP0 TSnCMP0 TSnCMP0 16-bit counter TSnCMP2 TSnCMP2 TSnCMP3 TSnCMP3 TSnCMP2 TSnCMP1 TSnCMP1 TSnCMP1 TSnCMP1 TSnCMP1 TSnCMP1 0000 TSnIDC bit TSG2nO1 pin TSG2nO2 pin Figure 15-74 Output Switch Example (Switched by TSnOPT0.TSnIDC) Note When the pattern is switched here, output control is switched in the next period.
Page 895 V850E2/PG4-L Section 15 TSG2 (TSG20) TSnOPT0.TSnSOC = 0, TSnPOT = 1 TSnCMP0 TSnCMP0 TSnCMP0 TSnCMP0 TSnCMP2, TSnCMP2, TSnCMP2, TSnCMP2, 16-bit counter TSnCMP2, TSnCMP4 TSnCMP4 TSnCMP4 TSnCMP4 TSnCMP4 TSnCMP1, TSnCMP1, TSnCMP1, TSnCMP1, TSnCMP1, TSnCMP1, TSnCMP3 TSnCMP3 TSnCMP3 TSnCMP3 TSnCMP3 TSnCMP3 0000 TSG2nO1 pin "L"...
Page 896 V850E2/PG4-L Section 15 TSG2 (TSG20) Compare Register Rewrite Timing in 120-DC Mode Example of operation when TSnCMP1 is reloaded (rewritten simultaneously) is shown below. Figure 15-77 shows an output example when TSnCMP1 is rewritten. After TSnCMP1 is changed, data is not transferred to the TSnCMP1 buffer register (changed data is not valid) until the next reload timing;...
Page 897 V850E2/PG4-L Section 15 TSG2 (TSG20) (10) Dead Time Control in 120-DC Mode In 120-DC mode, the dead time is controlled on falling of each phase, and the dead time is added. The dead time set in TSnDTC1 is inserted on falling of the positive phase, and the dead time set in TSnDTC0 is inserted on falling of the inverse phase.
Page 898 V850E2/PG4-L Section 15 TSG2 (TSG20) (12) Operation when Noise is Generated in TSG2nPTSI2 to TSG2nPTSI0 Pins in 120-DC Mode Input to the TSG2nPTSI2 to TSG2nPTSI0 pins is assumed to be the hall sensor signals of the brushless DC motor. Depending on the system, a noise may be generated on the TSG2nPTSI2 to TSG2nPTSI0 pins.
Page 899 V850E2/PG4-L Section 15 TSG2 (TSG20) Change Timing of Input Pattern Change Detection Signal (TSnPTE) • The TSnPTE signal toggles when the input pattern (TSG2nPTSI2 to TSG2nPTSI0 pins) changes. Caution Be sure to specify the rotation direction by TSnPSC (TSnPSS = 1 in TSnOPT0) in TSnOPT0.
Page 900 V850E2/PG4-L Section 15 TSG2 (TSG20) Change Timing of Three-Phase Encode Signal (TSnPEC) • The TSnPEC signal toggles when input pattern (TSG2nPTSI2 to TSG2nPTSI0 pins) changes. TSG2nPTSI2 to TSG2nPTSI0 Pins after Change Current TSG2nPTSI2 TSG2nPTSI0 Toggle Toggle Pins Toggle Toggle Toggle Toggle Toggle Toggle...
Page 901 V850E2/PG4-L Section 15 TSG2 (TSG20) Set Timing of TSnNDF Flag • The TSnNTF flag is set when two or more pins of the TSG2nPTSI2 to TSG2nPTSI0 pins change simultaneously, and cleared when 1 is written to the TSnNDR bit. The TSnNDF flag is valid when 1 is set to the TSnNDC bit. Set Timing of TSnPRF Flag •...
Page 902 V850E2/PG4-L Section 15 TSG2 (TSG20) (13) Basic Control Flow in 120-DC Mode In 120-DC mode, there are eight control states as listed in Figure 15-76. When TSnOPT0.TSnSTE = 1 and TSnPOT = 0, the pattern switch method is used for 120-DC control. This is defined as fixed phase control.
Page 903 V850E2/PG4-L Section 15 TSG2 (TSG20) Generally, the state, when the motor rotation stops, is assumed to be a state of the start and the control begins. First the fixed phase control is used to rotate the motor from the stopped state. Afterwards, to accelerate the motor speed to the fast rotation, the variable phase control is switched on.
Page 904 V850E2/PG4-L Section 15 TSG2 (TSG20) (14) Software Output Control Function in 120-DC Mode TSnOPT0.TSnSOC and TSnIDC, and TSnOPT1.TSnSPC2 to TSnSPC0 are used in 120-DC mode for timer output control by software. As shown in Figure 15-83, the output control is switched immediately when TSnSOC is set to 1.
Page 905 V850E2/PG4-L Section 15 TSG2 (TSG20) Procedure for Software Output Control START Set the rotation direction with TSnOPT0.TSnIDC. Set the output pattern to TSnOPT1.TSnSPC2 to TSnSPC0 and set TSnSOC to 1 simultaneously. Change the setting of TSnSPC2 to TSnSPC0 Repeat as required. and switch the output pattern.
Page 906 V850E2/PG4-L Section 15 TSG2 (TSG20) (5) By setting TSnSOC = 0 the software control starts to be released (it is not released here yet). (6) After releasing the software output control, set the necessary compare registers. Proceed to the following step when the register setting is not required.
Page 907 V850E2/PG4-L Section 15 TSG2 (TSG20) 15.11.5 Software Output Control Function Software output control function can be used in HT-PWM mode, SP-PWM mode, and 120-DC mode. This function can switch six output patterns for the TSG2nO1 to TSG2nO6 pins using TSnOPT0.TSnSOC, TSnIDC, and TSnOPT1.TSnSPC2 to TSnSPC0.
Page 908 V850E2/PG4-L Section 15 TSG2 (TSG20) Table 15-79 Output Pattern of Software Output Control (TSnOPT0.TSnIDC = 1) TSnOPT0.TSnSOC = 1, TSnSTE = 0, TSnIDC = 1 TSnSTR1.TSnOPF2-TSnOPF0 Output Pin TSG2nO1 INACT INACT INACT INACT TSG2nO2 INACT INACT INACT INACT TSG2nO3 INACT INACT INACT INACT...
Page 909 V850E2/PG4-L Section 16 TPBA Section 16 TPBA 16.1 Functions of TPBAn Instances This product provides 1 instance of TPBAn. Table 16-1 Instances of TPBA TPBA Instances Name TPBA0 Instances index n Throughout this section, the instances of the TPBA are identified by the index "n"...
Page 910 V850E2/PG4-L Section 16 TPBA Interrupts The TPBA interrupt requests are listed in Table 16-5. Table 16-5 List of TPBA Interrupt Requests TPBAn Interrupt Request Function Connected to INTTPBAnIPRD Period-matched detection Interrupt controller interrupt INTTPBAnIDTY Duty-cycle-matched detection Interrupt controller interrupt INTTPBAnIPAT Number-of-patterns matched Interrupt controller detection interrupt...
Page 911 V850E2/PG4-L Section 16 TPBA 16.3 Configuration TPBAnCMP1 TPBAnRSF1 Reload Compare register TPBAnDPS TPBAnCB1 INTTPBAnIPAT Buffer 7-bit counter TPBAnCNT1 Clear TPBAnBUF 63-00 Enable Reload TO controller TPBnO TPBAnPRS1-0 TPBAnTOL Compare register TPBAnTOE TPBAnCB2 Prescaler PCLK TPBAnTO INTTPBAnIDTY Clear 16-bit counter TPBAnSST Controller TPBAnCNT0 INTTPBAnIPRD...
Page 912 V850E2/PG4-L Section 16 TPBA 16.4 Registers This section contains a description of all registers of the TPBAn. 16.4.1 TPBAn Registers Overview The TPBAn is controlled and operated based on the settings of the following registers listed in Table 16-6. Table 16-6 TPBAn Registers Register Name Symbol...
Page 913 V850E2/PG4-L Section 16 TPBA 16.4.2 TPBAn Registers Details TPBAn Control Register (TPBAnCTL) This register specifies the operation of the TPBAn. Access This register can be read/written in 8-bit units. Address <TPBAn_base0> + 200 Initial value This register is initialized by a reset from any source. TPBAn TPBAn TPBAn...
Page 914 V850E2/PG4-L Section 16 TPBA TPBAn Reload Data Mode Register (TPBAnRDM) This register controls the reload timing of the TPBAn period setting register and TPBAn timer output level register values. Access This register can be read/written in 8-bit units. Address <TPBAn_base1> + 118 Initial value This register is initialized by a reset from any source.
Page 915 V850E2/PG4-L Section 16 TPBA TPBAn Reload Status Register (TPBAnRSF) This register indicates whether or not reload requests from the corresponding registers have been generated. Access This register can be read in 8-bit units. Address <TPBAn_base1> + 110 Initial value This register is initialized by a reset from any source. TPBAn TPBAn RSF1...
Page 916 V850E2/PG4-L Section 16 TPBA TPBAn Reload Data Trigger Register (TPBAnRDT) This register enables reload of the register values. Access This register can be written in 8-bit units. It is always read as 0. Address <TPBAn_base1> + 114 Initial value This register is initialized by a reset from any source. TPBAn TPBAn RDT1...
Page 917 V850E2/PG4-L Section 16 TPBA TPBAn Timer Output Enable Register (TPBAnTOE) This register enables or disables the timer output. Access This register can be read/written in 8-bit units. Address <TPBAn_base1> + 120 Initial value This register is initialized by a reset from any source. TPBAn TOE0 Table 16-11...
Page 918 V850E2/PG4-L Section 16 TPBA TPBAn Timer Output Register (TPBAnTO) This register reads the output settings and the output level. Access This register can be read/written in 8-bit units. Address <TPBAn_base1> + 11C Initial value This register is initialized by a reset from any source. TPBAn Table 16-12 TPBAnTO Register Contents...
Page 919 V850E2/PG4-L Section 16 TPBA TPBAn Timer Output Level Register (TPBAnTOL) This register controls the timer output level. Access This register can be read/written in 8-bit units. Address <TPBAn_base1> + 124 Initial value This register is initialized by a reset from any source. TPBAn TOL0 Table 16-13...
Page 920 V850E2/PG4-L Section 16 TPBA TPBAn Period Setting Register (TPBAnCMP0) This is a 16-bit compare register for setting the PWM period. Access This register can be read/written in 16-bit units. Address < 0> + 100 TPBAn_base Initial value 0000 This register is initialized by a reset from any source. TPBAnCMP0 Table 16-14 TPBAnCMP0 Register Setting...
Page 921 V850E2/PG4-L Section 16 TPBA TPBAn Duty Setting Register (TPBAnBUFm) This register is a 16 × 64 buffer register for duty setting. Access This register can be read/written in 16-bit units. Address < 1> + 000 to 0FC TPBAn_base Initial value 0000 This register is initialized by a reset from any source.
Page 922 V850E2/PG4-L Section 16 TPBA (10) TPBAn Pattern Number Setting Register (TPBAnCMP1) This register sets the number of PWM output patterns. Access This register can be read/written in 8-bit units. Address <TPBAn_base1> + 104 Initial value This register is initialized by a reset from any source. TPBAnCMP1 Table 16-16 TPBAnCMP1 Register Contents...
Page 923 V850E2/PG4-L Section 16 TPBA (11) TPBAn Timer Counter Register (TPBAnCNT0) This register is a 16-bit counter that generates PWM output. Access This register can only be read in 16-bit units. Address < 1> + 108 TPBAn_base Initial value FFFF This register is initialized by a reset from any source. TPBAnCNT0 16-bit counter This register is a counter register through which the 16-bit counter value can...
Page 924 V850E2/PG4-L Section 16 TPBA (13) TPBAn Enable Status Register (TPBAnTE) This register indicates whether the timer counter is operating or stopped. Access This register can only be read in 8-bit units. Address <TPBAn_base1> + 128 Initial value This register is initialized by a reset from any source. TPBAn Table 16-17 TPBAnTE Register Contents...
Page 925 V850E2/PG4-L Section 16 TPBA (14) TPBAn Start Trigger Register (TPBAnTS) This register controls the timer counter start trigger. Access This register can only be written in 8-bit units. It is always read as 0. Address <TPBAn_base1> + 12C Initial value This register is initialized by a reset from any source.
Page 926 V850E2/PG4-L Section 16 TPBA 16.5 Basic Operation 16.5.1 Basic Operation of Counter Basic Operation of 16-Bit Counter (TPBAnCNT0) Counting start The 16-bit counter (TPBAnCNT0) starts counting from the initial value FFFF Counter clear The 16-bit counter is cleared by the match of the counter value and the buffer register (TPBAnCB0) set value of TPBAnCMP0.
Page 927 V850E2/PG4-L Section 16 TPBA 16.5.2 Compare Register Rewrite Operation The following registers are rewritten by reload. • TPBAnCMP0 • TPBAnCMP1 • TPBAnTOL Reload mode Writing to TPBAnRDT enables reload of the registers corresponding to the set (simultaneous bits (sets the reload request flag (TPBAnRSF.TPBAnRSFk)), and the values of rewrite function) all the pertinent registers are updated simultaneously at the next reload timing (reload).
Page 928 V850E2/PG4-L Section 16 TPBA Setting Flow for Registers to Be Reloaded The rewritten values of the registers to be reloaded (TPBAnCMP0, TPBAnCMP1, and TPBAnTOL) can be transferred to the respective buffer registers simultaneously at the reload timing. START Initial setting •...
Page 929 V850E2/PG4-L Section 16 TPBA 16-bit counter Reload timing TPBAnCMP0 Updated simultaneously at reload timing. TPBAnCB0 TPBAnRDT0 Reload request flag is set. Reload request flag is cleared after reloading. TPBAnRSF0 INTTPBAnIPRD Figure 16-3 Simultaneous Rewrite Timing (TPBAnDPS = 0, TPBAnRDM = 0, and TPBAnTOL = 0) R01UH0336EJ0102 Rev.1.02 Page 929 of 1538...
Page 930 V850E2/PG4-L Section 16 TPBA 16.5.3 Duty Rewrite Operation TPBAnBUFm can be rewritten during operation. The rewritten setting is reflected immediately. TPBAnBUFm Setting Flow START Read TPBAnCNT1. Read TPBAnCMP1. Determine whether TPBAnBUFm can be rewritten based on the values of both registers.* Rewritable? Rewrite TPBAnBUFm.
Page 931 V850E2/PG4-L Section 16 TPBA Access to TPBAnBUFm TPBAnBUFm is accessed in 16 bit units. The following shows the access in 16 bits × 64 patterns mode and the access in 8 bits × 128 patterns mode. • In 16 bits × 64 patterns mode (TPBAnDPS = 0) This register is accessed by the CPU in units of one 16-bit pattern.
Page 932 V850E2/PG4-L Section 16 TPBA (3) Relationship between TPBAnCNT1 Read Value and TPBAnBUFm The duty value of the currently output PWM waveform can be obtained by reading the TPBAnCNT1 count value during operation. TPBAnBUFm in which the currently output duty value is stored can be found by one of the following formulas.
Page 933 V850E2/PG4-L Section 16 TPBA 16.5.4 Basic Operation Example Overview A PWM signal is output from the TPBnO pin according to the PWM period set in the TPBAnCMP0 register and duty cycle set in the TPBAnBUF00 to TPBAnBUF63 registers. Prerequisites • Select 16 bits × 64 patterns mode or 8 bits × 128 patterns mode by setting TPBAnDPS.
Page 934 V850E2/PG4-L Section 16 TPBA List of Operations Table 16-20 16-Bit Counter Function Operation Setting Condition 16-bit Start Writing 1 to TPBAnTS or synchronous start trigger counter Clear Compare match of TPBAnCMP0 buffer register and 16-bit counter Stop Writing 1 to TPBAnTT Table 16-21 7-Bit Counter Function Operation...
Page 935 V850E2/PG4-L Section 16 TPBA Table 16-25 Compare Match Timing Compare Match Timing TPBAnCMP0 When the 16-bit counter changes from TPBAnCMP0 to 0000 TPBAnCMP0 When the 7-bit counter changes from TPBAnCMP1 to 00 TPBAnBUFm When the 16-bit counter matches with the buffer register (TPBAnCB2). Table 16-26 Example of Setting Each Timer Output Condition Output Duty...
Page 936 V850E2/PG4-L Section 16 TPBA When a number-of-patterns matched detection interrupt is used as a trigger of the TPBAnCMP0 and TPBAnTOL reload timing (TPBAnIRDM.TPBAnRDM0 = 0 and TPBAnTOL = 0) Pattern period Pattern period Pattern period FFFF 16-bit counter 0000 TPBAnTE TPBAnCMP0 TPBAnCB0 TPBAnCNT1...
Page 937 V850E2/PG4-L Section 16 TPBA When a period-matched detection interrupt is used as a trigger of the TPBAnCMP0 and TPBAnTOL reload timing (TPBAnIRDM.TPBAnRDM0 = 1 and TPBAnTOL = 0) Pattern period Pattern period Pattern period FFFF 16-bit counter 0000 TPBAnTE TPBAnCMP0 TPBAnCB0 TPBAnCNT1 TPBAnCMP1...
Page 938 V850E2/PG4-L Section 17 OS Timer (OSTM) Section 17 OS Timer (OSTM) This section contains a generic description of the OS timer. 17.1 OSTM Features Instances This product has the following number of instances of the OS timer. Table 17-1 Instances of OS timer OS Timer Instances Name...
Page 939 V850E2/PG4-L Section 17 OS Timer (OSTM) I/O signals The I/O signals of the OS timers are listed in the following table. Table 17-5 OSTMn I/O Signals OSTNn Signals Function Connected to OSTM0TTOUT OS timer output OSTM0O OSTM1TTOUT OSTM1O Table 17-6 OSTMn Signal Processing OSTNn Signals Function...
Page 940 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.2 Functional Overview Features The OS timer has the following features. summary • Two operating modes – Interval timer mode – Free-running comparison mode • Two output modes – Software control mode – Timer-output toggling mode •...
Page 941 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.3 Functional Description Each OS timer is a 32-bit timer/counter. The settings for operating mode specify the direction of counting (up or down) and the generation of interrupt requests. 17.3.1 Clock Signal to Drive Counting The clock for counting by the OS timer is defined by the level of the OSTMnTCKE input signal.
Page 942 V850E2/PG4-L Section 17 OS Timer (OSTM) Caution 1. Select a counter-clock-enable signal for OSTMn while the operation of OSTMn is stopped (the OSTMnTE.OSTMnTE bit is 0). Caution 2. After using the IC0CKSELn.IC0CKSELn[13:0] bits to select the counter-clock- enable signal for OSTMn, set the IC0CKSELn.IC0TMENn bit to 1. Caution 3.
Page 943 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.3.2 Output Modes The OS timer has the following output modes. The mode is selected by the setting of the OSTMnTOE.OSTMnTOE bit. • Software control mode (the OSTMnTOE.OSTMnTOE bit is 0) The level on the OSTMnTTOUT signal corresponds to the setting of the OSTMnTO.OSTMnTO bit.
Page 944 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.3.3 Interrupt Request Generation An OSTMnTINT interrupt request is generated whenever the counter reaches 0000 0000 (in interval timer mode) or matches the comparison value (in free- running comparison mode). An interrupt request can also be generated on starting and restarting of the counter.
Page 945 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.3.4 Starting and Stopping the Timer The OS timer is started and stopped as follows. Starting The timer is started in either of the following ways: the timer • setting the OSTMnTS.OSTMnTS bit to 1 or •...
Page 946 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.3.5 Interval Timer Mode Select the interval timer mode when an OS timer is to be used as a reference timer for generating interrupt requests at a fixed interval. Basic Operation in Interval Timer Mode In interval timer mode, the timer counts down from the value specified in the OSTMnCMP register.
Page 947 V850E2/PG4-L Section 17 OS Timer (OSTM) The above timing diagram shows the following operations. 1. The counter starts counting when OSTMnTS.OSTMnTS = 1 or OSTMnTSST is high (if a synchronous start trigger is in use). The counter starts counting-down from the value of OSTMnCMP. If OSTMnCTL.OSTMnMD0 is 1, OSTMnTINT interrupt requests are generated at the start of counting and the OSTMnTTOUT output is toggled.
Page 948 V850E2/PG4-L Section 17 OS Timer (OSTM) Forced restart The counter is forcibly restarted by setting OSTMnTS.OSTMnTS = 1 or by setting the OSTMnTSST signal at the high level (if the synchronous start trigger is in use) during counting. The counter loads the initial value from the OSTMnCMP register and continues counting down.
Page 949 V850E2/PG4-L Section 17 OS Timer (OSTM) Operation when OSTMnCMP = 0000 0000 When OSTMnCMP = 0000 0000 , the OS timer behaves as follows. • When PCLK is selected as the counter clock, the OSTMnTINT interrupt request signal stays fixed to the high level from the start of counting to the end of counting.
Page 950 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.3.6 Free-Running Comparison Mode Basic Operation in Free-Running Comparison Mode In free-running comparison mode, the counter counts up from 0000 0000 FFFF FFFF . An OSTMnTINT interrupt request is output when the current value of the counter matches the value of the OSTMnCMP register. The free- running comparison mode is selected by setting the OSTMnCTL.OSTMnMD1 bit to 1.
Page 951 V850E2/PG4-L Section 17 OS Timer (OSTM) The OSTMnTINT interrupt-generation period depends on the timing for updating of the OSTMnCMP register and the counter value at the time. For the formula to calculate the period for generation of the OSTMnTINT interrupt, refer to the table below. Table 17-7 OSTMnTINT Generation Timing Old Value...
Page 952 V850E2/PG4-L Section 17 OS Timer (OSTM) Operation when OSTMnCMP = 0000 0000 The following figure shows the operation of the OS timer when OSTMnCMP = 0000 0000 , counter-start interrupts are enabled (OSTMnCTL.OSTMnMD0 = 1), and OSTMnTTOUT is in timer-output toggling mode (OSTMnTOE.OSTMnTOE = 1).
Page 953 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.4 Registers This section describes all registers of the OS timer. 17.4.1 OS Timer Registers Overview The OS timer is controlled and operated by the following registers. Table 17-8 List of OS Timer Registers Register Name Symbol Address...
Page 954 V850E2/PG4-L Section 17 OS Timer (OSTM) 17.4.2 OS Timer Registers in Detail OSTMnCMP - OSTM Compare Register Depending on the mode of operation, this register holds the start value for the down-counter or the value for comparison with that of the counter. Access This register is readable/writable in 32-bit units.
Page 955 V850E2/PG4-L Section 17 OS Timer (OSTM) OSTMnCNT - OSTM Counter Register This register indicates the counter value of the timer. Access This register is readable in 32-bit units. Address <OSTMn_base1> + 4 Initial value The initial value depends on the operating mode of the OS timer. Refer to Table 17-11, Correspondence between Operating Mode, Counting Direction and Initial Value.
Page 956 V850E2/PG4-L Section 17 OS Timer (OSTM) OSTMnTO - OSTM Output Register This register is for specifying or reading of the level of the OSTMnTTOUT output signal. Access This register is readable and writable in 8-bit units. Writing can only proceed when the software control mode is selected (OSTMnTOE.OSTMnTOE = 0).
Page 957 V850E2/PG4-L Section 17 OS Timer (OSTM) OSTMnTE - OSTM Count Enable Status Register This register indicates whether the counter is enabled or disabled. Access This register is readable in 8-bit units. Address <OSTMn_base1> + 10 Initial value This register is initialized by a reset from any source. OSTMnTE Table 17-14 OSTMnTE Register Contents...
Page 958 V850E2/PG4-L Section 17 OS Timer (OSTM) OSTMnTS - OSTM Count Start Trigger Register This register starts the counter. Access This register is writable in 8-bit units. It is always read as 00 Address <OSTMn_base1> + 14 Initial value This register is initialized by a reset from any source. OSTMnTS Table 17-15 OSTMnTS Register Contents...
Page 959 V850E2/PG4-L Section 17 OS Timer (OSTM) OSTMnCTL - OSTM Control Register This register specifies the operating mode for the counter and controls the generation of OSTMnTINT interrupt requests when counting starts. Access This register is readable/writable in 8-bit units. Writing to this register is only possible if the counter is disabled (OSTMnTE.OSTMnTE = 0).
Page 960 V850E2/PG4-L Section 17 OS Timer (OSTM) IC0CKSEL0 - OSTM Input Clock Select Function Register 0 This register is used to select the clock-enable signal for the counter clock of OSTM0. Access This register is readable/writable in 16-bit units. Address FF83F000 Initial value 0000 This register is initialized by a reset from any source.
Page 961 V850E2/PG4-L Section 17 OS Timer (OSTM) Caution 1. Select a counter-clock-enable signal for OSTMn while the operation of OSTMn is stopped (the OSTMnTE.OSTMnTE bit is 0). Caution 2. After using the IC0CKSELn.IC0CKSELn[13:0] bits to select the counter-clock- enable signal for OSTMn, set the IC0CKSELn.IC0TMENn bit to 1. Caution 3.
Page 962 V850E2/PG4-L Section 17 OS Timer (OSTM) (10) IC0CKSEL1 - OSTM Input Clock Select Function Register 1 This register is used to select the clock-enable signal for the counter clock of OSTM1. Access This register is readable/writable in 16-bit units. Address FF83F004 Initial value 0000...
Page 963 V850E2/PG4-L Section 17 OS Timer (OSTM) Caution 1. Select a counter-clock-enable signal for OSTMn while the operation of OSTMn is stopped (the OSTMnTE.OSTMnTE bit is 0). Caution 2. After using the IC0CKSELn.IC0CKSELn[13:0] bits to select the counter-clock- enable signal for OSTMn, set the IC0CKSELn.IC0TMENn bit to 1. Caution 3.
Page 964 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Section 18 Encoder Timer (ENCA) 18.1 ENCA Features Instances This product has 1 encoder timer. Table 18-1 Instances of ENCA Encoder Timer Instance Name ENCA0 Instances index n Throughout this section, both of the individual encoder timers are indicated by the index "n"...
Page 965 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Interrupt requests Interrupt requests from ENCAn are listed in the following table: Table 18-4 List of ENCAn Interrupt Requests ENCAn Signals Function Connected to INTENCAnIOV Overflow interrupt Interrupt controller, DMA INTENCAnIUD Underflow interrupt Interrupt controller, DMA INTENCAnI0 Compare match 0 or Interrupt controller, DMA...
Page 966 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.2 Functional Overview Features • Generates a counter control signal from the encoder input signal and summary executes counting in synchronization with PCLK. • Capture function for capturing the counter value with an external trigger signal •...
Page 967 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.2.1 Block Diagram ENCAnUDS ENCAnACL ENCAnCLOV [1:0] ENCAnBCL ENCAnCLUD ENCAnZCL INTENCAnIEC ENCAnEIS ENCAnSCE (encoder clearing interrupt) [1:0] INTENCAnIOV (overflow interrupt) 16-bit counter ENCAnOVF ENCAnE1 Edge INTENCAnIUD (encoder input 1) CKEN (underflow interrupt) ENCAnUFD detector ENCAnCNT ENCAnE0 (encoder input 0)
Page 968 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.3 ENCA Control Registers The ENCAn is controlled and operated by the following registers: Table 18-6 ENCAn Register Overview Register Function Name Address ENCAn capture/compare ENCAnCCR0 <ENCAn_base1> register 0 ENCAn capture/compare ENCAnCCR1 <ENCAn_base1> + 04 register 1 ENCAn counter register ENCAnCNT...
Page 969 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnCTL – ENCA Control Register This register is a 16-bit register that controls operation of the encoder timer. Access This register can be read/written in 16-bit units. Writing to this register during operation is prohibited. Address <ENCAn_base0>...
Page 970 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Table 18-7 ENCAnCTL Register Contents (2/3) Bit Position Bit Name Function ENCAnCTS This bit selects the trigger for capture by the ENCAnCCR1 register. 0: The ENCAnl1 input is the capture trigger. 1: The ENCAnEC input is the capture trigger. Caution: The setting of the ENCAnCTS bit is only valid when ENCAnCRM1 = 1.
Page 971 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Table 18-7 ENCAnCTL Register Contents (3/3) Bit Position Bit Name Function 1, 0 ENCAnUDS1, Along with the inputs on the ENCAnE0 and ENCAnE1 pins, these bits control ENCAnUDS0 whether counting is up or down. ENCAn ENCAn UDS1...
Page 972 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnIOC0 – ENCA I/O Control Register 0 This is an 8-bit register for use to control the valid edge in the input of capture triggers 0 and 1 (i.e. input signals ENCAnI0 and ENCAnI1). Access This register can be read/written in 8-bit units.
Page 973 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnIOC1 – ENCA I/O Control Register 1 This is an 8-bit register that controls the clearing condition and valid edges for the input and clearing input signals from the encoder (ENCAnE0, ENCAnE1 and ENCAnEC). Access This register can be read/written in 8-bit units.
Page 974 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Table 18-9 ENCAnIOC1 Register Contents (2/2) Bit Position Bit Name Function 3, 2 ENCAnECS1, These bits set the valid edge of the encoder-clearing input signal (ENCAnEC). ENCAnECS0 ENCAn ENCAn ECS1 ECS0 Operation Neither edge is detected. Rising edges are detected.
Page 975 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnFLG – ENCA Status Flag Register This 8-bit flag register indicates the state of the timer counter for the encoder. Access This register is read-only and readable in 8-bit units. Address <ENCAn_base1> + 0C Initial value A reset from any source will initialize the bits.
Page 976 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnFGC – ENCA Status Flag Clear Register This register is an 8-bit register that controls clearing of the timer counter status flags in the ENCAnFLG register. Access This register can be written in 8-bit units. This register always returns 00 when read.
Page 977 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnCCR0 – ENCA Capture/Compare Register 0 This register is a 16-bit register that is used in both capture and comparison roles (i.e. to hold captured values or values for use in comparison). Access This register can be read/written in 16-bit units. This register can be written in 16-bit units when used as a comparison register (ENCAnCTL.ENCAnCRM0 = 0).
Page 978 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnCCR1 – ENCA Capture/Compare Register 1 This register is a 16-bit register that is used in both capture and comparison roles (i.e. to hold captured values or values for use in comparison). Access This register can be read/written in 16-bit units. This register can be written in 16-bit units when used as a comparison register (ENCAnCTL.ENCAnCRM1 = 0).
Page 979 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnCNT – ENCA Counter Register This register is a 16-bit timer counter. Access This register can be read/written in 16-bit units. This register can be written only when the counting operation is stopped. Writing to this register during counting operation is invalid. Address <ENCAn_base1>...
Page 980 V850E2/PG4-L Section 18 Encoder Timer (ENCA) ENCAnTE – ENCA Timer Enable Status Register This 8-bit register indicates the state of operation of the encoder timer. Access This register is read-only and readable in 8-bit units. Address <ENCAn_base1> + 14 Initial value A reset from any source will initialize the bits.
Page 981 V850E2/PG4-L Section 18 Encoder Timer (ENCA) (10) ENCAnTS – ENCA Timer Start Trigger Register This 8-bit register controls starting of the encoder timer. Access This register can be read/written in 8-bit units. This register always returns 00 when read. Writing to this register is only valid when ENCAnTE.ENCAnTE = 0.
Page 982 V850E2/PG4-L Section 18 Encoder Timer (ENCA) (11) ENCAnTT – ENCA Timer Stop Trigger Register This 8-bit register controls stopping of the encoder timer. Access This register can be read/written in 8-bit units. This register always returns 00 when read. Address <ENCAn_base1>...
Page 983 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.4 Functional Description The encoder inputs and encoder-clearing input (ENCAnE0, ENCAnE1, and ENCAnEC) control the counter of ENCAn by causing it to count up or down or by clearing it. The ENCAnCCR0 and ENCAnCCR1 registers are available for use as comparison registers or as capture registers.
Page 984 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Timer Counter Initial Value Setting The initial value of the ENCAn counter register (ENCAnCNT) can be set in the counter operation stopped status (ENCAnTE.ENCAnTE = 0). Combinations of compare/capture in ENCAnCCR0 and ENCAnCCR1 are listed in the table below.
Page 985 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Overflow Operation An overflow occurs when up-counting is performed when the counter value is FFFF . When an overflow occurs, an overflow interrupt (INTENCAnIOV) is output, and the overflow flag (ENCAnOVF) is set to "1". The overflow flag (ENCAnOVF) is cleared to "0"...
Page 986 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Underflow Operation An underflow occurs when down-counting is performed when the counter value is 0000 . When an underflow occurs, an underflow interrupt (INTENCAnIUD) is output, and the underflow flag (ENCAnUDF) is set to "1". The underflow flag (ENCAnUDF) is cleared to "0"...
Page 987 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.4.2 Up/Down Control of Timer Counter The setting of the ENCAnCTL.ENCAnUDS[1:0] bits and the phase of the encoder inputs (ENCAnE0 and ENCAnE1) control counting up and down by the timer. When ENCAnCTL.ENCAnUDS[1:0] = 00B Operation Description Signal on the Signal on the...
Page 988 V850E2/PG4-L Section 18 Encoder Timer (ENCA) When ENCAnCTL.ENCAnUDS[1:0] = 01 Description of Operation Signal on the Signal on the Counting ENCAnUDS1 ENCAnUDS0 ENCAnE0 Pin ENCAnE1 Pin Operation Low level Rising edge Counting down Falling edge Both edges High level Rising edge Falling edge Both edges Rising edge...
Page 989 V850E2/PG4-L Section 18 Encoder Timer (ENCA) When ENCAnCTL.ENCAnUDS[1:0] = 10 Description of Operation Signal on the Signal on the Counting ENCAnUDS1 ENCAnUDS0 ENCAnE0 Pin ENCAnE1 Pin Operation Rising edge Low level Counting down Rising edge Falling edge Falling edge Low level Counting up Falling edge Falling edge...
Page 990 V850E2/PG4-L Section 18 Encoder Timer (ENCA) When ENCAnCTL.ENCAnUDS[1:0] = 11 Description of Operation Signal on the Signal on the Counting ENCAnUDS1 ENCAnUDS0 ENCAnE0 Pin ENCAnE1 Pin Operation Low level Falling edge Counting down Rising edge Low level High level Rising edge Falling edge High level Rising edge...
Page 991 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.4.3 Control of Timer Counter Clearing Any of following condition leads to clearing of the timer counter. Clearing condition Detection of a valid edge of the encoder clearing input signal (signal on the (1): ENCAnEC pin) Clearing condition Level detection of the encoder input and encoder clearing input signals...
Page 992 V850E2/PG4-L Section 18 Encoder Timer (ENCA) (1)-2 Operations for Counter Clearing and Capture in Response to Encoder Clearing Input (ENCAnEC) PCLK ENCAnCSF flag L = counting down Counter clock ENCAnEC pin Underflow occurs ENCAnEC pin: rising-edge detection ENCAnCNT counter 0002 0000 FFFF FFFE...
Page 993 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Clearing in Response to Detection of the Input and Clearing Input Signals from the Encoder Clearing is in accord with the settings of the ENCAnSCE, ENCAnZCL, ENCAnBCL, ENCAnACL, ENCAnECS1 and ENCAnECS0 bits in the ENCAnIOC1 register (when ENCAnIOC1.ENCAnSCE = 1).
Page 994 V850E2/PG4-L Section 18 Encoder Timer (ENCA) When Input on the ENCAnEC Pin Follows Input on the ENCAnE1 Pin during Counting up (When ENCAnIOC1.ENCAnACL = 1, ENCAnIOC1.ENCAnBCL = 0, ENCAnIOC1.ENCAnZCL = 1, and ENCAnCTL.ENCAnUDS[1:0] = 11 ENCAnE0 pin ENCAnE1 pin ENCAnEC pin PCLK register Clearing signal ENCAnCNT register...
Page 995 V850E2/PG4-L Section 18 Encoder Timer (ENCA) When the Timing of Input on the ENCAnEC and ENCAnE1 Pins Coincides during Counting up (When ENCAnIOC1.ENCAnACL = 1, ENCAnIOC1.ENCAnBCL = 0, ENCAnIOC1.ENCAnZCL = 1, and ENCAnCTL.ENCAnUDS[1:0] = 11 ENCAnE0 pin ENCAnE1 pin ENCAnEC pin PCLK Clearing signal ENCAnCNT register...
Page 996 V850E2/PG4-L Section 18 Encoder Timer (ENCA) When Input on the ENCAnEC Pin Follows Input on the ENCAnE1 Pin during Counting down (When ENCAnIOC1.ENCAnACL = 1, ENCAnIOC1.ENCAnBCL = 0, ENCAnIOC1.ENCAnZCL = 1, and ENCAnCTL.ENCAnUDS[1:0] = 11 ENCAnE0 pin ENCAnE1 pin ENCAnEC pin PCLK Clearing signal ENCAnCNT register...
Page 997 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.4.4 Detailed Description of the ENCAnCCR0 Register Compare Function • When ENCAnCTL.ENCAnCRM0 = 0, the ENCAnCCR0 register functions as a dedicated comparison register. • A compare 0 match interrupt (INTENCAnI0) is output when the values in the timer counter and the ENCAnCCR0 register match.
Page 998 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Capture Function • When ENCAnCTL.ENCAnCRM0 = 1, the ENCAnCCR0 register functions as a dedicated capture register. • On detection of the valid edge of capture trigger input 0 (ENCAnI0), the value of the timer counter is stored in the ENCAnCCR0 register. •...
Page 999 V850E2/PG4-L Section 18 Encoder Timer (ENCA) 18.4.5 Detailed Description of the ENCAnCCR1 Register Compare Function • When ENCAnCTL.ENCAnCRM1 = 0, the ENCAnCCR1 register functions as a dedicated comparison register. • A compare 1 match interrupt (INTENCAnI1) is output when the values in the timer counter and the ENCAnCCR1 register match.
Page 1000 V850E2/PG4-L Section 18 Encoder Timer (ENCA) Compare 1 ENCAnCCR1 Match Interrupt Interrupt Mask Cancel Trigger Function Masking Underflow Compare 1 Match Interrupt Occurrence upon Output upon Compare Match ENCAnCRM1 ENCAnCME ENCAnMCS ENCAnLDE = 0 with ENCAnCCR1 — — Outputs compare 1 match (Compare) (Masking (Setting invalid)

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